From: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
To: dev@dpdk.org
Cc: yogesh.jangra@intel.com
Subject: [PATCH V2 4/4] pipeline: add drop port for each pipeline
Date: Sat, 27 Nov 2021 00:02:54 +0000 [thread overview]
Message-ID: <20211127000254.36148-4-cristian.dumitrescu@intel.com> (raw)
In-Reply-To: <20211127000254.36148-1-cristian.dumitrescu@intel.com>
An additional output port is now implicitly created for every pipeline
to serve as the packet drop port. Up to now, the drop port had to be
explicitly created for each pipeline.
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
Signed-off-by: Yogesh Jangra <yogesh.jangra@intel.com>
---
examples/pipeline/cli.c | 15 +++++++++++----
examples/pipeline/examples/fib.cli | 1 -
examples/pipeline/examples/learner.cli | 1 -
examples/pipeline/examples/selector.cli | 1 -
examples/pipeline/examples/varbit.cli | 1 -
examples/pipeline/examples/vxlan.cli | 1 -
examples/pipeline/examples/vxlan_pcap.cli | 1 -
lib/pipeline/rte_swx_pipeline.c | 11 +++++++++++
8 files changed, 22 insertions(+), 10 deletions(-)
diff --git a/examples/pipeline/cli.c b/examples/pipeline/cli.c
index 83b460caf6..c32349e5f0 100644
--- a/examples/pipeline/cli.c
+++ b/examples/pipeline/cli.c
@@ -2551,10 +2551,17 @@ cmd_pipeline_stats(char **tokens,
rte_swx_ctl_pipeline_port_out_stats_read(p->p, i, &stats);
- snprintf(out, out_size, "\tPort %u:"
- " packets %" PRIu64
- " bytes %" PRIu64 "\n",
- i, stats.n_pkts, stats.n_bytes);
+ if (i != info.n_ports_out - 1)
+ snprintf(out, out_size, "\tPort %u:"
+ " packets %" PRIu64
+ " bytes %" PRIu64 "\n",
+ i, stats.n_pkts, stats.n_bytes);
+ else
+ snprintf(out, out_size, "\tDROP:"
+ " packets %" PRIu64
+ " bytes %" PRIu64 "\n",
+ stats.n_pkts, stats.n_bytes);
+
out_size -= strlen(out);
out += strlen(out);
}
diff --git a/examples/pipeline/examples/fib.cli b/examples/pipeline/examples/fib.cli
index b20aed3cf6..93ab2b08f8 100644
--- a/examples/pipeline/examples/fib.cli
+++ b/examples/pipeline/examples/fib.cli
@@ -25,7 +25,6 @@ pipeline PIPELINE0 port out 0 link LINK0 txq 0 bsz 32
pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
-pipeline PIPELINE0 port out 4 sink none
pipeline PIPELINE0 build ./examples/pipeline/examples/fib.spec
diff --git a/examples/pipeline/examples/learner.cli b/examples/pipeline/examples/learner.cli
index af7792624f..688ce34f34 100644
--- a/examples/pipeline/examples/learner.cli
+++ b/examples/pipeline/examples/learner.cli
@@ -25,7 +25,6 @@ pipeline PIPELINE0 port out 0 link LINK0 txq 0 bsz 32
pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
-pipeline PIPELINE0 port out 4 sink none
pipeline PIPELINE0 build ./examples/pipeline/examples/learner.spec
diff --git a/examples/pipeline/examples/selector.cli b/examples/pipeline/examples/selector.cli
index 36f3ead541..123782c57b 100644
--- a/examples/pipeline/examples/selector.cli
+++ b/examples/pipeline/examples/selector.cli
@@ -19,7 +19,6 @@ pipeline PIPELINE0 port out 0 link LINK0 txq 0 bsz 32
pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
-pipeline PIPELINE0 port out 4 sink none
pipeline PIPELINE0 build ./examples/pipeline/examples/selector.spec
diff --git a/examples/pipeline/examples/varbit.cli b/examples/pipeline/examples/varbit.cli
index 0589e32c15..9caeb9ca26 100644
--- a/examples/pipeline/examples/varbit.cli
+++ b/examples/pipeline/examples/varbit.cli
@@ -25,7 +25,6 @@ pipeline PIPELINE0 port out 0 link LINK0 txq 0 bsz 32
pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
-pipeline PIPELINE0 port out 4 sink none
pipeline PIPELINE0 build ./examples/pipeline/examples/varbit.spec
diff --git a/examples/pipeline/examples/vxlan.cli b/examples/pipeline/examples/vxlan.cli
index a3bde6a9f9..444f3f7bd8 100644
--- a/examples/pipeline/examples/vxlan.cli
+++ b/examples/pipeline/examples/vxlan.cli
@@ -19,7 +19,6 @@ pipeline PIPELINE0 port out 0 link LINK0 txq 0 bsz 32
pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
-pipeline PIPELINE0 port out 4 sink none
pipeline PIPELINE0 build ./examples/pipeline/examples/vxlan.spec
pipeline PIPELINE0 table vxlan_table add ./examples/pipeline/examples/vxlan_table.txt
diff --git a/examples/pipeline/examples/vxlan_pcap.cli b/examples/pipeline/examples/vxlan_pcap.cli
index c03dc9303d..83fca8d0d9 100644
--- a/examples/pipeline/examples/vxlan_pcap.cli
+++ b/examples/pipeline/examples/vxlan_pcap.cli
@@ -14,7 +14,6 @@ pipeline PIPELINE0 port out 0 sink none
pipeline PIPELINE0 port out 1 sink none
pipeline PIPELINE0 port out 2 sink none
pipeline PIPELINE0 port out 3 sink none
-pipeline PIPELINE0 port out 4 sink none
pipeline PIPELINE0 build ./examples/pipeline/examples/vxlan.spec
pipeline PIPELINE0 table vxlan_table add ./examples/pipeline/examples/vxlan_table.txt
diff --git a/lib/pipeline/rte_swx_pipeline.c b/lib/pipeline/rte_swx_pipeline.c
index dd914fd935..c332d44bd1 100644
--- a/lib/pipeline/rte_swx_pipeline.c
+++ b/lib/pipeline/rte_swx_pipeline.c
@@ -9199,6 +9199,9 @@ pipeline_compile(struct rte_swx_pipeline *p);
int
rte_swx_pipeline_build(struct rte_swx_pipeline *p)
{
+ struct rte_swx_port_sink_params drop_port_params = {
+ .file_name = NULL,
+ };
int status;
CHECK(p, EINVAL);
@@ -9208,6 +9211,14 @@ rte_swx_pipeline_build(struct rte_swx_pipeline *p)
if (status)
goto error;
+ /* Drop port. */
+ status = rte_swx_pipeline_port_out_config(p,
+ p->n_ports_out,
+ "sink",
+ &drop_port_params);
+ if (status)
+ goto error;
+
status = port_out_build(p);
if (status)
goto error;
--
2.17.1
next prev parent reply other threads:[~2021-11-27 0:03 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-26 23:51 [PATCH 1/4] pipeline: improve the drop instruction Cristian Dumitrescu
2021-11-26 23:51 ` [PATCH 2/4] pipeline: move port type registration to library Cristian Dumitrescu
2021-11-26 23:51 ` [PATCH 3/4] pipeline: move table " Cristian Dumitrescu
2021-11-26 23:51 ` [PATCH 4/4] pipeline: add drop port for each pipeline Cristian Dumitrescu
2021-11-27 0:02 ` [PATCH V2 1/4] pipeline: improve the drop instruction Cristian Dumitrescu
2021-11-27 0:02 ` [PATCH V2 2/4] pipeline: move port type registration to library Cristian Dumitrescu
2021-11-27 0:02 ` [PATCH V2 3/4] pipeline: move table " Cristian Dumitrescu
2021-11-27 0:02 ` Cristian Dumitrescu [this message]
2022-02-13 19:48 ` [PATCH V2 4/4] pipeline: add drop port for each pipeline Thomas Monjalon
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