From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0482FA00C2; Thu, 9 Dec 2021 10:13:52 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8358940F35; Thu, 9 Dec 2021 10:13:52 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id A575640151 for ; Thu, 9 Dec 2021 10:13:50 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1B97bEve009585 for ; Thu, 9 Dec 2021 01:13:49 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=pfpt0220; bh=OJy7WBK8EhR5A1aXG9405So00LTqhEe79PNfkNpLzHk=; b=jxzBBoaVFJ7yHREVhKLc9uMjeacdGPjpjqWXPnSdqxSK309967Vp5wpXdUS2j/GMw9Qh AHLqxtObnyF+/KjeoMwE1d/k8gNPlVeWog4ROc0FTYtqqmZhInZyIqvRT3dmb+50gppp 6KyZZnaLie7dUoxzd+5BoCXnNSPeui932ec7VLwCtAyVoOCT1dZ9BlVR/BFeuKO7Qi1f mI7NZ8MOCHpTJ12bugmFOVnM51fvMVnNgIHEY3vI8w+CwLaF60AWGbsHKHynJCOMNhdh pQOKX+izTVlxRqdIM8OVK7X/ZLIZ3SY4D0Z5AUXTEglJqnPm+ziTQjQoswtXVcvJKxOY dA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3cudjt0anh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 09 Dec 2021 01:13:49 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 9 Dec 2021 01:13:47 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 9 Dec 2021 01:13:47 -0800 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id C1AD23F7054; Thu, 9 Dec 2021 01:13:45 -0800 (PST) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: Subject: [PATCH 1/8] common/cnxk: fix shift offset for tl3 length disable Date: Thu, 9 Dec 2021 14:43:35 +0530 Message-ID: <20211209091342.27017-1-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: 9jOVYu41KN7D-I-u_gSNcklS1wCFjsQ3 X-Proofpoint-GUID: 9jOVYu41KN7D-I-u_gSNcklS1wCFjsQ3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-09_04,2021-12-08_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fix shift offset for length disable flag in NIXX_AF_TL3X_SHAPE register to be 24 instead of zero similar to other level SHAPE registers. Also mask unused bits in adjust value. Fixes: 0885429c3028 ("common/cnxk: add NIX TM hierarchy enable/disable") Signed-off-by: Nithin Dabilpuram Signed-off-by: Satha Rao --- drivers/common/cnxk/roc_nix_tm_utils.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c index 543adf9..9e80c2a 100644 --- a/drivers/common/cnxk/roc_nix_tm_utils.c +++ b/drivers/common/cnxk/roc_nix_tm_utils.c @@ -642,6 +642,7 @@ nix_tm_shaper_reg_prep(struct nix_tm_node *node, else if (profile) adjust = profile->pkt_len_adj; + adjust &= 0x1FF; plt_tm_dbg("Shaper config node %s(%u) lvl %u id %u, " "pir %" PRIu64 "(%" PRIu64 "B)," " cir %" PRIu64 "(%" PRIu64 "B)" @@ -708,7 +709,7 @@ nix_tm_shaper_reg_prep(struct nix_tm_node *node, /* Configure RED algo */ reg[k] = NIX_AF_TL3X_SHAPE(schq); regval[k] = (adjust | (uint64_t)node->red_algo << 9 | - (uint64_t)node->pkt_mode); + (uint64_t)node->pkt_mode << 24); k++; break; -- 2.8.4