From: <pbhagavatula@marvell.com>
To: <jerinj@marvell.com>, Jan Viktorin <viktorin@rehivetech.com>,
Ruifeng Wang <ruifeng.wang@arm.com>,
Bruce Richardson <bruce.richardson@intel.com>
Cc: <dev@dpdk.org>, Pavan Nikhilesh <pbhagavatula@marvell.com>
Subject: [PATCH] config/cn10k: align mempool elements to 128 bytes
Date: Mon, 13 Dec 2021 16:36:14 +0530 [thread overview]
Message-ID: <20211213110615.4458-1-pbhagavatula@marvell.com> (raw)
From: Pavan Nikhilesh <pbhagavatula@marvell.com>
Mempool elements are by default aligned to CACHELINE_SIZE.
In CN10K cacheline size is 64B but the RoC requires buffers to be
aligned to 128B.
Set RTE_MEMPOOL_ALIGN to 128 to force mempool buffers to be aligned
128 bytes.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
config/arm/meson.build | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 213324d262..33afe1a9ad 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -276,7 +276,8 @@ soc_cn10k = {
'implementer' : '0x41',
'flags': [
['RTE_MAX_LCORE', 24],
- ['RTE_MAX_NUMA_NODES', 1]
+ ['RTE_MAX_NUMA_NODES', 1],
+ ['RTE_MEMPOOL_ALIGN', 128]
],
'part_number': '0xd49',
'extra_march_features': ['crypto'],
--
2.17.1
next reply other threads:[~2021-12-13 11:06 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-13 11:06 pbhagavatula [this message]
2021-12-14 9:23 ` Ruifeng Wang
2022-01-20 9:51 ` Jerin Jacob
2022-01-21 9:37 ` Jerin Jacob
2022-02-12 14:14 ` Thomas Monjalon
2021-12-14 10:30 ` Kevin Traynor
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