From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BFB73A034D; Mon, 13 Dec 2021 22:15:40 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 22A4F41148; Mon, 13 Dec 2021 22:15:32 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id BC99141148 for ; Mon, 13 Dec 2021 22:15:30 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 1BDElBZC029954 for ; Mon, 13 Dec 2021 13:15:30 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=+Xa3irZFGXbJkg4esCECZ9meyE9aDXZQNxZiN/8kk3I=; b=MamA9oQrjiA4r1EIztFgVljkjLmFrufQ9EmVP2mWHQ+McdSZ8pRR/iMaT+u/pSRAy41v mo75dA1/PAgGAmf4Mr7IgWW+DDfqjSPdGgKjzIP21pL0hyNuR4mjqdPFNt3RQ5Jkg0kj U8pNLd7bQ0ZWQEa5E9ngq1MMXeCuSXbbqGdOr7QwUOT9P0slS1AwLbBc45SEXYPwSx3l dm1UkKZGY77WXgwUCh/2G4d5y5pNXUhJhNMgaQZMcyKHtEzIrj1MHrGHz5W1vKAR8Dvj UaJAworuVDbqXIPFg/h4f7RsHAYoqUryXeCQLEYjyqsB+qVXImz+lU4mSYgtfEa7Q3VQ 1g== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3cx88ahnmx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 13 Dec 2021 13:15:29 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 13 Dec 2021 13:15:28 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 13 Dec 2021 13:15:28 -0800 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176]) by maili.marvell.com (Postfix) with ESMTP id 9E7F23F704A; Mon, 13 Dec 2021 13:15:26 -0800 (PST) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: Subject: [PATCH 3/4] event/cnxk: disable default wait time for dequeue Date: Tue, 14 Dec 2021 02:44:23 +0530 Message-ID: <20211213211425.6332-3-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20211213211425.6332-1-pbhagavatula@marvell.com> References: <20211213211425.6332-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: g2TmiKQCVKsuVYkoGZK7RDaG7U5WjCTm X-Proofpoint-ORIG-GUID: g2TmiKQCVKsuVYkoGZK7RDaG7U5WjCTm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-13_10,2021-12-13_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Pavan Nikhilesh Setting WAITW bit enables default min dequeue timeout of 1us. Avoid the min dequeue timeout by setting WAITW only when dequeue_timeout is configured. Signed-off-by: Pavan Nikhilesh --- drivers/event/cnxk/cn10k_eventdev.c | 8 +++++-- drivers/event/cnxk/cn9k_eventdev.c | 9 ++++++- drivers/event/cnxk/cn9k_worker.h | 37 +++++++++++++---------------- drivers/event/cnxk/cnxk_eventdev.c | 2 +- drivers/event/cnxk/cnxk_eventdev.h | 2 ++ 5 files changed, 34 insertions(+), 24 deletions(-) diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index c57e45a118..380d1ede69 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -15,7 +15,10 @@ static uint32_t cn10k_sso_gw_mode_wdata(struct cnxk_sso_evdev *dev) { - uint32_t wdata = BIT(16) | 1; + uint32_t wdata = 1; + + if (dev->deq_tmo_ns) + wdata |= BIT(16); switch (dev->gw_mode) { case CN10K_GW_MODE_NONE: @@ -88,7 +91,8 @@ cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base) ws->xaq_lmt = dev->xaq_lmt; /* Set get_work timeout for HWS */ - val = NSEC2USEC(dev->deq_tmo_ns) - 1; + val = NSEC2USEC(dev->deq_tmo_ns); + val = val ? val - 1 : 0; plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM); } diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index 98294be11f..eeacdf9439 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -72,7 +72,8 @@ cn9k_sso_hws_setup(void *arg, void *hws, uintptr_t grp_base) uint64_t val; /* Set get_work tmo for HWS */ - val = dev->deq_tmo_ns ? NSEC2USEC(dev->deq_tmo_ns) - 1 : 0; + val = NSEC2USEC(dev->deq_tmo_ns); + val = val ? val - 1 : 0; if (dev->dual_ws) { dws = hws; dws->grp_base = grp_base; @@ -696,6 +697,9 @@ cn9k_sso_init_hws_mem(void *arg, uint8_t port_id) dws->hws_id = port_id; dws->swtag_req = 0; dws->vws = 0; + if (dev->deq_tmo_ns) + dws->gw_wdata = BIT_ULL(16); + dws->gw_wdata |= 1; data = dws; } else { @@ -714,6 +718,9 @@ cn9k_sso_init_hws_mem(void *arg, uint8_t port_id) ws->base = roc_sso_hws_base_get(&dev->sso, port_id); ws->hws_id = port_id; ws->swtag_req = 0; + if (dev->deq_tmo_ns) + ws->gw_wdata = BIT_ULL(16); + ws->gw_wdata |= 1; data = ws; } diff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h index 0f58e00e7f..32bf2345e7 100644 --- a/drivers/event/cnxk/cn9k_worker.h +++ b/drivers/event/cnxk/cn9k_worker.h @@ -149,10 +149,8 @@ cn9k_wqe_to_mbuf(uint64_t wqe, const uint64_t mbuf, uint8_t port_id, static __rte_always_inline uint16_t cn9k_sso_hws_dual_get_work(uint64_t base, uint64_t pair_base, struct rte_event *ev, const uint32_t flags, - const void *const lookup_mem, - struct cnxk_timesync_info *const tstamp) + struct cn9k_sso_hws_dual *dws) { - const uint64_t set_gw = BIT_ULL(16) | 1; union { __uint128_t get_work; uint64_t u64[2]; @@ -161,7 +159,7 @@ cn9k_sso_hws_dual_get_work(uint64_t base, uint64_t pair_base, uint64_t mbuf; if (flags & NIX_RX_OFFLOAD_PTYPE_F) - rte_prefetch_non_temporal(lookup_mem); + rte_prefetch_non_temporal(dws->lookup_mem); #ifdef RTE_ARCH_ARM64 asm volatile(PLT_CPU_FEATURE_PREAMBLE "rty%=: \n" @@ -175,14 +173,14 @@ cn9k_sso_hws_dual_get_work(uint64_t base, uint64_t pair_base, : [tag] "=&r"(gw.u64[0]), [wqp] "=&r"(gw.u64[1]), [mbuf] "=&r"(mbuf) : [tag_loc] "r"(base + SSOW_LF_GWS_TAG), - [wqp_loc] "r"(base + SSOW_LF_GWS_WQP), [gw] "r"(set_gw), + [wqp_loc] "r"(base + SSOW_LF_GWS_WQP), [gw] "r"(dws->gw_wdata), [pong] "r"(pair_base + SSOW_LF_GWS_OP_GET_WORK0)); #else gw.u64[0] = plt_read64(base + SSOW_LF_GWS_TAG); while ((BIT_ULL(63)) & gw.u64[0]) gw.u64[0] = plt_read64(base + SSOW_LF_GWS_TAG); gw.u64[1] = plt_read64(base + SSOW_LF_GWS_WQP); - plt_write64(set_gw, pair_base + SSOW_LF_GWS_OP_GET_WORK0); + plt_write64(dws->gw_wdata, pair_base + SSOW_LF_GWS_OP_GET_WORK0); mbuf = (uint64_t)((char *)gw.u64[1] - sizeof(struct rte_mbuf)); #endif @@ -202,12 +200,13 @@ cn9k_sso_hws_dual_get_work(uint64_t base, uint64_t pair_base, gw.u64[0] = CNXK_CLR_SUB_EVENT(gw.u64[0]); cn9k_wqe_to_mbuf(gw.u64[1], mbuf, port, gw.u64[0] & 0xFFFFF, flags, - lookup_mem); + dws->lookup_mem); /* Extracting tstamp, if PTP enabled*/ tstamp_ptr = *(uint64_t *)(((struct nix_wqe_hdr_s *) gw.u64[1]) + CNXK_SSO_WQE_SG_PTR); - cnxk_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf, tstamp, + cnxk_nix_mbuf_to_tstamp((struct rte_mbuf *)mbuf, + dws->tstamp, flags & NIX_RX_OFFLOAD_TSTAMP_F, flags & NIX_RX_MULTI_SEG_F, (uint64_t *)tstamp_ptr); @@ -232,9 +231,7 @@ cn9k_sso_hws_get_work(struct cn9k_sso_hws *ws, struct rte_event *ev, uint64_t tstamp_ptr; uint64_t mbuf; - plt_write64(BIT_ULL(16) | /* wait for work. */ - 1, /* Use Mask set 0. */ - ws->base + SSOW_LF_GWS_OP_GET_WORK0); + plt_write64(ws->gw_wdata, ws->base + SSOW_LF_GWS_OP_GET_WORK0); if (flags & NIX_RX_OFFLOAD_PTYPE_F) rte_prefetch_non_temporal(lookup_mem); @@ -532,9 +529,9 @@ NIX_RX_FASTPATH_MODES SSOW_LF_GWS_TAG); \ return 1; \ } \ - gw = cn9k_sso_hws_dual_get_work( \ - dws->base[dws->vws], dws->base[!dws->vws], ev, flags, \ - dws->lookup_mem, dws->tstamp); \ + gw = cn9k_sso_hws_dual_get_work(dws->base[dws->vws], \ + dws->base[!dws->vws], ev, \ + flags, dws); \ dws->vws = !dws->vws; \ return gw; \ } @@ -558,14 +555,14 @@ NIX_RX_FASTPATH_MODES SSOW_LF_GWS_TAG); \ return ret; \ } \ - ret = cn9k_sso_hws_dual_get_work( \ - dws->base[dws->vws], dws->base[!dws->vws], ev, flags, \ - dws->lookup_mem, dws->tstamp); \ + ret = cn9k_sso_hws_dual_get_work(dws->base[dws->vws], \ + dws->base[!dws->vws], ev, \ + flags, dws); \ dws->vws = !dws->vws; \ for (iter = 1; iter < timeout_ticks && (ret == 0); iter++) { \ - ret = cn9k_sso_hws_dual_get_work( \ - dws->base[dws->vws], dws->base[!dws->vws], ev, \ - flags, dws->lookup_mem, dws->tstamp); \ + ret = cn9k_sso_hws_dual_get_work(dws->base[dws->vws], \ + dws->base[!dws->vws], \ + ev, flags, dws); \ dws->vws = !dws->vws; \ } \ return ret; \ diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index 6ad4e23e2b..be021d86c9 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -610,7 +610,7 @@ cnxk_sso_init(struct rte_eventdev *event_dev) } dev->is_timeout_deq = 0; - dev->min_dequeue_timeout_ns = USEC2NSEC(1); + dev->min_dequeue_timeout_ns = 0; dev->max_dequeue_timeout_ns = USEC2NSEC(0x3FF); dev->max_num_events = -1; dev->nb_event_queues = 0; diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index ab58508590..e3b5ffa7eb 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -144,6 +144,7 @@ struct cn10k_sso_hws { /* Event port a.k.a GWS */ struct cn9k_sso_hws { uint64_t base; + uint64_t gw_wdata; /* PTP timestamp */ struct cnxk_timesync_info *tstamp; void *lookup_mem; @@ -160,6 +161,7 @@ struct cn9k_sso_hws { struct cn9k_sso_hws_dual { uint64_t base[2]; /* Ping and Pong */ + uint64_t gw_wdata; /* PTP timestamp */ struct cnxk_timesync_info *tstamp; void *lookup_mem; -- 2.17.1