From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 71C29A0353; Fri, 21 Jan 2022 13:04:41 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EC96142753; Fri, 21 Jan 2022 13:04:40 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 6D41440042; Fri, 21 Jan 2022 13:04:39 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 20LARhgC029262; Fri, 21 Jan 2022 04:04:38 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=HthvfotntoVL5qoOAVpSBYvkErQZmgt+d5UBr3oe3v8=; b=TLTQsq6ad/9otxeyysySge4wZ1ns93TJ68TR8rxwjWAsF1fC1H5PER/6tRN2kuHpOfju wplS1arT6D2HSXUHYxSjwayvw3tA763/K/dWSUD/zn0TH8pQMeGIlotzvf9z1FRY8ke4 aPJMhJWViKkrDlpWpph5nSI2P1YvFTaNU+i1U0DE3isuOX8z917vyUltyepXqLvdMn3I lRVgB+hKlHkeZ7pNfF/HcoYhIsqbC3m2hCrzcwv8VlJpGW+ajmtAzPpJDlff4+kz89B0 icvkPOoGsV4+yaPVl3YE+uk2adpb8W2NBJFmsDNdP4zCE1gWWk2eFtNDAEuXhd2YxZNJ UA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3dqj05hu13-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 21 Jan 2022 04:04:38 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 21 Jan 2022 04:04:36 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Fri, 21 Jan 2022 04:04:36 -0800 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id A14513F709E; Fri, 21 Jan 2022 04:04:33 -0800 (PST) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , , Subject: [PATCH v2 01/10] common/cnxk: fix shift offset for TL3 length disable Date: Fri, 21 Jan 2022 17:34:15 +0530 Message-ID: <20220121120424.28166-1-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20211209091342.27017-1-ndabilpuram@marvell.com> References: <20211209091342.27017-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: HwXXWSxyimjiLJ9NVZpBKpdO5Lsyo0SK X-Proofpoint-ORIG-GUID: HwXXWSxyimjiLJ9NVZpBKpdO5Lsyo0SK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-21_06,2022-01-21_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fix shift offset for length disable flag in NIXX_AF_TL3X_SHAPE register to be 24 instead of zero similar to other level SHAPE registers. Also mask unused bits in adjust value. Fixes: 0885429c3028 ("common/cnxk: add NIX TM hierarchy enable/disable") Cc: stable@dpdk.org Signed-off-by: Nithin Dabilpuram Signed-off-by: Satha Rao --- v2: - Updated series from Jerin - Handle comments from Ferruh in patch 3/8. - Split patch 6/8 to two patches - Split patch 7/8 to two patches drivers/common/cnxk/roc_nix_tm_utils.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c index 543adf9..9e80c2a 100644 --- a/drivers/common/cnxk/roc_nix_tm_utils.c +++ b/drivers/common/cnxk/roc_nix_tm_utils.c @@ -642,6 +642,7 @@ nix_tm_shaper_reg_prep(struct nix_tm_node *node, else if (profile) adjust = profile->pkt_len_adj; + adjust &= 0x1FF; plt_tm_dbg("Shaper config node %s(%u) lvl %u id %u, " "pir %" PRIu64 "(%" PRIu64 "B)," " cir %" PRIu64 "(%" PRIu64 "B)" @@ -708,7 +709,7 @@ nix_tm_shaper_reg_prep(struct nix_tm_node *node, /* Configure RED algo */ reg[k] = NIX_AF_TL3X_SHAPE(schq); regval[k] = (adjust | (uint64_t)node->red_algo << 9 | - (uint64_t)node->pkt_mode); + (uint64_t)node->pkt_mode << 24); k++; break; -- 2.8.4