From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BDDC2A0353; Fri, 21 Jan 2022 13:05:01 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E387842773; Fri, 21 Jan 2022 13:04:51 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 2C3CC42761 for ; Fri, 21 Jan 2022 13:04:50 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 20LAM30q029289; Fri, 21 Jan 2022 04:04:49 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=iLFFmIrFk7w2c24OLwzI0YZl2bTEv8bUdY8E6SfJiYE=; b=LwAw7pFzkh1K/msJnphdm7mE3tCzJZPFsxZMxdD7FRGiOL9NjkhLQGLrLMyK2T6cEysy szcKVw1/N1z9YagutJl5GAYKHPTxcicfaZeQd/ZHIbNYJbkfl2AhfcpKAJxbiOslTAy3 HGp7PIlSUKxvpols3wg+83yTY/99d5e8RDwQJ67ZliOUxC1o6Q4w1nr2ilPsiE6Ib3kB uLmU4to5+dMgIDDNiuIx2hqm5rJt4PlGyPpUzwjznO4t5cF+FrkfcmxJNbkmQLoi2xej sI+dXoURI/5NoC+bK3EwLZWWw4hWNuxWmuqqOQSqlIC/UoyqqW18OVlDIZ0WjoeSTNjr BQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3dqj05hu1n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 21 Jan 2022 04:04:49 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 21 Jan 2022 04:04:47 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 21 Jan 2022 04:04:47 -0800 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 7E21F3F708F; Fri, 21 Jan 2022 04:04:44 -0800 (PST) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , , Harman Kalra Subject: [PATCH v2 04/10] common/cnxk: reset stale values on error debug registers Date: Fri, 21 Jan 2022 17:34:18 +0530 Message-ID: <20220121120424.28166-4-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220121120424.28166-1-ndabilpuram@marvell.com> References: <20211209091342.27017-1-ndabilpuram@marvell.com> <20220121120424.28166-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: fa6cRZKSlGilIHGWoCDITYREfEsLI_38 X-Proofpoint-ORIG-GUID: fa6cRZKSlGilIHGWoCDITYREfEsLI_38 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-21_06,2022-01-21_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Harman Kalra LF's error debug registers like NIX_LF_SQ_OP_ERR_DBG, NIX_LF_MNQ_ERR_DBG, NIX_LF_SEND_ERR_DBG captures debug info for an error detected during LMT operation or meta enqueue or after meta enqueue granted respectively. HW sets a valid bit when info is captured and SW is expected to clear this valid bit by writing 1, else these registers will show stale values of first interrupt when occurred and will never update with subsequent interrupts. Signed-off-by: Harman Kalra Acked-by: Jerin Jacob --- drivers/common/cnxk/roc_nix_irq.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_nix_irq.c b/drivers/common/cnxk/roc_nix_irq.c index a5cd9d4..7dcd533 100644 --- a/drivers/common/cnxk/roc_nix_irq.c +++ b/drivers/common/cnxk/roc_nix_irq.c @@ -202,9 +202,12 @@ nix_lf_sq_debug_reg(struct nix *nix, uint32_t off) uint64_t reg; reg = plt_read64(nix->base + off); - if (reg & BIT_ULL(44)) + if (reg & BIT_ULL(44)) { plt_err("SQ=%d err_code=0x%x", (int)((reg >> 8) & 0xfffff), (uint8_t)(reg & 0xff)); + /* Clear valid bit */ + plt_write64(BIT_ULL(44), nix->base + off); + } } static void -- 2.8.4