From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 25746A0353; Fri, 21 Jan 2022 13:05:07 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CDE0542766; Fri, 21 Jan 2022 13:04:54 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 4024A42766 for ; Fri, 21 Jan 2022 13:04:53 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 20LB3uAI015213; Fri, 21 Jan 2022 04:04:52 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=CIX8utzXIoVwLBpN56rlShHO/+I9FVTFOgZjWz7+0L0=; b=Qt1XFCio+Ikp5fJXJ3fVPAHffc6XzkNjgrInSjn+0EqnGokcD1KCfd+JABjsVDcdxf5B b09UHzzKPF8cT1hOv15ei/A2XQR3C16XDBSMp6CScQjGnXQofGyycEbstjhr4jZZq2kY kiqqCL/du4BdlUfCKViOXG5cJruWmfs0K4hwZiBdQRmFKLtORDS62rjEiFDokd/Bi1aV CIBExZP9wj5s9bjteSgp4ksgGwCP5D+OGtzcgiD8FYnDbzTZXw4gpDmSUOWoKnhylkcf k3s7afCSpfZBmNl+vCqukMf8mYQ5//BJStNIpp9c2icKBj5wO+6L6HeK8Qo0O0YSECEQ BA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3dqhytsw81-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 21 Jan 2022 04:04:52 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 21 Jan 2022 04:04:50 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Fri, 21 Jan 2022 04:04:50 -0800 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id F34573F7095; Fri, 21 Jan 2022 04:04:47 -0800 (PST) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , , Harman Kalra Subject: [PATCH v2 05/10] common/cnxk: always use single interrupt ID with NIX Date: Fri, 21 Jan 2022 17:34:19 +0530 Message-ID: <20220121120424.28166-5-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220121120424.28166-1-ndabilpuram@marvell.com> References: <20211209091342.27017-1-ndabilpuram@marvell.com> <20220121120424.28166-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: MsklzfoZUHO-wWN8qsRBwQjRAcZ5HdNt X-Proofpoint-GUID: MsklzfoZUHO-wWN8qsRBwQjRAcZ5HdNt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-21_06,2022-01-21_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Harman Kalra An errata exists whereby, in certain cases NIX may use an incorrect QINT_IDX for SQ interrupts. As a result, the interrupt may not be delivered to software, or may not be associated with the correct SQ. When NIX uses an incorrect QINT_IDX : 1. NIX_LF_QINT(0..63)_CNT[COUNT] will be incremented for incorrect QINT. 2. NIX_LF_QINT(0..63)_INT[INTR] will be set for incorrect QINT. Signed-off-by: Harman Kalra Acked-by: Jerin Jacob --- drivers/common/cnxk/roc_nix_queue.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index c638cd4..80e1c9f 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -690,7 +690,11 @@ sq_cn9k_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum, aq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR); /* Many to one reduction */ - aq->sq.qint_idx = sq->qid % nix->qints; + /* Assigning QINT 0 to all the SQs, an errata exists where NIXTX can + * send incorrect QINT_IDX when reporting queue interrupt (QINT). This + * might result in software missing the interrupt. + */ + aq->sq.qint_idx = 0; } static int @@ -789,8 +793,11 @@ sq_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum, aq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR); aq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR); - /* Many to one reduction */ - aq->sq.qint_idx = sq->qid % nix->qints; + /* Assigning QINT 0 to all the SQs, an errata exists where NIXTX can + * send incorrect QINT_IDX when reporting queue interrupt (QINT). This + * might result in software missing the interrupt. + */ + aq->sq.qint_idx = 0; } static int -- 2.8.4