From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id ABD28A0353; Fri, 21 Jan 2022 13:05:25 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AA3AF4275E; Fri, 21 Jan 2022 13:05:05 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id D83E84277F for ; Fri, 21 Jan 2022 13:05:03 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 20LAASCO015148; Fri, 21 Jan 2022 04:05:03 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=RszvQ29BerGRPfLov0lSI8CYcYdvl/9daNyzVgly6JM=; b=K2bwjWnwyXo4NDq+lSzKMh76pipNi+GAGCVtv2GbWv5cfKrB3OwcdhKUESsEUehlu3Lf BtpR4BiM3GOspMwTiAY/jKGbtsMdgSxtEoKnXXgDqM1fUc0T/lDaUzL2koVEXNh0xZc3 Uf/MhGTI5T3G824SzbCCKNFgi9G2Ph9ZsiFlX97gB5Ik1kNDYbWvyJg7YLQoPRxpK6Tg 565+uzJBTjDNENnIwMnhnp1PSTxE/VIzKJadllKb1wpAhgF8NT1vFiHMOyr4jw3YN7Bl 1vF1+5I1Whyn+JFwU8nzg3kbpMA8OVo+ByrqVkVqthtrnUQVeR/XQY9VT+aOvESY72XG Ug== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3dqhytsw94-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 21 Jan 2022 04:05:02 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 21 Jan 2022 04:05:01 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 21 Jan 2022 04:05:01 -0800 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id E41D53F708F; Fri, 21 Jan 2022 04:04:58 -0800 (PST) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH v2 08/10] net/cnxk: improve inbound inline error handling for cn9k Date: Fri, 21 Jan 2022 17:34:22 +0530 Message-ID: <20220121120424.28166-8-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220121120424.28166-1-ndabilpuram@marvell.com> References: <20211209091342.27017-1-ndabilpuram@marvell.com> <20220121120424.28166-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: uIEG-QMRse4SzogC_dU3eZxDulHXWtxn X-Proofpoint-GUID: uIEG-QMRse4SzogC_dU3eZxDulHXWtxn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-21_06,2022-01-21_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Improve inbound inline error handling for CN9K in terms of packet delivered to application for different kinds of errors. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_ie_on.h | 16 ++++++++++++- drivers/net/cnxk/cn9k_rx.h | 50 +++++++++++++++++++++++++++++++++++++++-- 2 files changed, 63 insertions(+), 3 deletions(-) diff --git a/drivers/common/cnxk/roc_ie_on.h b/drivers/common/cnxk/roc_ie_on.h index 53591c6..376e698 100644 --- a/drivers/common/cnxk/roc_ie_on.h +++ b/drivers/common/cnxk/roc_ie_on.h @@ -188,7 +188,21 @@ struct roc_ie_on_inb_sa { #define ROC_IE_ONF_MAJOR_OP_PROCESS_INBOUND_IPSEC 0x26UL /* Ucode completion codes */ -#define ROC_IE_ONF_UCC_SUCCESS 0 +#define ROC_IE_ON_UCC_SUCCESS 0 +#define ROC_IE_ON_UCC_ENC_TYPE_ERR 0xB1 +#define ROC_IE_ON_UCC_IP_VER_ERR 0xB2 +#define ROC_IE_ON_UCC_PROTO_ERR 0xB3 +#define ROC_IE_ON_UCC_CTX_INVALID 0xB4 +#define ROC_IE_ON_UCC_CTX_DIR_MISMATCH 0xB5 +#define ROC_IE_ON_UCC_IP_PAYLOAD_TYPE_ERR 0xB6 +#define ROC_IE_ON_UCC_CTX_FLAG_MISMATCH 0xB7 +#define ROC_IE_ON_UCC_SPI_MISMATCH 0xBE +#define ROC_IE_ON_UCC_IP_CHKSUM_ERR 0xBF +#define ROC_IE_ON_UCC_AUTH_ERR 0xC3 +#define ROC_IE_ON_UCC_PADDING_INVALID 0xC4 +#define ROC_IE_ON_UCC_SA_MISMATCH 0xCC +#define ROC_IE_ON_UCC_L2_HDR_INFO_ERR 0xCF +#define ROC_IE_ON_UCC_L2_HDR_LEN_ERR 0xE0 struct roc_ie_onf_sa_ctl { uint32_t spi; diff --git a/drivers/net/cnxk/cn9k_rx.h b/drivers/net/cnxk/cn9k_rx.h index 225bb41..cbb6299 100644 --- a/drivers/net/cnxk/cn9k_rx.h +++ b/drivers/net/cnxk/cn9k_rx.h @@ -211,6 +211,52 @@ ipsec_antireplay_check(struct roc_onf_ipsec_inb_sa *sa, return rc; } +static inline uint64_t +nix_rx_sec_mbuf_err_update(const union nix_rx_parse_u *rx, uint16_t res, + uint64_t *rearm_val, uint16_t *len) +{ + uint8_t uc_cc = res >> 8; + uint8_t cc = res & 0xFF; + uint64_t data_off; + uint64_t ol_flags; + uint16_t m_len; + + if (unlikely(cc != CPT_COMP_GOOD)) + return RTE_MBUF_F_RX_SEC_OFFLOAD | + RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED; + + data_off = *rearm_val & (BIT_ULL(16) - 1); + m_len = rx->cn9k.pkt_lenm1 + 1; + + switch (uc_cc) { + case ROC_IE_ON_UCC_IP_PAYLOAD_TYPE_ERR: + case ROC_IE_ON_UCC_AUTH_ERR: + case ROC_IE_ON_UCC_PADDING_INVALID: + /* Adjust data offset to start at copied L2 */ + data_off += ROC_ONF_IPSEC_INB_SPI_SEQ_SZ + + ROC_ONF_IPSEC_INB_MAX_L2_SZ; + ol_flags = RTE_MBUF_F_RX_SEC_OFFLOAD | + RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED; + break; + case ROC_IE_ON_UCC_CTX_INVALID: + case ROC_IE_ON_UCC_SPI_MISMATCH: + case ROC_IE_ON_UCC_SA_MISMATCH: + /* Return as normal packet */ + ol_flags = 0; + break; + default: + /* Return as error packet after updating packet lengths */ + ol_flags = RTE_MBUF_F_RX_SEC_OFFLOAD | + RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED; + break; + } + + *len = m_len; + *rearm_val = *rearm_val & ~(BIT_ULL(16) - 1); + *rearm_val |= data_off; + return ol_flags; +} + static __rte_always_inline uint64_t nix_rx_sec_mbuf_update(const struct nix_cqe_hdr_s *cq, struct rte_mbuf *m, uintptr_t sa_base, uint64_t *rearm_val, uint16_t *len) @@ -236,8 +282,8 @@ nix_rx_sec_mbuf_update(const struct nix_cqe_hdr_s *cq, struct rte_mbuf *m, rte_prefetch0((void *)data); - if (unlikely(res != (CPT_COMP_GOOD | ROC_IE_ONF_UCC_SUCCESS << 8))) - return RTE_MBUF_F_RX_SEC_OFFLOAD | RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED; + if (unlikely(res != (CPT_COMP_GOOD | ROC_IE_ON_UCC_SUCCESS << 8))) + return nix_rx_sec_mbuf_err_update(rx, res, rearm_val, len); data += lcptr; /* 20 bits of tag would have the SPI */ -- 2.8.4