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From: <ssebasti@amd.com>
To: <dev@dpdk.org>
Subject: [PATCH v2 6/6] net/axgbe: alter the port speed bit range
Date: Tue, 25 Jan 2022 17:47:47 +0530	[thread overview]
Message-ID: <20220125121747.344631-7-ssebasti@amd.com> (raw)
In-Reply-To: <20220125121747.344631-1-ssebasti@amd.com>

From: Selwin Sebastian <selwin.sebastian@amd.com>

Newer generation Hardware uses the slightly different
port speed bit widths, so alter the existing port speed
bit range to extend support to the newer generation hardware
while maintaining the backward compatibility with older
generation hardware.

The previously reserved bits are now being used which
then requires the adjustment to the BIT values, e.g.:

Before:
   PORT_PROPERTY_0[22:21] - Reserved
   PORT_PROPERTY_0[26:23] - Supported Speeds

After:
   PORT_PROPERTY_0[21] - Reserved
   PORT_PROPERTY_0[26:22] - Supported Speeds

To make this backwards compatible, the existing BIT
definitions for the port speeds are incremented by one
to maintain the original position.

Signed-off-by: Selwin Sebastian <selwin.sebastian@amd.com>
---
 drivers/net/axgbe/axgbe_common.h   | 4 ++--
 drivers/net/axgbe/axgbe_phy_impl.c | 8 ++++----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
index a5431dd998..5310ac54f5 100644
--- a/drivers/net/axgbe/axgbe_common.h
+++ b/drivers/net/axgbe/axgbe_common.h
@@ -1032,8 +1032,8 @@
 #define XP_PROP_0_PORT_ID_WIDTH			8
 #define XP_PROP_0_PORT_MODE_INDEX		8
 #define XP_PROP_0_PORT_MODE_WIDTH		4
-#define XP_PROP_0_PORT_SPEEDS_INDEX		23
-#define XP_PROP_0_PORT_SPEEDS_WIDTH		4
+#define XP_PROP_0_PORT_SPEEDS_INDEX		22
+#define XP_PROP_0_PORT_SPEEDS_WIDTH		5
 #define XP_PROP_1_MAX_RX_DMA_INDEX		24
 #define XP_PROP_1_MAX_RX_DMA_WIDTH		5
 #define XP_PROP_1_MAX_RX_QUEUES_INDEX		8
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c
index b0e1c267b1..d97fbbfddd 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -7,10 +7,10 @@
 #include "axgbe_common.h"
 #include "axgbe_phy.h"
 
-#define AXGBE_PHY_PORT_SPEED_100	BIT(0)
-#define AXGBE_PHY_PORT_SPEED_1000	BIT(1)
-#define AXGBE_PHY_PORT_SPEED_2500	BIT(2)
-#define AXGBE_PHY_PORT_SPEED_10000	BIT(3)
+#define AXGBE_PHY_PORT_SPEED_100	BIT(1)
+#define AXGBE_PHY_PORT_SPEED_1000	BIT(2)
+#define AXGBE_PHY_PORT_SPEED_2500	BIT(3)
+#define AXGBE_PHY_PORT_SPEED_10000	BIT(4)
 
 #define AXGBE_MUTEX_RELEASE		0x80000000
 
-- 
2.25.1


  parent reply	other threads:[~2022-01-25 12:20 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-25 12:17 [PATCH v2 0/6] axgbe pmd updates ssebasti
2022-01-25 12:17 ` [PATCH v2 1/6] net/axgbe: always attempt link training in KR mode ssebasti
2022-01-27 13:45   ` Namburu, Chandu-babu
2022-01-25 12:17 ` [PATCH v2 2/6] net/axgbe: toggle PLL settings during rate change ssebasti
2022-01-27 13:39   ` Namburu, Chandu-babu
2022-01-25 12:17 ` [PATCH v2 3/6] net/axgbe: simplify mailbox interface rate change code ssebasti
2022-01-27 13:39   ` Namburu, Chandu-babu
2022-01-25 12:17 ` [PATCH v2 4/6] net/axgbe: reset PHY Rx when mailbox command timeout ssebasti
2022-01-27 13:39   ` Namburu, Chandu-babu
2022-01-25 12:17 ` [PATCH v2 5/6] net/axgbe: add support for new port mode ssebasti
2022-01-27 13:39   ` Namburu, Chandu-babu
2022-01-25 12:17 ` ssebasti [this message]
2022-01-25 16:21   ` [PATCH v2 6/6] net/axgbe: alter the port speed bit range Namburu, Chandu-babu
2022-01-27 14:31     ` Ferruh Yigit
2022-01-25 12:47 ` [PATCH v2 0/6] axgbe pmd updates Ferruh Yigit
2022-01-25 12:50 ` Ferruh Yigit

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