From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id CCB12A0353; Mon, 31 Jan 2022 11:52:42 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 520A040E25; Mon, 31 Jan 2022 11:52:42 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id E18614069D for ; Mon, 31 Jan 2022 11:52:40 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 20UKxfjB013892; Mon, 31 Jan 2022 02:52:40 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=/nPZTYd0DF8Hm2w6rjKqGEg/8B80Ngv+1KJlOnjC0AM=; b=X8fxFNgXpk6soa/FxBjEa3LQF4b3BKxsdxyVdtQRgUPN3YyCTyaf3tzGrZjRWBOJmXTH g/ssKmndJRkGGv5RgV01P1Q3RQmvxxQX2MK2PpU1wVnapHY7AezCQ08dYUAPQ+zlwweL yUKAr7ZZyLo5jfFCRoYT502T6MAVoTjAq+9LjzKsQM8CZQOOcLo4A7fz5V+bfmZ3AWMi eeW3arBhoZbr2OTYhotHOI1uokh9XHcoULIiv/QW8p4x10DAHqrCw4+PTALqGSGLhJJg r2FUaUV1pmfBr18ojQirI/27WkTZvjZiL7RXeT9GJrManOfKAKO5nfoDRWxbY6ZCqDWL Mw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3dw5yqm4hw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 31 Jan 2022 02:52:40 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 Jan 2022 02:52:38 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 31 Jan 2022 02:52:38 -0800 Received: from localhost.marvell.com (unknown [10.29.52.211]) by maili.marvell.com (Postfix) with ESMTP id 626D53F7050; Mon, 31 Jan 2022 02:52:36 -0800 (PST) From: Harman Kalra To: , , CC: Harman Kalra Subject: [PATCH v2] common/cnxk: enable NIX Tx interrupts errata Date: Mon, 31 Jan 2022 16:22:10 +0530 Message-ID: <20220131105210.183152-1-hkalra@marvell.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220113121807.187105-1-hkalra@marvell.com> References: <20220113121807.187105-1-hkalra@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: WcjmOPYalKiYVLO248l_GK40EdXiSzmL X-Proofpoint-GUID: WcjmOPYalKiYVLO248l_GK40EdXiSzmL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-31_04,2022-01-28_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org An errata exists whereby NIX may incorrectly overwrite the value in NIX_SQ_CTX_S[SQ_INT]. This may cause set interrupts to get cleared or causing an QINT when no error is outstanding. As a workaround, software should always read all SQ debug registers and not just rely on NIX_SQINT_E bits set in NIX_SQ_CTX_S[SQ_INT]. Also for detecting SQB faults software must read SQ context and check id next_sqb is NULL. Signed-off-by: Harman Kalra --- V2: * Rebase on branch code drivers/common/cnxk/roc_nix_irq.c | 64 ++++++++++++++++++++++--------- 1 file changed, 46 insertions(+), 18 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_irq.c b/drivers/common/cnxk/roc_nix_irq.c index 7dcd533ea9..71971ef261 100644 --- a/drivers/common/cnxk/roc_nix_irq.c +++ b/drivers/common/cnxk/roc_nix_irq.c @@ -196,18 +196,42 @@ nix_lf_sq_irq_get_and_clear(struct nix *nix, uint16_t sq) return nix_lf_q_irq_get_and_clear(nix, sq, NIX_LF_SQ_OP_INT, ~0x1ff00); } -static inline void +static inline bool +nix_lf_is_sqb_null(struct dev *dev, int q) +{ + bool is_sqb_null = false; + volatile void *ctx; + int rc; + + rc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_SQ, q, &ctx); + if (rc) { + plt_err("Failed to get sq context"); + } else { + is_sqb_null = + roc_model_is_cn9k() ? + (((__io struct nix_sq_ctx_s *)ctx)->next_sqb == + 0) : + (((__io struct nix_cn10k_sq_ctx_s *)ctx) + ->next_sqb == 0); + } + + return is_sqb_null; +} + +static inline uint8_t nix_lf_sq_debug_reg(struct nix *nix, uint32_t off) { + uint8_t err = 0; uint64_t reg; reg = plt_read64(nix->base + off); if (reg & BIT_ULL(44)) { - plt_err("SQ=%d err_code=0x%x", (int)((reg >> 8) & 0xfffff), - (uint8_t)(reg & 0xff)); + err = reg & 0xff; /* Clear valid bit */ plt_write64(BIT_ULL(44), nix->base + off); } + + return err; } static void @@ -229,6 +253,7 @@ nix_lf_q_irq(void *param) struct dev *dev = &nix->dev; int q, cq, rq, sq; uint64_t intr; + uint8_t rc; intr = plt_read64(nix->base + NIX_LF_QINTX_INT(qintx)); if (intr == 0) @@ -269,22 +294,25 @@ nix_lf_q_irq(void *param) sq = q % nix->qints; irq = nix_lf_sq_irq_get_and_clear(nix, sq); - if (irq & BIT_ULL(NIX_SQINT_LMT_ERR)) { - plt_err("SQ=%d NIX_SQINT_LMT_ERR", sq); - nix_lf_sq_debug_reg(nix, NIX_LF_SQ_OP_ERR_DBG); - } - if (irq & BIT_ULL(NIX_SQINT_MNQ_ERR)) { - plt_err("SQ=%d NIX_SQINT_MNQ_ERR", sq); - nix_lf_sq_debug_reg(nix, NIX_LF_MNQ_ERR_DBG); - } - if (irq & BIT_ULL(NIX_SQINT_SEND_ERR)) { - plt_err("SQ=%d NIX_SQINT_SEND_ERR", sq); - nix_lf_sq_debug_reg(nix, NIX_LF_SEND_ERR_DBG); - } - if (irq & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) { + /* Detect LMT store error */ + rc = nix_lf_sq_debug_reg(nix, NIX_LF_SQ_OP_ERR_DBG); + if (rc) + plt_err("SQ=%d NIX_SQINT_LMT_ERR, errcode %x", sq, rc); + + /* Detect Meta-descriptor enqueue error */ + rc = nix_lf_sq_debug_reg(nix, NIX_LF_MNQ_ERR_DBG); + if (rc) + plt_err("SQ=%d NIX_SQINT_MNQ_ERR, errcode %x", sq, rc); + + /* Detect Send error */ + rc = nix_lf_sq_debug_reg(nix, NIX_LF_SEND_ERR_DBG); + if (rc) + plt_err("SQ=%d NIX_SQINT_SEND_ERR, errcode %x", sq, rc); + + /* Detect SQB fault, read SQ context to check SQB NULL case */ + if (irq & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL) || + nix_lf_is_sqb_null(dev, q)) plt_err("SQ=%d NIX_SQINT_SQB_ALLOC_FAIL", sq); - nix_lf_sq_debug_reg(nix, NIX_LF_SEND_ERR_DBG); - } } /* Clear interrupt */ -- 2.18.0