From: Tejasree Kondoj <ktejasree@marvell.com>
To: Akhil Goyal <gakhil@marvell.com>
Cc: Anoob Joseph <anoobj@marvell.com>,
Ankur Dwivedi <adwivedi@marvell.com>,
Archana Muniganti <marchana@marvell.com>,
Tejasree Kondoj <ktejasree@marvell.com>, <dev@dpdk.org>
Subject: [PATCH 5/5] crypto/cnxk: fix updation of number of descriptors
Date: Mon, 31 Jan 2022 18:00:29 +0530 [thread overview]
Message-ID: <20220131123029.4024-6-ktejasree@marvell.com> (raw)
In-Reply-To: <20220131123029.4024-1-ktejasree@marvell.com>
From: Anoob Joseph <anoobj@marvell.com>
Pending queue also need to be adjusted while updating the number of
descriptors.
Fixes: a455fd869cd7 ("common/cnxk: align CPT queue depth to power of 2")
Cc: anoobj@marvell.com
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
---
drivers/common/cnxk/roc_cpt.c | 3 ---
drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 8 ++++++--
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c
index 1bc7a29ef9..4e24850366 100644
--- a/drivers/common/cnxk/roc_cpt.c
+++ b/drivers/common/cnxk/roc_cpt.c
@@ -568,9 +568,6 @@ cpt_lf_init(struct roc_cpt_lf *lf)
if (lf->nb_desc == 0 || lf->nb_desc > CPT_LF_MAX_NB_DESC)
lf->nb_desc = CPT_LF_DEFAULT_NB_DESC;
- /* Update nb_desc to next power of 2 to aid in pending queue checks */
- lf->nb_desc = plt_align32pow2(lf->nb_desc);
-
/* Allocate memory for instruction queue for CPT LF. */
iq_mem = plt_zmalloc(cpt_lf_iq_mem_calc(lf->nb_desc), ROC_ALIGN);
if (iq_mem == NULL)
diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
index 67a2d9b08e..a5fb68da02 100644
--- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
+++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c
@@ -361,6 +361,7 @@ cnxk_cpt_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
struct roc_cpt *roc_cpt = &vf->cpt;
struct rte_pci_device *pci_dev;
struct cnxk_cpt_qp *qp;
+ uint32_t nb_desc;
int ret;
if (dev->data->queue_pairs[qp_id] != NULL)
@@ -373,14 +374,17 @@ cnxk_cpt_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
return -EIO;
}
- qp = cnxk_cpt_qp_create(dev, qp_id, conf->nb_descriptors);
+ /* Update nb_desc to next power of 2 to aid in pending queue checks */
+ nb_desc = plt_align32pow2(conf->nb_descriptors);
+
+ qp = cnxk_cpt_qp_create(dev, qp_id, nb_desc);
if (qp == NULL) {
plt_err("Could not create queue pair %d", qp_id);
return -ENOMEM;
}
qp->lf.lf_id = qp_id;
- qp->lf.nb_desc = conf->nb_descriptors;
+ qp->lf.nb_desc = nb_desc;
ret = roc_cpt_lf_init(roc_cpt, &qp->lf);
if (ret < 0) {
--
2.27.0
next prev parent reply other threads:[~2022-01-31 11:39 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-31 12:30 [PATCH 0/5] Adding new features and improvements in cnxk crypto PMD Tejasree Kondoj
2022-01-31 12:30 ` [PATCH 1/5] common/cnxk: add err ctl Tejasree Kondoj
2022-01-31 12:30 ` [PATCH 2/5] crypto/cnxk: add ESN and antireplay support Tejasree Kondoj
2022-01-31 12:30 ` [PATCH 3/5] common/cnxk: add ROC cache line size constant Tejasree Kondoj
2022-01-31 12:30 ` [PATCH 4/5] crypto/cnxk: use unique cache line per inst Tejasree Kondoj
2022-01-31 12:30 ` Tejasree Kondoj [this message]
2022-02-08 22:26 ` [PATCH 0/5] Adding new features and improvements in cnxk crypto PMD Akhil Goyal
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