From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0ED65A0353; Sat, 5 Feb 2022 01:26:53 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 102CE410DC; Sat, 5 Feb 2022 01:26:50 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id 92694410DC; Sat, 5 Feb 2022 01:26:48 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E1A8E11D4; Fri, 4 Feb 2022 16:26:47 -0800 (PST) Received: from n1sdp-1.usa.Arm.com (n1sdp-1.usa.arm.com [10.118.91.53]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DAAD33F73B; Fri, 4 Feb 2022 16:26:47 -0800 (PST) From: Kathleen Capella To: Jingjing Wu , Beilei Xing , Wenzhuo Lu Cc: dev@dpdk.org, nd@arm.com, dharmik.thakkar@arm.com, honnappa.nagarahalli@arm.com, Kathleen Capella , stable@dpdk.org Subject: [PATCH 1/2] net/iavf: count continuous DD bits for Arm Date: Sat, 5 Feb 2022 00:26:29 +0000 Message-Id: <20220205002630.31841-2-kathleen.capella@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220205002630.31841-1-kathleen.capella@arm.com> References: <20220205002630.31841-1-kathleen.capella@arm.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org On Arm platforms, reading of descriptors may be re-ordered causing the status of DD bits to be discontinuous. Add logic to only process continuous descriptors by checking DD bits. Fixes: 1060591eada5 ("net/avf: enable bulk allocate Rx") Cc: stable@dpdk.org Signed-off-by: Kathleen Capella Reviewed-by: Honnappa Nagarahalli --- drivers/net/iavf/iavf_rxtx.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/net/iavf/iavf_rxtx.c b/drivers/net/iavf/iavf_rxtx.c index 59623ac820..4fc1bf5e78 100644 --- a/drivers/net/iavf/iavf_rxtx.c +++ b/drivers/net/iavf/iavf_rxtx.c @@ -1898,7 +1898,7 @@ iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq) uint16_t pkt_len; uint64_t qword1; uint32_t rx_status; - int32_t s[IAVF_LOOK_AHEAD], nb_dd; + int32_t s[IAVF_LOOK_AHEAD], var, nb_dd; int32_t i, j, nb_rx = 0; uint64_t pkt_flags; const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl; @@ -1929,9 +1929,27 @@ iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq) rte_smp_rmb(); - /* Compute how many status bits were set */ - for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++) - nb_dd += s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT); + /* Compute how many contiguous DD bits were set */ + for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++) { + var = s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT); +#ifdef RTE_ARCH_ARM + /* For Arm platforms, count only contiguous descriptors + * whose DD bit is set to 1. On Arm platforms, reads of + * descriptors can be reordered. Since the CPU may + * be reading the descriptors as the NIC updates them + * in memory, it is possbile that the DD bit for a + * descriptor earlier in the queue is read as not set + * while the DD bit for a descriptor later in the queue + * is read as set. + */ + if (var) + nb_dd += 1; + else + break; +#else + nb_dd += var; +#endif + } nb_rx += nb_dd; -- 2.17.1