[PATCH 01/20] common/cnxk: increase resource count for bitmap alloc

[PATCH 01/20] common/cnxk: increase resource count for bitmap alloc

[Nithin Dabilpuram]

From: Satha Rao <skoteshwar@marvell.com>

CN10K supports up to 832 resources at SMQ level, so increase
bitmap count to 1024.

Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---

Depends-on: Series-20935 ("common/cnxk: use XAQ create API for inline device")
Depends-on: Series-20934 ("common/cnxk: add workaround for vWQE flush")
 drivers/common/cnxk/roc_nix_priv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h
index deb2a6b..4d2a7d8 100644
--- a/drivers/common/cnxk/roc_nix_priv.h
+++ b/drivers/common/cnxk/roc_nix_priv.h
@@ -31,7 +31,7 @@ struct nix_qint {
 };
 
 /* Traffic Manager */
-#define NIX_TM_MAX_HW_TXSCHQ 512
+#define NIX_TM_MAX_HW_TXSCHQ 1024
 #define NIX_TM_HW_ID_INVALID UINT32_MAX
 
 /* TM flags */
-- 
2.8.4

[PATCH 02/20] common/cnxk: realloc inline device XAQ AURA

[Nithin Dabilpuram]

Add support to realloc inline device XAQ AURA with more
buffers of new packet pool AURA.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/common/cnxk/roc_nix_inl.h         |   1 +
 drivers/common/cnxk/roc_nix_inl_dev.c     | 110 +++++++++++++++++++++++++++++-
 drivers/common/cnxk/roc_nix_inl_dev_irq.c |   2 +-
 drivers/common/cnxk/roc_nix_inl_priv.h    |   3 +
 drivers/common/cnxk/roc_platform.h        |   1 +
 drivers/common/cnxk/version.map           |   3 +-
 6 files changed, 115 insertions(+), 5 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h
index abbeac6..bbdcbc8 100644
--- a/drivers/common/cnxk/roc_nix_inl.h
+++ b/drivers/common/cnxk/roc_nix_inl.h
@@ -124,6 +124,7 @@ void __roc_api roc_nix_inl_dev_dump(struct roc_nix_inl_dev *roc_inl_dev);
 bool __roc_api roc_nix_inl_dev_is_probed(void);
 void __roc_api roc_nix_inl_dev_lock(void);
 void __roc_api roc_nix_inl_dev_unlock(void);
+int __roc_api roc_nix_inl_dev_xaq_realloc(uint64_t aura_handle);
 
 /* NIX Inline Inbound API */
 int __roc_api roc_nix_inl_inb_init(struct roc_nix *roc_nix);
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c
index dd93765..1d14f04 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -219,7 +219,6 @@ nix_inl_sso_setup(struct nix_inl_dev *inl_dev)
 	struct sso_lf_alloc_rsp *sso_rsp;
 	struct dev *dev = &inl_dev->dev;
 	uint16_t hwgrp[1] = {0};
-	uint32_t xae_cnt;
 	int rc;
 
 	/* Alloc SSOW LF */
@@ -240,8 +239,8 @@ nix_inl_sso_setup(struct nix_inl_dev *inl_dev)
 	inl_dev->xae_waes = sso_rsp->xaq_wq_entries;
 	inl_dev->iue = sso_rsp->in_unit_entries;
 
-	xae_cnt = inl_dev->iue;
-	rc = sso_hwgrp_init_xaq_aura(dev, &inl_dev->xaq, xae_cnt,
+	inl_dev->nb_xae = inl_dev->iue;
+	rc = sso_hwgrp_init_xaq_aura(dev, &inl_dev->xaq, inl_dev->nb_xae,
 				     inl_dev->xae_waes, inl_dev->xaq_buf_size,
 				     1);
 	if (rc) {
@@ -518,6 +517,111 @@ nix_inl_lf_detach(struct nix_inl_dev *inl_dev)
 	return mbox_process(dev->mbox);
 }
 
+static int
+nix_inl_dev_wait_for_sso_empty(struct nix_inl_dev *inl_dev)
+{
+	uintptr_t sso_base = inl_dev->sso_base;
+	int wait_ms = 3000;
+
+	while (wait_ms > 0) {
+		/* Break when empty */
+		if (!plt_read64(sso_base + SSO_LF_GGRP_XAQ_CNT) &&
+		    !plt_read64(sso_base + SSO_LF_GGRP_AQ_CNT))
+			return 0;
+
+		plt_delay_us(1000);
+		wait_ms -= 1;
+	}
+
+	return -ETIMEDOUT;
+}
+
+int
+roc_nix_inl_dev_xaq_realloc(uint64_t aura_handle)
+{
+	struct idev_cfg *idev = idev_get_cfg();
+	struct nix_inl_dev *inl_dev;
+	int rc, i;
+
+	if (idev == NULL)
+		return 0;
+
+	inl_dev = idev->nix_inl_dev;
+	/* Nothing to do if no inline device */
+	if (!inl_dev)
+		return 0;
+
+	if (!aura_handle) {
+		inl_dev->nb_xae = inl_dev->iue;
+		goto no_pool;
+	}
+
+	/* Check if aura is already considered */
+	for (i = 0; i < inl_dev->pkt_pools_cnt; i++) {
+		if (inl_dev->pkt_pools[i] == aura_handle)
+			return 0;
+	}
+
+no_pool:
+	/* Disable RQ if enabled */
+	if (inl_dev->rq_refs) {
+		rc = nix_rq_ena_dis(&inl_dev->dev, &inl_dev->rq, false);
+		if (rc) {
+			plt_err("Failed to disable inline dev RQ, rc=%d", rc);
+			return rc;
+		}
+	}
+
+	/* Wait for events to be removed */
+	rc = nix_inl_dev_wait_for_sso_empty(inl_dev);
+	if (rc) {
+		plt_err("Timeout waiting for inline device event cleanup");
+		goto exit;
+	}
+
+	/* Disable HWGRP */
+	plt_write64(0, inl_dev->sso_base + SSO_LF_GGRP_QCTL);
+
+	inl_dev->pkt_pools_cnt++;
+	inl_dev->pkt_pools =
+		plt_realloc(inl_dev->pkt_pools,
+			    sizeof(uint64_t *) * inl_dev->pkt_pools_cnt, 0);
+	if (!inl_dev->pkt_pools)
+		inl_dev->pkt_pools_cnt = 0;
+	else
+		inl_dev->pkt_pools[inl_dev->pkt_pools_cnt - 1] = aura_handle;
+	inl_dev->nb_xae += roc_npa_aura_op_limit_get(aura_handle);
+
+	/* Realloc XAQ aura */
+	rc = sso_hwgrp_init_xaq_aura(&inl_dev->dev, &inl_dev->xaq,
+				     inl_dev->nb_xae, inl_dev->xae_waes,
+				     inl_dev->xaq_buf_size, 1);
+	if (rc) {
+		plt_err("Failed to reinitialize xaq aura, rc=%d", rc);
+		return rc;
+	}
+
+	/* Setup xaq for hwgrps */
+	rc = sso_hwgrp_alloc_xaq(&inl_dev->dev, inl_dev->xaq.aura_handle, 1);
+	if (rc) {
+		plt_err("Failed to setup hwgrp xaq aura, rc=%d", rc);
+		return rc;
+	}
+
+	/* Enable HWGRP */
+	plt_write64(0x1, inl_dev->sso_base + SSO_LF_GGRP_QCTL);
+
+exit:
+	/* Renable RQ */
+	if (inl_dev->rq_refs) {
+		rc = nix_rq_ena_dis(&inl_dev->dev, &inl_dev->rq, true);
+		if (rc)
+			plt_err("Failed to enable inline dev RQ, rc=%d", rc);
+	}
+
+	return rc;
+}
+
 int
 roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)
 {
diff --git a/drivers/common/cnxk/roc_nix_inl_dev_irq.c b/drivers/common/cnxk/roc_nix_inl_dev_irq.c
index 848523b..d758e0c 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev_irq.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev_irq.c
@@ -72,7 +72,7 @@ nix_inl_sso_hwgrp_irq(void *param)
 	if (intr & BIT(1))
 		nix_inl_sso_work_cb(inl_dev);
 
-	if (!(intr & BIT(1)))
+	if (intr & ~BIT(1))
 		plt_err("GGRP 0 GGRP_INT=0x%" PRIx64 "", intr);
 
 	/* Clear interrupt */
diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h
index 2cdab6dc..17df23f 100644
--- a/drivers/common/cnxk/roc_nix_inl_priv.h
+++ b/drivers/common/cnxk/roc_nix_inl_priv.h
@@ -27,9 +27,12 @@ struct nix_inl_dev {
 	uint32_t xaq_buf_size;
 	uint32_t xae_waes;
 	uint32_t iue;
+	uint32_t nb_xae;
 	struct roc_sso_xaq_data xaq;
 	roc_nix_inl_sso_work_cb_t work_cb;
 	void *cb_args;
+	uint64_t *pkt_pools;
+	uint16_t pkt_pools_cnt;
 
 	/* NIX data */
 	uint8_t lf_tx_stats;
diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h
index c35a2b1..8eac24f 100644
--- a/drivers/common/cnxk/roc_platform.h
+++ b/drivers/common/cnxk/roc_platform.h
@@ -147,6 +147,7 @@
 #define plt_intr_handle rte_intr_handle
 
 #define plt_zmalloc(sz, align) rte_zmalloc("cnxk", sz, align)
+#define plt_realloc	       rte_realloc
 #define plt_free	       rte_free
 
 #define plt_read64(addr) rte_read64_relaxed((volatile void *)(addr))
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 82b9fc1..617364f 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -132,11 +132,12 @@ INTERNAL {
 	roc_nix_inl_dev_init;
 	roc_nix_inl_dev_is_probed;
 	roc_nix_inl_dev_lock;
-	roc_nix_inl_dev_unlock;
 	roc_nix_inl_dev_rq;
 	roc_nix_inl_dev_rq_get;
 	roc_nix_inl_dev_rq_put;
 	roc_nix_inl_dev_rq_limit_get;
+	roc_nix_inl_dev_unlock;
+	roc_nix_inl_dev_xaq_realloc;
 	roc_nix_inl_inb_is_enabled;
 	roc_nix_inl_inb_init;
 	roc_nix_inl_inb_sa_base_get;
-- 
2.8.4

[PATCH 03/20] common/cnxk: adjust shaper rates to lower boundaries

[Nithin Dabilpuram]

From: Satha Rao <skoteshwar@marvell.com>

New api to get floor values for a requested shaper rate, which can assure
packets should never be transmitted at a rate higher than configured.

Keep the old api to get HW suggested values.
And introduce new parameter to select appropriate api.

Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---
 drivers/common/cnxk/roc_nix.h          |  1 +
 drivers/common/cnxk/roc_nix_priv.h     |  4 +-
 drivers/common/cnxk/roc_nix_tm_ops.c   | 10 ++--
 drivers/common/cnxk/roc_nix_tm_utils.c | 90 ++++++++++++++++++++++++++++++++--
 4 files changed, 96 insertions(+), 9 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 755212c..250e1c0 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -531,6 +531,7 @@ struct roc_nix_tm_shaper_profile {
 	uint64_t peak_sz;
 	int32_t pkt_len_adj;
 	bool pkt_mode;
+	int8_t accuracy;
 	/* Function to free this memory */
 	void (*free_fn)(void *profile);
 };
diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h
index 4d2a7d8..ec6f106 100644
--- a/drivers/common/cnxk/roc_nix_priv.h
+++ b/drivers/common/cnxk/roc_nix_priv.h
@@ -95,6 +95,7 @@ struct nix_tm_shaper_profile {
 	int32_t pkt_mode_adj;
 	bool pkt_mode;
 	uint32_t id;
+	int8_t accuracy;
 	void (*free_fn)(void *profile);
 
 	uint32_t ref_cnt;
@@ -399,7 +400,8 @@ uint32_t nix_tm_check_rr(struct nix *nix, uint32_t parent_id,
 			 uint32_t *max_prio);
 uint64_t nix_tm_shaper_profile_rate_min(struct nix *nix);
 uint64_t nix_tm_shaper_rate_conv(uint64_t value, uint64_t *exponent_p,
-				 uint64_t *mantissa_p, uint64_t *div_exp_p);
+				 uint64_t *mantissa_p, uint64_t *div_exp_p,
+				 int8_t accuracy);
 uint64_t nix_tm_shaper_burst_conv(uint64_t value, uint64_t *exponent_p,
 				  uint64_t *mantissa_p);
 bool nix_tm_child_res_valid(struct nix_tm_node_list *list,
diff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c
index 3d81247..a1f5f0e 100644
--- a/drivers/common/cnxk/roc_nix_tm_ops.c
+++ b/drivers/common/cnxk/roc_nix_tm_ops.c
@@ -173,8 +173,8 @@ nix_tm_shaper_profile_add(struct roc_nix *roc_nix,
 	if (commit_rate || commit_sz) {
 		if (commit_sz < min_burst || commit_sz > max_burst)
 			return NIX_ERR_TM_INVALID_COMMIT_SZ;
-		else if (!nix_tm_shaper_rate_conv(commit_rate, NULL, NULL,
-						  NULL))
+		else if (!nix_tm_shaper_rate_conv(commit_rate, NULL, NULL, NULL,
+						  profile->accuracy))
 			return NIX_ERR_TM_INVALID_COMMIT_RATE;
 	}
 
@@ -182,7 +182,8 @@ nix_tm_shaper_profile_add(struct roc_nix *roc_nix,
 	if (peak_sz || peak_rate) {
 		if (peak_sz < min_burst || peak_sz > max_burst)
 			return NIX_ERR_TM_INVALID_PEAK_SZ;
-		else if (!nix_tm_shaper_rate_conv(peak_rate, NULL, NULL, NULL))
+		else if (!nix_tm_shaper_rate_conv(peak_rate, NULL, NULL, NULL,
+						  profile->accuracy))
 			return NIX_ERR_TM_INVALID_PEAK_RATE;
 	}
 
@@ -230,6 +231,7 @@ roc_nix_tm_shaper_profile_add(struct roc_nix *roc_nix,
 	profile->pkt_len_adj = roc_profile->pkt_len_adj;
 	profile->pkt_mode = roc_profile->pkt_mode;
 	profile->free_fn = roc_profile->free_fn;
+	profile->accuracy = roc_profile->accuracy;
 
 	return nix_tm_shaper_profile_add(roc_nix, profile, 0);
 }
@@ -246,6 +248,8 @@ roc_nix_tm_shaper_profile_update(struct roc_nix *roc_nix,
 	profile->peak.rate = roc_profile->peak_rate;
 	profile->commit.size = roc_profile->commit_sz;
 	profile->peak.size = roc_profile->peak_sz;
+	profile->pkt_len_adj = roc_profile->pkt_len_adj;
+	profile->accuracy = roc_profile->accuracy;
 
 	return nix_tm_shaper_profile_add(roc_nix, profile, 1);
 }
diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c
index 9e80c2a..4ba0752 100644
--- a/drivers/common/cnxk/roc_nix_tm_utils.c
+++ b/drivers/common/cnxk/roc_nix_tm_utils.c
@@ -125,9 +125,72 @@ nix_tm_node_search(struct nix *nix, uint32_t node_id, enum roc_nix_tm_tree tree)
 	return NULL;
 }
 
-uint64_t
-nix_tm_shaper_rate_conv(uint64_t value, uint64_t *exponent_p,
-			uint64_t *mantissa_p, uint64_t *div_exp_p)
+static uint64_t
+nix_tm_shaper_rate_conv_floor(uint64_t value, uint64_t *exponent_p,
+			      uint64_t *mantissa_p, uint64_t *div_exp_p)
+{
+	uint64_t div_exp, exponent, mantissa;
+
+	/* Boundary checks */
+	if (value < NIX_TM_MIN_SHAPER_RATE || value > NIX_TM_MAX_SHAPER_RATE)
+		return 0;
+
+	if (value <= NIX_TM_SHAPER_RATE(0, 0, 0)) {
+		/* Calculate rate div_exp and mantissa using
+		 * the following formula:
+		 *
+		 * value = (2E6 * (256 + mantissa)
+		 *              / ((1 << div_exp) * 256))
+		 */
+		div_exp = 0;
+		exponent = 0;
+		mantissa = NIX_TM_MAX_RATE_MANTISSA;
+
+		while (value <= (NIX_TM_SHAPER_RATE_CONST / (1 << div_exp)))
+			div_exp += 1;
+
+		while (value <= ((NIX_TM_SHAPER_RATE_CONST * (256 + mantissa)) /
+				 ((1 << div_exp) * 256)))
+			mantissa -= 1;
+	} else {
+		/* Calculate rate exponent and mantissa using
+		 * the following formula:
+		 *
+		 * value = (2E6 * ((256 + mantissa) << exponent)) / 256
+		 *
+		 */
+		div_exp = 0;
+		exponent = NIX_TM_MAX_RATE_EXPONENT;
+		mantissa = NIX_TM_MAX_RATE_MANTISSA;
+
+		while (value <= (NIX_TM_SHAPER_RATE_CONST * (1 << exponent)))
+			exponent -= 1;
+
+		while (value <= ((NIX_TM_SHAPER_RATE_CONST *
+				  ((256 + mantissa) << exponent)) /
+				 256))
+			mantissa -= 1;
+	}
+
+	if (div_exp > NIX_TM_MAX_RATE_DIV_EXP ||
+	    exponent > NIX_TM_MAX_RATE_EXPONENT ||
+	    mantissa > NIX_TM_MAX_RATE_MANTISSA)
+		return 0;
+
+	if (div_exp_p)
+		*div_exp_p = div_exp;
+	if (exponent_p)
+		*exponent_p = exponent;
+	if (mantissa_p)
+		*mantissa_p = mantissa;
+
+	/* Calculate real rate value */
+	return NIX_TM_SHAPER_RATE(exponent, mantissa, div_exp);
+}
+
+static uint64_t
+nix_tm_shaper_rate_conv_exact(uint64_t value, uint64_t *exponent_p,
+			      uint64_t *mantissa_p, uint64_t *div_exp_p)
 {
 	uint64_t div_exp, exponent, mantissa;
 
@@ -188,6 +251,23 @@ nix_tm_shaper_rate_conv(uint64_t value, uint64_t *exponent_p,
 	return NIX_TM_SHAPER_RATE(exponent, mantissa, div_exp);
 }
 
+/* With zero accuracy we will tune parameters as defined by HW,
+ * non zero accuracy will keep the parameters close to lower values
+ * and make sure long term shaper rate will not exceed requested rate.
+ */
+uint64_t
+nix_tm_shaper_rate_conv(uint64_t value, uint64_t *exponent_p,
+			uint64_t *mantissa_p, uint64_t *div_exp_p,
+			int8_t accuracy)
+{
+	if (!accuracy)
+		return nix_tm_shaper_rate_conv_exact(value, exponent_p,
+						     mantissa_p, div_exp_p);
+
+	return nix_tm_shaper_rate_conv_floor(value, exponent_p, mantissa_p,
+					     div_exp_p);
+}
+
 uint64_t
 nix_tm_shaper_burst_conv(uint64_t value, uint64_t *exponent_p,
 			 uint64_t *mantissa_p)
@@ -245,13 +325,13 @@ nix_tm_shaper_conf_get(struct nix_tm_shaper_profile *profile,
 	if (profile->commit.rate)
 		cir->rate = nix_tm_shaper_rate_conv(
 			profile->commit.rate, &cir->exponent, &cir->mantissa,
-			&cir->div_exp);
+			&cir->div_exp, profile->accuracy);
 
 	/* Calculate PIR exponent and mantissa */
 	if (profile->peak.rate)
 		pir->rate = nix_tm_shaper_rate_conv(
 			profile->peak.rate, &pir->exponent, &pir->mantissa,
-			&pir->div_exp);
+			&pir->div_exp, profile->accuracy);
 
 	/* Calculate CIR burst exponent and mantissa */
 	if (profile->commit.size)
-- 
2.8.4

Re: [PATCH 03/20] common/cnxk: adjust shaper rates to lower boundaries

[Jerin Jacob]

On Mon, Feb 7, 2022 at 1:00 PM Nithin Dabilpuram
<ndabilpuram@marvell.com> wrote:
>
> From: Satha Rao <skoteshwar@marvell.com>
>
> New api to get floor values for a requested shaper rate, which can assure

Since it is internal API, no need to mention in the comment log

> packets should never be transmitted at a rate higher than configured.
>
> Keep the old api to get HW suggested values.
> And introduce new parameter to select appropriate api.

api -> API

>
> Signed-off-by: Satha Rao <skoteshwar@marvell.com>
> ---
> +static uint64_t
> +nix_tm_shaper_rate_conv_floor(uint64_t value, uint64_t *exponent_p,
> +                             uint64_t *mantissa_p, uint64_t *div_exp_p)
> +{
> +       uint64_t div_exp, exponent, mantissa;
> +
> +       /* Boundary checks */
> +       if (value < NIX_TM_MIN_SHAPER_RATE || value > NIX_TM_MAX_SHAPER_RATE)
> +               return 0;
> +
> +       if (value <= NIX_TM_SHAPER_RATE(0, 0, 0)) {
> +               /* Calculate rate div_exp and mantissa using
> +                * the following formula:
> +                *
> +                * value = (2E6 * (256 + mantissa)
> +                *              / ((1 << div_exp) * 256))
> +                */
> +               div_exp = 0;
> +               exponent = 0;
> +               mantissa = NIX_TM_MAX_RATE_MANTISSA;
> +
> +               while (value <= (NIX_TM_SHAPER_RATE_CONST / (1 << div_exp)))
> +                       div_exp += 1;
> +
> +               while (value <= ((NIX_TM_SHAPER_RATE_CONST * (256 + mantissa)) /
> +                                ((1 << div_exp) * 256)))
> +                       mantissa -= 1;

Please move this as another static function.


> +       } else {
> +               /* Calculate rate exponent and mantissa using
> +                * the following formula:
> +                *
> +                * value = (2E6 * ((256 + mantissa) << exponent)) / 256
> +                *
> +                */
> +               div_exp = 0;
> +               exponent = NIX_TM_MAX_RATE_EXPONENT;
> +               mantissa = NIX_TM_MAX_RATE_MANTISSA;
> +
> +               while (value <= (NIX_TM_SHAPER_RATE_CONST * (1 << exponent)))
> +                       exponent -= 1;
> +
> +               while (value <= ((NIX_TM_SHAPER_RATE_CONST *
> +                                 ((256 + mantissa) << exponent)) /
> +                                256))
> +                       mantissa -= 1;

Please move this as another static function.

> +       }
> +
> +       if (div_exp > NIX_TM_MAX_RATE_DIV_EXP ||
> +           exponent > NIX_TM_MAX_RATE_EXPONENT ||
> +           mantissa > NIX_TM_MAX_RATE_MANTISSA)
> +               return 0;
> +
> +       if (div_exp_p)
> +               *div_exp_p = div_exp;
> +       if (exponent_p)
> +               *exponent_p = exponent;
> +       if (mantissa_p)
> +               *mantissa_p = mantissa;
> +
> +       /* Calculate real rate value */
> +       return NIX_TM_SHAPER_RATE(exponent, mantissa, div_exp);
> +}
> +
> +static uint64_t
> +nix_tm_shaper_rate_conv_exact(uint64_t value, uint64_t *exponent_p,
> +                             uint64_t *mantissa_p, uint64_t *div_exp_p)
>  {
>         uint64_t div_exp, exponent, mantissa;
>
> @@ -188,6 +251,23 @@ nix_tm_shaper_rate_conv(uint64_t value, uint64_t *exponent_p,
>         return NIX_TM_SHAPER_RATE(exponent, mantissa, div_exp);
>  }
>
> +/* With zero accuracy we will tune parameters as defined by HW,
> + * non zero accuracy will keep the parameters close to lower values
> + * and make sure long term shaper rate will not exceed requested rate.

long-term
requested -> the requested

Re: [PATCH 03/20] common/cnxk: adjust shaper rates to lower boundaries

[Nithin Kumar Dabilpuram]

Please see inline.

On 2/17/22 6:50 PM, Jerin Jacob wrote:
> On Mon, Feb 7, 2022 at 1:00 PM Nithin Dabilpuram
> <ndabilpuram@marvell.com> wrote:
>>
>> From: Satha Rao <skoteshwar@marvell.com>
>>
>> New api to get floor values for a requested shaper rate, which can assure
> 
> Since it is internal API, no need to mention in the comment log
> 
>> packets should never be transmitted at a rate higher than configured.
>>
>> Keep the old api to get HW suggested values.
>> And introduce new parameter to select appropriate api.
> 
> api -> API
> 
>>
>> Signed-off-by: Satha Rao <skoteshwar@marvell.com>
>> ---
>> +static uint64_t
>> +nix_tm_shaper_rate_conv_floor(uint64_t value, uint64_t *exponent_p,
>> +                             uint64_t *mantissa_p, uint64_t *div_exp_p)
>> +{
>> +       uint64_t div_exp, exponent, mantissa;
>> +
>> +       /* Boundary checks */
>> +       if (value < NIX_TM_MIN_SHAPER_RATE || value > NIX_TM_MAX_SHAPER_RATE)
>> +               return 0;
>> +
>> +       if (value <= NIX_TM_SHAPER_RATE(0, 0, 0)) {
>> +               /* Calculate rate div_exp and mantissa using
>> +                * the following formula:
>> +                *
>> +                * value = (2E6 * (256 + mantissa)
>> +                *              / ((1 << div_exp) * 256))
>> +                */
>> +               div_exp = 0;
>> +               exponent = 0;
>> +               mantissa = NIX_TM_MAX_RATE_MANTISSA;
>> +
>> +               while (value <= (NIX_TM_SHAPER_RATE_CONST / (1 << div_exp)))
>> +                       div_exp += 1;
>> +
>> +               while (value <= ((NIX_TM_SHAPER_RATE_CONST * (256 + mantissa)) /
>> +                                ((1 << div_exp) * 256)))
>> +                       mantissa -= 1;
> 
> Please move this as another static function.
This is not same as the non-floor function though it looks same. The 
while loops terminate in <= in this function. Do you still need sub 
functions for these ?
> 
> 
>> +       } else {
>> +               /* Calculate rate exponent and mantissa using
>> +                * the following formula:
>> +                *
>> +                * value = (2E6 * ((256 + mantissa) << exponent)) / 256
>> +                *
>> +                */
>> +               div_exp = 0;
>> +               exponent = NIX_TM_MAX_RATE_EXPONENT;
>> +               mantissa = NIX_TM_MAX_RATE_MANTISSA;
>> +
>> +               while (value <= (NIX_TM_SHAPER_RATE_CONST * (1 << exponent)))
>> +                       exponent -= 1;
>> +
>> +               while (value <= ((NIX_TM_SHAPER_RATE_CONST *
>> +                                 ((256 + mantissa) << exponent)) /
>> +                                256))
>> +                       mantissa -= 1;
> 
> Please move this as another static function.
Same comment as above.
> 
>> +       }
>> +
>> +       if (div_exp > NIX_TM_MAX_RATE_DIV_EXP ||
>> +           exponent > NIX_TM_MAX_RATE_EXPONENT ||
>> +           mantissa > NIX_TM_MAX_RATE_MANTISSA)
>> +               return 0;
>> +
>> +       if (div_exp_p)
>> +               *div_exp_p = div_exp;
>> +       if (exponent_p)
>> +               *exponent_p = exponent;
>> +       if (mantissa_p)
>> +               *mantissa_p = mantissa;
>> +
>> +       /* Calculate real rate value */
>> +       return NIX_TM_SHAPER_RATE(exponent, mantissa, div_exp);
>> +}
>> +
>> +static uint64_t
>> +nix_tm_shaper_rate_conv_exact(uint64_t value, uint64_t *exponent_p,
>> +                             uint64_t *mantissa_p, uint64_t *div_exp_p)
>>   {
>>          uint64_t div_exp, exponent, mantissa;
>>
>> @@ -188,6 +251,23 @@ nix_tm_shaper_rate_conv(uint64_t value, uint64_t *exponent_p,
>>          return NIX_TM_SHAPER_RATE(exponent, mantissa, div_exp);
>>   }
>>
>> +/* With zero accuracy we will tune parameters as defined by HW,
>> + * non zero accuracy will keep the parameters close to lower values
>> + * and make sure long term shaper rate will not exceed requested rate.
> 
> long-term
> requested -> the requested

Re: [PATCH 03/20] common/cnxk: adjust shaper rates to lower boundaries

[Jerin Jacob]

On Tue, Feb 22, 2022 at 11:49 PM Nithin Kumar Dabilpuram
<ndabilpuram@marvell.com> wrote:
>
> Please see inline.
>
> On 2/17/22 6:50 PM, Jerin Jacob wrote:
> > On Mon, Feb 7, 2022 at 1:00 PM Nithin Dabilpuram
> > <ndabilpuram@marvell.com> wrote:
> >>
> >> From: Satha Rao <skoteshwar@marvell.com>
> >>
> >> New api to get floor values for a requested shaper rate, which can assure
> >
> > Since it is internal API, no need to mention in the comment log
> >
> >> packets should never be transmitted at a rate higher than configured.
> >>
> >> Keep the old api to get HW suggested values.
> >> And introduce new parameter to select appropriate api.
> >
> > api -> API
> >
> >>
> >> Signed-off-by: Satha Rao <skoteshwar@marvell.com>
> >> ---
> >> +static uint64_t
> >> +nix_tm_shaper_rate_conv_floor(uint64_t value, uint64_t *exponent_p,
> >> +                             uint64_t *mantissa_p, uint64_t *div_exp_p)
> >> +{
> >> +       uint64_t div_exp, exponent, mantissa;
> >> +
> >> +       /* Boundary checks */
> >> +       if (value < NIX_TM_MIN_SHAPER_RATE || value > NIX_TM_MAX_SHAPER_RATE)
> >> +               return 0;
> >> +
> >> +       if (value <= NIX_TM_SHAPER_RATE(0, 0, 0)) {
> >> +               /* Calculate rate div_exp and mantissa using
> >> +                * the following formula:
> >> +                *
> >> +                * value = (2E6 * (256 + mantissa)
> >> +                *              / ((1 << div_exp) * 256))
> >> +                */
> >> +               div_exp = 0;
> >> +               exponent = 0;
> >> +               mantissa = NIX_TM_MAX_RATE_MANTISSA;
> >> +
> >> +               while (value <= (NIX_TM_SHAPER_RATE_CONST / (1 << div_exp)))
> >> +                       div_exp += 1;
> >> +
> >> +               while (value <= ((NIX_TM_SHAPER_RATE_CONST * (256 + mantissa)) /
> >> +                                ((1 << div_exp) * 256)))
> >> +                       mantissa -= 1;
> >
> > Please move this as another static function.
> This is not same as the non-floor function though it looks same. The
> while loops terminate in <= in this function. Do you still need sub
> functions for these ?

No. It is fine.

> >
> >
> >> +       } else {
> >> +               /* Calculate rate exponent and mantissa using
> >> +                * the following formula:
> >> +                *
> >> +                * value = (2E6 * ((256 + mantissa) << exponent)) / 256
> >> +                *
> >> +                */
> >> +               div_exp = 0;
> >> +               exponent = NIX_TM_MAX_RATE_EXPONENT;
> >> +               mantissa = NIX_TM_MAX_RATE_MANTISSA;
> >> +
> >> +               while (value <= (NIX_TM_SHAPER_RATE_CONST * (1 << exponent)))
> >> +                       exponent -= 1;
> >> +
> >> +               while (value <= ((NIX_TM_SHAPER_RATE_CONST *
> >> +                                 ((256 + mantissa) << exponent)) /
> >> +                                256))
> >> +                       mantissa -= 1;
> >
> > Please move this as another static function.
> Same comment as above.
> >
> >> +       }
> >> +
> >> +       if (div_exp > NIX_TM_MAX_RATE_DIV_EXP ||
> >> +           exponent > NIX_TM_MAX_RATE_EXPONENT ||
> >> +           mantissa > NIX_TM_MAX_RATE_MANTISSA)
> >> +               return 0;
> >> +
> >> +       if (div_exp_p)
> >> +               *div_exp_p = div_exp;
> >> +       if (exponent_p)
> >> +               *exponent_p = exponent;
> >> +       if (mantissa_p)
> >> +               *mantissa_p = mantissa;
> >> +
> >> +       /* Calculate real rate value */
> >> +       return NIX_TM_SHAPER_RATE(exponent, mantissa, div_exp);
> >> +}
> >> +
> >> +static uint64_t
> >> +nix_tm_shaper_rate_conv_exact(uint64_t value, uint64_t *exponent_p,
> >> +                             uint64_t *mantissa_p, uint64_t *div_exp_p)
> >>   {
> >>          uint64_t div_exp, exponent, mantissa;
> >>
> >> @@ -188,6 +251,23 @@ nix_tm_shaper_rate_conv(uint64_t value, uint64_t *exponent_p,
> >>          return NIX_TM_SHAPER_RATE(exponent, mantissa, div_exp);
> >>   }
> >>
> >> +/* With zero accuracy we will tune parameters as defined by HW,
> >> + * non zero accuracy will keep the parameters close to lower values
> >> + * and make sure long term shaper rate will not exceed requested rate.
> >
> > long-term
> > requested -> the requested

[PATCH 04/20] common/cnxk: support inline device API without ROC NIX

[Nithin Dabilpuram]

From: Vidya Sagar Velumuri <vvelumuri@marvell.com>

Update the inline device functions to work when roc_nix is NULL.
This is required, as IPsec driver have to use these APIs to work
with inline IPsec device, but the IPsec driver might not have roc_nix
information.

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
---
 drivers/common/cnxk/roc_nix_inl.c      | 98 ++++++++++++++++++++++++----------
 drivers/common/cnxk/roc_nix_inl.h      |  2 +
 drivers/common/cnxk/roc_nix_inl_dev.c  |  7 +++
 drivers/common/cnxk/roc_nix_inl_priv.h |  1 +
 drivers/common/cnxk/version.map        |  1 +
 drivers/net/cnxk/cnxk_ethdev_sec.c     |  2 +
 6 files changed, 84 insertions(+), 27 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index e8981c4..356d11d 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -107,18 +107,24 @@ roc_nix_inl_outb_sa_base_get(struct roc_nix *roc_nix)
 uintptr_t
 roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix, bool inb_inl_dev)
 {
-	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
 	struct idev_cfg *idev = idev_get_cfg();
 	struct nix_inl_dev *inl_dev;
+	struct nix *nix = NULL;
 
 	if (idev == NULL)
 		return 0;
 
-	if (!nix->inl_inb_ena)
-		return 0;
+	if (!inb_inl_dev && roc_nix == NULL)
+		return -EINVAL;
+
+	if (roc_nix) {
+		nix = roc_nix_to_nix_priv(roc_nix);
+		if (!nix->inl_inb_ena)
+			return 0;
+	}
 
-	inl_dev = idev->nix_inl_dev;
 	if (inb_inl_dev) {
+		inl_dev = idev->nix_inl_dev;
 		/* Return inline dev sa base */
 		if (inl_dev)
 			return (uintptr_t)inl_dev->inb_sa_base;
@@ -131,18 +137,24 @@ roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix, bool inb_inl_dev)
 uint32_t
 roc_nix_inl_inb_sa_max_spi(struct roc_nix *roc_nix, bool inb_inl_dev)
 {
-	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
 	struct idev_cfg *idev = idev_get_cfg();
 	struct nix_inl_dev *inl_dev;
+	struct nix *nix;
 
 	if (idev == NULL)
 		return 0;
 
-	if (!nix->inl_inb_ena)
-		return 0;
+	if (!inb_inl_dev && roc_nix == NULL)
+		return -EINVAL;
+
+	if (roc_nix) {
+		nix = roc_nix_to_nix_priv(roc_nix);
+		if (!nix->inl_inb_ena)
+			return 0;
+	}
 
-	inl_dev = idev->nix_inl_dev;
 	if (inb_inl_dev) {
+		inl_dev = idev->nix_inl_dev;
 		if (inl_dev)
 			return inl_dev->ipsec_in_max_spi;
 		return 0;
@@ -154,21 +166,28 @@ roc_nix_inl_inb_sa_max_spi(struct roc_nix *roc_nix, bool inb_inl_dev)
 uint32_t
 roc_nix_inl_inb_sa_sz(struct roc_nix *roc_nix, bool inl_dev_sa)
 {
-	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
 	struct idev_cfg *idev = idev_get_cfg();
 	struct nix_inl_dev *inl_dev;
+	struct nix *nix;
 
 	if (idev == NULL)
 		return 0;
 
-	if (!inl_dev_sa)
-		return nix->inb_sa_sz;
+	if (!inl_dev_sa && roc_nix == NULL)
+		return -EINVAL;
 
-	inl_dev = idev->nix_inl_dev;
-	if (inl_dev_sa && inl_dev)
-		return inl_dev->inb_sa_sz;
+	if (roc_nix) {
+		nix = roc_nix_to_nix_priv(roc_nix);
+		if (!inl_dev_sa)
+			return nix->inb_sa_sz;
+	}
+
+	if (inl_dev_sa) {
+		inl_dev = idev->nix_inl_dev;
+		if (inl_dev)
+			return inl_dev->inb_sa_sz;
+	}
 
-	/* On error */
 	return 0;
 }
 
@@ -536,7 +555,7 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq)
 	inl_rq->tag_mask = 0xFFF00000;
 	inl_rq->tt = SSO_TT_ORDERED;
 	inl_rq->hwgrp = 0;
-	inl_rq->wqe_skip = 1;
+	inl_rq->wqe_skip = inl_dev->wqe_skip;
 	inl_rq->sso_ena = true;
 
 	/* Prepare and send RQ init mbox */
@@ -731,13 +750,14 @@ int
 roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa, bool inb,
 		    enum roc_nix_inl_sa_sync_op op)
 {
-	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
-	struct roc_cpt_lf *outb_lf = nix->cpt_lf_base;
 	struct idev_cfg *idev = idev_get_cfg();
 	struct nix_inl_dev *inl_dev = NULL;
+	struct roc_cpt_lf *outb_lf = NULL;
 	union cpt_lf_ctx_reload reload;
 	union cpt_lf_ctx_flush flush;
+	bool get_inl_lf = true;
 	uintptr_t rbase;
+	struct nix *nix;
 
 	/* Nothing much to do on cn9k */
 	if (roc_model_is_cn9k()) {
@@ -745,11 +765,22 @@ roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa, bool inb,
 		return 0;
 	}
 
-	if (inb && nix->inb_inl_dev) {
+	if (idev)
+		inl_dev = idev->nix_inl_dev;
+
+	if (!inl_dev && roc_nix == NULL)
+		return -EINVAL;
+
+	if (roc_nix) {
+		nix = roc_nix_to_nix_priv(roc_nix);
+		outb_lf = nix->cpt_lf_base;
+		if (inb && !nix->inb_inl_dev)
+			get_inl_lf = false;
+	}
+
+	if (inb && get_inl_lf) {
 		outb_lf = NULL;
-		if (idev)
-			inl_dev = idev->nix_inl_dev;
-		if (inl_dev)
+		if (inl_dev && inl_dev->attach_cptlf)
 			outb_lf = &inl_dev->cpt_lf;
 	}
 
@@ -783,12 +814,13 @@ int
 roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, void *sa_cptr,
 		      bool inb, uint16_t sa_len)
 {
-	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
-	struct roc_cpt_lf *outb_lf = nix->cpt_lf_base;
 	struct idev_cfg *idev = idev_get_cfg();
 	struct nix_inl_dev *inl_dev = NULL;
+	struct roc_cpt_lf *outb_lf = NULL;
 	union cpt_lf_ctx_flush flush;
+	bool get_inl_lf = true;
 	uintptr_t rbase;
+	struct nix *nix;
 	int rc;
 
 	/* Nothing much to do on cn9k */
@@ -797,10 +829,22 @@ roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, void *sa_cptr,
 		return 0;
 	}
 
-	if (inb && nix->inb_inl_dev) {
+	if (idev)
+		inl_dev = idev->nix_inl_dev;
+
+	if (!inl_dev && roc_nix == NULL)
+		return -EINVAL;
+
+	if (roc_nix) {
+		nix = roc_nix_to_nix_priv(roc_nix);
+		outb_lf = nix->cpt_lf_base;
+
+		if (inb && !nix->inb_inl_dev)
+			get_inl_lf = false;
+	}
+
+	if (inb && get_inl_lf) {
 		outb_lf = NULL;
-		if (idev)
-			inl_dev = idev->nix_inl_dev;
 		if (inl_dev && inl_dev->attach_cptlf)
 			outb_lf = &inl_dev->cpt_lf;
 	}
diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h
index bbdcbc8..ceeccab 100644
--- a/drivers/common/cnxk/roc_nix_inl.h
+++ b/drivers/common/cnxk/roc_nix_inl.h
@@ -111,6 +111,7 @@ struct roc_nix_inl_dev {
 	uint16_t channel;
 	uint16_t chan_mask;
 	bool attach_cptlf;
+	bool wqe_skip;
 	/* End of input parameters */
 
 #define ROC_NIX_INL_MEM_SZ (1280)
@@ -125,6 +126,7 @@ bool __roc_api roc_nix_inl_dev_is_probed(void);
 void __roc_api roc_nix_inl_dev_lock(void);
 void __roc_api roc_nix_inl_dev_unlock(void);
 int __roc_api roc_nix_inl_dev_xaq_realloc(uint64_t aura_handle);
+uint16_t __roc_api roc_nix_inl_dev_pffunc_get(void);
 
 /* NIX Inline Inbound API */
 int __roc_api roc_nix_inl_inb_init(struct roc_nix *roc_nix);
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c
index 1d14f04..12160e9 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -27,6 +27,12 @@ nix_inl_dev_pffunc_get(void)
 	return 0;
 }
 
+uint16_t
+roc_nix_inl_dev_pffunc_get(void)
+{
+	return nix_inl_dev_pffunc_get();
+}
+
 static void
 nix_inl_selftest_work_cb(uint64_t *gw, void *args)
 {
@@ -655,6 +661,7 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)
 	inl_dev->channel = roc_inl_dev->channel;
 	inl_dev->chan_mask = roc_inl_dev->chan_mask;
 	inl_dev->attach_cptlf = roc_inl_dev->attach_cptlf;
+	inl_dev->wqe_skip = roc_inl_dev->wqe_skip;
 
 	/* Initialize base device */
 	rc = dev_init(&inl_dev->dev, pci_dev);
diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h
index 17df23f..dcf752e 100644
--- a/drivers/common/cnxk/roc_nix_inl_priv.h
+++ b/drivers/common/cnxk/roc_nix_inl_priv.h
@@ -58,6 +58,7 @@ struct nix_inl_dev {
 	bool is_multi_channel;
 	uint16_t ipsec_in_max_spi;
 	bool attach_cptlf;
+	bool wqe_skip;
 };
 
 int nix_inl_sso_register_irqs(struct nix_inl_dev *inl_dev);
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 617364f..4f98a38 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -156,6 +156,7 @@ INTERNAL {
 	roc_nix_inl_outb_is_enabled;
 	roc_nix_inl_sa_sync;
 	roc_nix_inl_ctx_write;
+	roc_nix_inl_dev_pffunc_get;
 	roc_nix_inl_inb_sa_init;
 	roc_nix_inl_outb_sa_init;
 	roc_nix_cpt_ctx_cache_sync;
diff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c
index 3fef056..ea204ca 100644
--- a/drivers/net/cnxk/cnxk_ethdev_sec.c
+++ b/drivers/net/cnxk/cnxk_ethdev_sec.c
@@ -278,6 +278,8 @@ cnxk_nix_inl_dev_probe(struct rte_pci_driver *pci_drv,
 	}
 
 	inl_dev->attach_cptlf = true;
+	/* WQE skip is one for DPDK */
+	inl_dev->wqe_skip = true;
 	rc = roc_nix_inl_dev_init(inl_dev);
 	if (rc) {
 		plt_err("Failed to init nix inl device, rc=%d(%s)", rc,
-- 
2.8.4

[PATCH 05/20] common/cnxk: use common SA init API for default options

[Nithin Dabilpuram]

From: Vidya Sagar Velumuri <vvelumuri@marvell.com>

Use common SA init API before doing initialization based on
params. This is better so that all HW specific default values
are at single place for lookaside and inline.

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/common/cnxk/cnxk_security.c   | 21 +++++++-----------
 drivers/common/cnxk/cnxk_security.h   |  3 ++-
 drivers/common/cnxk/meson.build       |  1 +
 drivers/common/cnxk/roc_ie_ot.c       | 41 +++++++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_ie_ot.h       | 11 ++++++----
 drivers/common/cnxk/roc_nix_inl.c     | 31 ++------------------------
 drivers/common/cnxk/roc_nix_inl.h     |  2 --
 drivers/common/cnxk/roc_nix_inl_dev.c |  2 +-
 drivers/common/cnxk/version.map       |  4 ++--
 drivers/crypto/cnxk/cn10k_ipsec.c     |  3 ++-
 drivers/net/cnxk/cn10k_ethdev_sec.c   |  7 +++---
 11 files changed, 70 insertions(+), 56 deletions(-)
 create mode 100644 drivers/common/cnxk/roc_ie_ot.c

diff --git a/drivers/common/cnxk/cnxk_security.c b/drivers/common/cnxk/cnxk_security.c
index 8b4dd1c..8696ff3 100644
--- a/drivers/common/cnxk/cnxk_security.c
+++ b/drivers/common/cnxk/cnxk_security.c
@@ -260,13 +260,17 @@ ot_ipsec_inb_tunnel_hdr_fill(struct roc_ot_ipsec_inb_sa *sa,
 int
 cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa,
 			  struct rte_security_ipsec_xform *ipsec_xfrm,
-			  struct rte_crypto_sym_xform *crypto_xfrm)
+			  struct rte_crypto_sym_xform *crypto_xfrm,
+			  bool is_inline)
 {
 	union roc_ot_ipsec_sa_word2 w2;
 	uint32_t replay_win_sz;
 	size_t offset;
 	int rc;
 
+	/* Initialize the SA */
+	roc_ot_ipsec_inb_sa_init(sa, is_inline);
+
 	w2.u64 = 0;
 	rc = ot_ipsec_sa_common_param_fill(&w2, sa->cipher_key, sa->w8.s.salt,
 					   sa->hmac_opad_ipad, ipsec_xfrm,
@@ -291,13 +295,6 @@ cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa,
 	if (rc)
 		return rc;
 
-	/* Default options for pkt_out and pkt_fmt are with
-	 * second pass meta and no defrag.
-	 */
-	sa->w0.s.pkt_format = ROC_IE_OT_SA_PKT_FMT_META;
-	sa->w0.s.pkt_output = ROC_IE_OT_SA_PKT_OUTPUT_HW_BASED_DEFRAG;
-	sa->w0.s.pkind = ROC_OT_CPT_META_PKIND;
-
 	/* ESN */
 	sa->w2.s.esn_en = !!ipsec_xfrm->options.esn;
 	if (ipsec_xfrm->options.udp_encap) {
@@ -346,11 +343,6 @@ cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa,
 		sa->w0.s.hard_life_dec = 1;
 	}
 
-	/* There are two words of CPT_CTX_HW_S for ucode to skip */
-	sa->w0.s.ctx_hdr_size = 1;
-	sa->w0.s.aop_valid = 1;
-	sa->w0.s.et_ovrwr = 1;
-
 	rte_wmb();
 
 	/* Enable SA */
@@ -368,6 +360,9 @@ cnxk_ot_ipsec_outb_sa_fill(struct roc_ot_ipsec_outb_sa *sa,
 	size_t offset;
 	int rc;
 
+	/* Initialize the SA */
+	roc_ot_ipsec_outb_sa_init(sa);
+
 	w2.u64 = 0;
 	rc = ot_ipsec_sa_common_param_fill(&w2, sa->cipher_key, sa->iv.s.salt,
 					   sa->hmac_opad_ipad, ipsec_xfrm,
diff --git a/drivers/common/cnxk/cnxk_security.h b/drivers/common/cnxk/cnxk_security.h
index db97887..02cdad2 100644
--- a/drivers/common/cnxk/cnxk_security.h
+++ b/drivers/common/cnxk/cnxk_security.h
@@ -38,7 +38,8 @@ cnxk_ipsec_outb_roundup_byte(enum rte_crypto_cipher_algorithm c_algo,
 int __roc_api
 cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa,
 			  struct rte_security_ipsec_xform *ipsec_xfrm,
-			  struct rte_crypto_sym_xform *crypto_xfrm);
+			  struct rte_crypto_sym_xform *crypto_xfrm,
+			  bool is_inline);
 int __roc_api
 cnxk_ot_ipsec_outb_sa_fill(struct roc_ot_ipsec_outb_sa *sa,
 			   struct rte_security_ipsec_xform *ipsec_xfrm,
diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 7e27b3c..928500b 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -23,6 +23,7 @@ sources = files(
         'roc_hash.c',
         'roc_idev.c',
         'roc_irq.c',
+        'roc_ie_ot.c',
         'roc_mbox.c',
         'roc_model.c',
         'roc_nix.c',
diff --git a/drivers/common/cnxk/roc_ie_ot.c b/drivers/common/cnxk/roc_ie_ot.c
new file mode 100644
index 0000000..1ea7bfd
--- /dev/null
+++ b/drivers/common/cnxk/roc_ie_ot.c
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2022 Marvell.
+ */
+
+#include "roc_api.h"
+#include "roc_priv.h"
+
+void
+roc_ot_ipsec_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa, bool is_inline)
+{
+	size_t offset;
+
+	memset(sa, 0, sizeof(struct roc_ot_ipsec_inb_sa));
+
+	if (is_inline) {
+		sa->w0.s.pkt_output = ROC_IE_OT_SA_PKT_OUTPUT_NO_FRAG;
+		sa->w0.s.pkt_format = ROC_IE_OT_SA_PKT_FMT_META;
+		sa->w0.s.pkind = ROC_IE_OT_CPT_PKIND;
+		sa->w0.s.et_ovrwr = 1;
+	}
+
+	offset = offsetof(struct roc_ot_ipsec_inb_sa, ctx);
+	sa->w0.s.hw_ctx_off = offset / ROC_CTX_UNIT_8B;
+	sa->w0.s.ctx_push_size = sa->w0.s.hw_ctx_off + 1;
+	sa->w0.s.ctx_size = ROC_IE_OT_CTX_ILEN;
+	sa->w0.s.ctx_hdr_size = ROC_IE_OT_SA_CTX_HDR_SIZE;
+	sa->w0.s.aop_valid = 1;
+}
+
+void
+roc_ot_ipsec_outb_sa_init(struct roc_ot_ipsec_outb_sa *sa)
+{
+	size_t offset;
+
+	memset(sa, 0, sizeof(struct roc_ot_ipsec_outb_sa));
+
+	offset = offsetof(struct roc_ot_ipsec_outb_sa, ctx);
+	sa->w0.s.ctx_push_size = (offset / ROC_CTX_UNIT_8B) + 1;
+	sa->w0.s.ctx_size = ROC_IE_OT_CTX_ILEN;
+	sa->w0.s.aop_valid = 1;
+}
diff --git a/drivers/common/cnxk/roc_ie_ot.h b/drivers/common/cnxk/roc_ie_ot.h
index 5b61902..2b4f5d3 100644
--- a/drivers/common/cnxk/roc_ie_ot.h
+++ b/drivers/common/cnxk/roc_ie_ot.h
@@ -1,13 +1,10 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2021 Marvell.
+ * Copyright(C) 2022 Marvell.
  */
 
 #ifndef __ROC_IE_OT_H__
 #define __ROC_IE_OT_H__
 
-/* PKIND to be used for CPT Meta parsing */
-#define ROC_OT_CPT_META_PKIND 58
-
 /* CN10K IPSEC opcodes */
 #define ROC_IE_OT_MAJOR_OP_PROCESS_OUTBOUND_IPSEC 0x28UL
 #define ROC_IE_OT_MAJOR_OP_PROCESS_INBOUND_IPSEC  0x29UL
@@ -16,6 +13,9 @@
 #define ROC_IE_OT_MINOR_OP_WRITE_SA 0x09UL
 
 #define ROC_IE_OT_CTX_ILEN 2
+/* PKIND to be used for CPT Meta parsing */
+#define ROC_IE_OT_CPT_PKIND	  58
+#define ROC_IE_OT_SA_CTX_HDR_SIZE 1
 
 enum roc_ie_ot_ucc_ipsec {
 	ROC_IE_OT_UCC_SUCCESS = 0x00,
@@ -517,4 +517,7 @@ PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, hmac_opad_ipad) ==
 PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, ctx) ==
 		  31 * sizeof(uint64_t));
 
+void __roc_api roc_ot_ipsec_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa,
+					bool is_inline);
+void __roc_api roc_ot_ipsec_outb_sa_init(struct roc_ot_ipsec_outb_sa *sa);
 #endif /* __ROC_IE_OT_H__ */
diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index 356d11d..f57f1a4 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -43,7 +43,7 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
 	if (roc_model_is_cn10k()) {
 		for (i = 0; i < ipsec_in_max_spi; i++) {
 			sa = ((uint8_t *)nix->inb_sa_base) + (i * inb_sa_sz);
-			roc_nix_inl_inb_sa_init(sa);
+			roc_ot_ipsec_inb_sa_init(sa, true);
 		}
 	}
 
@@ -401,7 +401,7 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
 	if (roc_model_is_cn10k()) {
 		for (i = 0; i < roc_nix->ipsec_out_max_sa; i++) {
 			sa = ((uint8_t *)sa_base) + (i * sa_sz);
-			roc_nix_inl_outb_sa_init(sa);
+			roc_ot_ipsec_outb_sa_init(sa);
 		}
 	}
 	nix->outb_sa_base = sa_base;
@@ -867,33 +867,6 @@ roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, void *sa_cptr,
 }
 
 void
-roc_nix_inl_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa)
-{
-	size_t offset;
-
-	memset(sa, 0, sizeof(struct roc_ot_ipsec_inb_sa));
-
-	offset = offsetof(struct roc_ot_ipsec_inb_sa, ctx);
-	sa->w0.s.hw_ctx_off = offset / ROC_CTX_UNIT_8B;
-	sa->w0.s.ctx_push_size = sa->w0.s.hw_ctx_off + 1;
-	sa->w0.s.ctx_size = ROC_IE_OT_CTX_ILEN;
-	sa->w0.s.aop_valid = 1;
-}
-
-void
-roc_nix_inl_outb_sa_init(struct roc_ot_ipsec_outb_sa *sa)
-{
-	size_t offset;
-
-	memset(sa, 0, sizeof(struct roc_ot_ipsec_outb_sa));
-
-	offset = offsetof(struct roc_ot_ipsec_outb_sa, ctx);
-	sa->w0.s.ctx_push_size = (offset / ROC_CTX_UNIT_8B);
-	sa->w0.s.ctx_size = ROC_IE_OT_CTX_ILEN;
-	sa->w0.s.aop_valid = 1;
-}
-
-void
 roc_nix_inl_dev_lock(void)
 {
 	struct idev_cfg *idev = idev_get_cfg();
diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h
index ceeccab..224aaba 100644
--- a/drivers/common/cnxk/roc_nix_inl.h
+++ b/drivers/common/cnxk/roc_nix_inl.h
@@ -171,7 +171,5 @@ int __roc_api roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa, bool inb,
 				  enum roc_nix_inl_sa_sync_op op);
 int __roc_api roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr,
 				    void *sa_cptr, bool inb, uint16_t sa_len);
-void __roc_api roc_nix_inl_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa);
-void __roc_api roc_nix_inl_outb_sa_init(struct roc_ot_ipsec_outb_sa *sa);
 
 #endif /* _ROC_NIX_INL_H_ */
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c
index 12160e9..9dc0a62 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -397,7 +397,7 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev)
 		for (i = 0; i < ipsec_in_max_spi; i++) {
 			sa = ((uint8_t *)inl_dev->inb_sa_base) +
 			     (i * inb_sa_sz);
-			roc_nix_inl_inb_sa_init(sa);
+			roc_ot_ipsec_inb_sa_init(sa, true);
 		}
 	}
 	/* Setup device specific inb SA table */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 4f98a38..a5ea244 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -157,8 +157,6 @@ INTERNAL {
 	roc_nix_inl_sa_sync;
 	roc_nix_inl_ctx_write;
 	roc_nix_inl_dev_pffunc_get;
-	roc_nix_inl_inb_sa_init;
-	roc_nix_inl_outb_sa_init;
 	roc_nix_cpt_ctx_cache_sync;
 	roc_nix_is_lbk;
 	roc_nix_is_pf;
@@ -322,6 +320,8 @@ INTERNAL {
 	roc_npc_mcam_read_counter;
 	roc_npc_profile_name_get;
 	roc_npc_validate_portid_action;
+	roc_ot_ipsec_inb_sa_init;
+	roc_ot_ipsec_outb_sa_init;
 	roc_plt_init;
 	roc_plt_init_cb_register;
 	roc_sso_dev_fini;
diff --git a/drivers/crypto/cnxk/cn10k_ipsec.c b/drivers/crypto/cnxk/cn10k_ipsec.c
index 27df1dc..308e518 100644
--- a/drivers/crypto/cnxk/cn10k_ipsec.c
+++ b/drivers/crypto/cnxk/cn10k_ipsec.c
@@ -128,7 +128,8 @@ cn10k_ipsec_inb_sa_create(struct roc_cpt *roc_cpt,
 	in_sa = &sa->in_sa;
 
 	/* Translate security parameters to SA */
-	ret = cnxk_ot_ipsec_inb_sa_fill(in_sa, ipsec_xfrm, crypto_xfrm);
+	ret = cnxk_ot_ipsec_inb_sa_fill(in_sa, ipsec_xfrm, crypto_xfrm,
+					false);
 	if (ret)
 		return ret;
 
diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c
index 12cec0a..6fbf444 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -319,7 +319,8 @@ cn10k_eth_sec_session_create(void *device,
 		memset(inb_sa_dptr, 0, sizeof(struct roc_ot_ipsec_inb_sa));
 
 		/* Fill inbound sa params */
-		rc = cnxk_ot_ipsec_inb_sa_fill(inb_sa_dptr, ipsec, crypto);
+		rc = cnxk_ot_ipsec_inb_sa_fill(inb_sa_dptr, ipsec, crypto,
+					       true);
 		if (rc) {
 			snprintf(tbuf, sizeof(tbuf),
 				 "Failed to init inbound sa, rc=%d", rc);
@@ -464,7 +465,7 @@ cn10k_eth_sec_session_destroy(void *device, struct rte_security_session *sess)
 	if (eth_sec->inb) {
 		/* Disable SA */
 		sa_dptr = dev->inb.sa_dptr;
-		roc_nix_inl_inb_sa_init(sa_dptr);
+		roc_ot_ipsec_inb_sa_init(sa_dptr, true);
 
 		roc_nix_inl_ctx_write(&dev->nix, sa_dptr, eth_sec->sa,
 				      eth_sec->inb,
@@ -474,7 +475,7 @@ cn10k_eth_sec_session_destroy(void *device, struct rte_security_session *sess)
 	} else {
 		/* Disable SA */
 		sa_dptr = dev->outb.sa_dptr;
-		roc_nix_inl_outb_sa_init(sa_dptr);
+		roc_ot_ipsec_outb_sa_init(sa_dptr);
 
 		roc_nix_inl_ctx_write(&dev->nix, sa_dptr, eth_sec->sa,
 				      eth_sec->inb,
-- 
2.8.4

[PATCH 06/20] common/cnxk: enable l3hdr write back in SA

[Nithin Dabilpuram]

From: Vidya Sagar Velumuri <vvelumuri@marvell.com>

Enable the field in SA to write back l2, l3 hdrs in case of errors
during inline processing.

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
---
 drivers/common/cnxk/roc_ie_ot.c | 1 +
 drivers/common/cnxk/roc_ie_ot.h | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/roc_ie_ot.c b/drivers/common/cnxk/roc_ie_ot.c
index 1ea7bfd..d0b7ad3 100644
--- a/drivers/common/cnxk/roc_ie_ot.c
+++ b/drivers/common/cnxk/roc_ie_ot.c
@@ -17,6 +17,7 @@ roc_ot_ipsec_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa, bool is_inline)
 		sa->w0.s.pkt_format = ROC_IE_OT_SA_PKT_FMT_META;
 		sa->w0.s.pkind = ROC_IE_OT_CPT_PKIND;
 		sa->w0.s.et_ovrwr = 1;
+		sa->w2.s.l3hdr_on_err = 1;
 	}
 
 	offset = offsetof(struct roc_ot_ipsec_inb_sa, ctx);
diff --git a/drivers/common/cnxk/roc_ie_ot.h b/drivers/common/cnxk/roc_ie_ot.h
index 2b4f5d3..1029d1e 100644
--- a/drivers/common/cnxk/roc_ie_ot.h
+++ b/drivers/common/cnxk/roc_ie_ot.h
@@ -336,7 +336,8 @@ struct roc_ot_ipsec_inb_sa {
 			uint64_t ip_hdr_verify : 2;
 			uint64_t udp_ports_verify : 1;
 
-			uint64_t rsvd6 : 7;
+			uint64_t l3hdr_on_err : 1;
+			uint64_t rsvd6 : 6;
 			uint64_t async_mode : 1;
 
 			uint64_t spi : 32;
-- 
2.8.4

[PATCH 07/20] common/cnxk: support to enable aura tail drop for RQ

[Nithin Dabilpuram]

Add support to enable aura tail drop via RQ specifically
for inline device RQ's pkt pool. This is better than RQ
red drop as it can be applied to all RQ's that are not
having security enabled but using same packet pool.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/common/cnxk/roc_nix.h          |  4 ++++
 drivers/common/cnxk/roc_nix_inl.c      | 39 ++++++++++++++++++++++++++++++----
 drivers/common/cnxk/roc_nix_inl.h      |  2 ++
 drivers/common/cnxk/roc_nix_inl_dev.c  |  9 ++++++++
 drivers/common/cnxk/roc_nix_inl_priv.h |  2 ++
 drivers/common/cnxk/roc_nix_queue.c    |  6 +++++-
 drivers/common/cnxk/roc_npa.c          | 33 ++++++++++++++++++++++++++--
 drivers/common/cnxk/roc_npa.h          |  3 +++
 drivers/common/cnxk/version.map        |  1 +
 9 files changed, 92 insertions(+), 7 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 250e1c0..0122b98 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -286,6 +286,10 @@ struct roc_nix_rq {
 	uint8_t spb_red_drop;
 	/* Average SPB aura level pass threshold for RED */
 	uint8_t spb_red_pass;
+	/* LPB aura drop enable */
+	bool lpb_drop_ena;
+	/* SPB aura drop enable */
+	bool spb_drop_ena;
 	/* End of Input parameters */
 	struct roc_nix *roc_nix;
 	bool inl_dev_ref;
diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index f57f1a4..ac17e95 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -528,23 +528,50 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq)
 	inl_rq->first_skip = rq->first_skip;
 	inl_rq->later_skip = rq->later_skip;
 	inl_rq->lpb_size = rq->lpb_size;
+	inl_rq->lpb_drop_ena = true;
+	inl_rq->spb_ena = rq->spb_ena;
+	inl_rq->spb_aura_handle = rq->spb_aura_handle;
+	inl_rq->spb_size = rq->spb_size;
+	inl_rq->spb_drop_ena = !!rq->spb_ena;
 
 	if (!roc_model_is_cn9k()) {
 		uint64_t aura_limit =
 			roc_npa_aura_op_limit_get(inl_rq->aura_handle);
 		uint64_t aura_shift = plt_log2_u32(aura_limit);
+		uint64_t aura_drop, drop_pc;
 
 		if (aura_shift < 8)
 			aura_shift = 0;
 		else
 			aura_shift = aura_shift - 8;
 
-		/* Set first pass RQ to drop when half of the buffers are in
+		/* Set first pass RQ to drop after part of buffers are in
 		 * use to avoid metabuf alloc failure. This is needed as long
-		 * as we cannot use different
+		 * as we cannot use different aura.
 		 */
-		inl_rq->red_pass = (aura_limit / 2) >> aura_shift;
-		inl_rq->red_drop = ((aura_limit / 2) - 1) >> aura_shift;
+		drop_pc = inl_dev->lpb_drop_pc;
+		aura_drop = ((aura_limit * drop_pc) / 100) >> aura_shift;
+		roc_npa_aura_drop_set(inl_rq->aura_handle, aura_drop, true);
+	}
+
+	if (inl_rq->spb_ena) {
+		uint64_t aura_limit =
+			roc_npa_aura_op_limit_get(inl_rq->spb_aura_handle);
+		uint64_t aura_shift = plt_log2_u32(aura_limit);
+		uint64_t aura_drop, drop_pc;
+
+		if (aura_shift < 8)
+			aura_shift = 0;
+		else
+			aura_shift = aura_shift - 8;
+
+		/* Set first pass RQ to drop after part of buffers are in
+		 * use to avoid metabuf alloc failure. This is needed as long
+		 * as we cannot use different aura.
+		 */
+		drop_pc = inl_dev->spb_drop_pc;
+		aura_drop = ((aura_limit * drop_pc) / 100) >> aura_shift;
+		roc_npa_aura_drop_set(inl_rq->spb_aura_handle, aura_drop, true);
 	}
 
 	/* Enable IPSec */
@@ -613,6 +640,10 @@ roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq)
 	if (rc)
 		plt_err("Failed to disable inline device rq, rc=%d", rc);
 
+	roc_npa_aura_drop_set(inl_rq->aura_handle, 0, false);
+	if (inl_rq->spb_ena)
+		roc_npa_aura_drop_set(inl_rq->spb_aura_handle, 0, false);
+
 	/* Flush NIX LF for CN10K */
 	nix_rq_vwqe_flush(rq, inl_dev->vwqe_interval);
 
diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h
index 224aaba..728225b 100644
--- a/drivers/common/cnxk/roc_nix_inl.h
+++ b/drivers/common/cnxk/roc_nix_inl.h
@@ -112,6 +112,8 @@ struct roc_nix_inl_dev {
 	uint16_t chan_mask;
 	bool attach_cptlf;
 	bool wqe_skip;
+	uint8_t spb_drop_pc;
+	uint8_t lpb_drop_pc;
 	/* End of input parameters */
 
 #define ROC_NIX_INL_MEM_SZ (1280)
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c
index 9dc0a62..4c1d85a 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -5,6 +5,8 @@
 #include "roc_api.h"
 #include "roc_priv.h"
 
+#define NIX_AURA_DROP_PC_DFLT 40
+
 /* Default Rx Config for Inline NIX LF */
 #define NIX_INL_LF_RX_CFG                                                      \
 	(ROC_NIX_LF_RX_CFG_DROP_RE | ROC_NIX_LF_RX_CFG_L2_LEN_ERR |            \
@@ -662,6 +664,13 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)
 	inl_dev->chan_mask = roc_inl_dev->chan_mask;
 	inl_dev->attach_cptlf = roc_inl_dev->attach_cptlf;
 	inl_dev->wqe_skip = roc_inl_dev->wqe_skip;
+	inl_dev->spb_drop_pc = NIX_AURA_DROP_PC_DFLT;
+	inl_dev->lpb_drop_pc = NIX_AURA_DROP_PC_DFLT;
+
+	if (roc_inl_dev->spb_drop_pc)
+		inl_dev->spb_drop_pc = roc_inl_dev->spb_drop_pc;
+	if (roc_inl_dev->lpb_drop_pc)
+		inl_dev->lpb_drop_pc = roc_inl_dev->lpb_drop_pc;
 
 	/* Initialize base device */
 	rc = dev_init(&inl_dev->dev, pci_dev);
diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h
index dcf752e..b6d8602 100644
--- a/drivers/common/cnxk/roc_nix_inl_priv.h
+++ b/drivers/common/cnxk/roc_nix_inl_priv.h
@@ -43,6 +43,8 @@ struct nix_inl_dev {
 	struct roc_nix_rq rq;
 	uint16_t rq_refs;
 	bool is_nix1;
+	uint8_t spb_drop_pc;
+	uint8_t lpb_drop_pc;
 
 	/* NIX/CPT data */
 	void *inb_sa_base;
diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c
index a283d96..7d27185 100644
--- a/drivers/common/cnxk/roc_nix_queue.c
+++ b/drivers/common/cnxk/roc_nix_queue.c
@@ -299,7 +299,9 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,
 	aq->rq.rq_int_ena = 0;
 	/* Many to one reduction */
 	aq->rq.qint_idx = rq->qid % qints;
-	aq->rq.xqe_drop_ena = 1;
+	aq->rq.xqe_drop_ena = 0;
+	aq->rq.lpb_drop_ena = rq->lpb_drop_ena;
+	aq->rq.spb_drop_ena = rq->spb_drop_ena;
 
 	/* If RED enabled, then fill enable for all cases */
 	if (rq->red_pass && (rq->red_pass >= rq->red_drop)) {
@@ -366,6 +368,8 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,
 		aq->rq_mask.rq_int_ena = ~aq->rq_mask.rq_int_ena;
 		aq->rq_mask.qint_idx = ~aq->rq_mask.qint_idx;
 		aq->rq_mask.xqe_drop_ena = ~aq->rq_mask.xqe_drop_ena;
+		aq->rq_mask.lpb_drop_ena = ~aq->rq_mask.lpb_drop_ena;
+		aq->rq_mask.spb_drop_ena = ~aq->rq_mask.spb_drop_ena;
 
 		if (rq->red_pass && (rq->red_pass >= rq->red_drop)) {
 			aq->rq_mask.spb_pool_pass = ~aq->rq_mask.spb_pool_pass;
diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c
index 75fc224..1e60f44 100644
--- a/drivers/common/cnxk/roc_npa.c
+++ b/drivers/common/cnxk/roc_npa.c
@@ -193,6 +193,35 @@ roc_npa_pool_op_pc_reset(uint64_t aura_handle)
 	}
 	return 0;
 }
+
+int
+roc_npa_aura_drop_set(uint64_t aura_handle, uint64_t limit, bool ena)
+{
+	struct npa_aq_enq_req *aura_req;
+	struct npa_lf *lf;
+	int rc;
+
+	lf = idev_npa_obj_get();
+	if (lf == NULL)
+		return NPA_ERR_DEVICE_NOT_BOUNDED;
+
+	aura_req = mbox_alloc_msg_npa_aq_enq(lf->mbox);
+	if (aura_req == NULL)
+		return -ENOMEM;
+	aura_req->aura_id = roc_npa_aura_handle_to_aura(aura_handle);
+	aura_req->ctype = NPA_AQ_CTYPE_AURA;
+	aura_req->op = NPA_AQ_INSTOP_WRITE;
+
+	aura_req->aura.aura_drop_ena = ena;
+	aura_req->aura.aura_drop = limit;
+	aura_req->aura_mask.aura_drop_ena =
+		~(aura_req->aura_mask.aura_drop_ena);
+	aura_req->aura_mask.aura_drop = ~(aura_req->aura_mask.aura_drop);
+	rc = mbox_process(lf->mbox);
+
+	return rc;
+}
+
 static inline char *
 npa_stack_memzone_name(struct npa_lf *lf, int pool_id, char *name)
 {
@@ -299,7 +328,7 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size,
 	aura->err_int_ena |= BIT(NPA_AURA_ERR_INT_AURA_ADD_UNDER);
 	aura->err_int_ena |= BIT(NPA_AURA_ERR_INT_AURA_FREE_UNDER);
 	aura->err_int_ena |= BIT(NPA_AURA_ERR_INT_POOL_DIS);
-	aura->avg_con = ROC_NPA_AVG_CONT;
+	aura->avg_con = 0;
 	/* Many to one reduction */
 	aura->err_qint_idx = aura_id % lf->qints;
 
@@ -316,7 +345,7 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size,
 	pool->err_int_ena = BIT(NPA_POOL_ERR_INT_OVFLS);
 	pool->err_int_ena |= BIT(NPA_POOL_ERR_INT_RANGE);
 	pool->err_int_ena |= BIT(NPA_POOL_ERR_INT_PERR);
-	pool->avg_con = ROC_NPA_AVG_CONT;
+	pool->avg_con = 0;
 
 	/* Many to one reduction */
 	pool->err_qint_idx = pool_id % lf->qints;
diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h
index 9f5fe5a..0339876bf 100644
--- a/drivers/common/cnxk/roc_npa.h
+++ b/drivers/common/cnxk/roc_npa.h
@@ -731,4 +731,7 @@ int __roc_api roc_npa_dump(void);
 /* Reset operation performance counter. */
 int __roc_api roc_npa_pool_op_pc_reset(uint64_t aura_handle);
 
+int __roc_api roc_npa_aura_drop_set(uint64_t aura_handle, uint64_t limit,
+				    bool ena);
+
 #endif /* _ROC_NPA_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index a5ea244..7a8aff1 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -285,6 +285,7 @@ INTERNAL {
 	roc_nix_vlan_mcam_entry_write;
 	roc_nix_vlan_strip_vtag_ena_dis;
 	roc_nix_vlan_tpid_set;
+	roc_npa_aura_drop_set;
 	roc_npa_aura_limit_modify;
 	roc_npa_aura_op_range_set;
 	roc_npa_ctx_dump;
-- 
2.8.4

Re: [PATCH 07/20] common/cnxk: support to enable aura tail drop for RQ

[Jerin Jacob]

On Mon, Feb 7, 2022 at 1:01 PM Nithin Dabilpuram
<ndabilpuram@marvell.com> wrote:
>
> Add support to enable aura tail drop via RQ specifically

aura-> AURA

> for inline device RQ's pkt pool. This is better than RQ
> red drop as it can be applied to all RQ's that are not

red->RED


> having security enabled but using same packet pool.

aura-> AURA in subject



>
> Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
> ---
>  drivers/common/cnxk/roc_nix.h          |  4 ++++
>  drivers/common/cnxk/roc_nix_inl.c      | 39 ++++++++++++++++++++++++++++++----
>  drivers/common/cnxk/roc_nix_inl.h      |  2 ++
>  drivers/common/cnxk/roc_nix_inl_dev.c  |  9 ++++++++
>  drivers/common/cnxk/roc_nix_inl_priv.h |  2 ++
>  drivers/common/cnxk/roc_nix_queue.c    |  6 +++++-
>  drivers/common/cnxk/roc_npa.c          | 33 ++++++++++++++++++++++++++--
>  drivers/common/cnxk/roc_npa.h          |  3 +++
>  drivers/common/cnxk/version.map        |  1 +
>  9 files changed, 92 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
> index 250e1c0..0122b98 100644
> --- a/drivers/common/cnxk/roc_nix.h
> +++ b/drivers/common/cnxk/roc_nix.h
> @@ -286,6 +286,10 @@ struct roc_nix_rq {
>         uint8_t spb_red_drop;
>         /* Average SPB aura level pass threshold for RED */
>         uint8_t spb_red_pass;
> +       /* LPB aura drop enable */
> +       bool lpb_drop_ena;
> +       /* SPB aura drop enable */
> +       bool spb_drop_ena;
>         /* End of Input parameters */
>         struct roc_nix *roc_nix;
>         bool inl_dev_ref;
> diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
> index f57f1a4..ac17e95 100644
> --- a/drivers/common/cnxk/roc_nix_inl.c
> +++ b/drivers/common/cnxk/roc_nix_inl.c
> @@ -528,23 +528,50 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq)
>         inl_rq->first_skip = rq->first_skip;
>         inl_rq->later_skip = rq->later_skip;
>         inl_rq->lpb_size = rq->lpb_size;
> +       inl_rq->lpb_drop_ena = true;
> +       inl_rq->spb_ena = rq->spb_ena;
> +       inl_rq->spb_aura_handle = rq->spb_aura_handle;
> +       inl_rq->spb_size = rq->spb_size;
> +       inl_rq->spb_drop_ena = !!rq->spb_ena;
>
>         if (!roc_model_is_cn9k()) {
>                 uint64_t aura_limit =
>                         roc_npa_aura_op_limit_get(inl_rq->aura_handle);
>                 uint64_t aura_shift = plt_log2_u32(aura_limit);
> +               uint64_t aura_drop, drop_pc;
>
>                 if (aura_shift < 8)
>                         aura_shift = 0;
>                 else
>                         aura_shift = aura_shift - 8;
>
> -               /* Set first pass RQ to drop when half of the buffers are in
> +               /* Set first pass RQ to drop after part of buffers are in
>                  * use to avoid metabuf alloc failure. This is needed as long
> -                * as we cannot use different
> +                * as we cannot use different aura.
>                  */
> -               inl_rq->red_pass = (aura_limit / 2) >> aura_shift;
> -               inl_rq->red_drop = ((aura_limit / 2) - 1) >> aura_shift;
> +               drop_pc = inl_dev->lpb_drop_pc;
> +               aura_drop = ((aura_limit * drop_pc) / 100) >> aura_shift;
> +               roc_npa_aura_drop_set(inl_rq->aura_handle, aura_drop, true);
> +       }
> +
> +       if (inl_rq->spb_ena) {
> +               uint64_t aura_limit =
> +                       roc_npa_aura_op_limit_get(inl_rq->spb_aura_handle);
> +               uint64_t aura_shift = plt_log2_u32(aura_limit);
> +               uint64_t aura_drop, drop_pc;
> +
> +               if (aura_shift < 8)
> +                       aura_shift = 0;
> +               else
> +                       aura_shift = aura_shift - 8;
> +
> +               /* Set first pass RQ to drop after part of buffers are in
> +                * use to avoid metabuf alloc failure. This is needed as long
> +                * as we cannot use different aura.
> +                */
> +               drop_pc = inl_dev->spb_drop_pc;
> +               aura_drop = ((aura_limit * drop_pc) / 100) >> aura_shift;
> +               roc_npa_aura_drop_set(inl_rq->spb_aura_handle, aura_drop, true);
>         }
>
>         /* Enable IPSec */
> @@ -613,6 +640,10 @@ roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq)
>         if (rc)
>                 plt_err("Failed to disable inline device rq, rc=%d", rc);
>
> +       roc_npa_aura_drop_set(inl_rq->aura_handle, 0, false);
> +       if (inl_rq->spb_ena)
> +               roc_npa_aura_drop_set(inl_rq->spb_aura_handle, 0, false);
> +
>         /* Flush NIX LF for CN10K */
>         nix_rq_vwqe_flush(rq, inl_dev->vwqe_interval);
>
> diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h
> index 224aaba..728225b 100644
> --- a/drivers/common/cnxk/roc_nix_inl.h
> +++ b/drivers/common/cnxk/roc_nix_inl.h
> @@ -112,6 +112,8 @@ struct roc_nix_inl_dev {
>         uint16_t chan_mask;
>         bool attach_cptlf;
>         bool wqe_skip;
> +       uint8_t spb_drop_pc;
> +       uint8_t lpb_drop_pc;
>         /* End of input parameters */
>
>  #define ROC_NIX_INL_MEM_SZ (1280)
> diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c
> index 9dc0a62..4c1d85a 100644
> --- a/drivers/common/cnxk/roc_nix_inl_dev.c
> +++ b/drivers/common/cnxk/roc_nix_inl_dev.c
> @@ -5,6 +5,8 @@
>  #include "roc_api.h"
>  #include "roc_priv.h"
>
> +#define NIX_AURA_DROP_PC_DFLT 40
> +
>  /* Default Rx Config for Inline NIX LF */
>  #define NIX_INL_LF_RX_CFG                                                      \
>         (ROC_NIX_LF_RX_CFG_DROP_RE | ROC_NIX_LF_RX_CFG_L2_LEN_ERR |            \
> @@ -662,6 +664,13 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)
>         inl_dev->chan_mask = roc_inl_dev->chan_mask;
>         inl_dev->attach_cptlf = roc_inl_dev->attach_cptlf;
>         inl_dev->wqe_skip = roc_inl_dev->wqe_skip;
> +       inl_dev->spb_drop_pc = NIX_AURA_DROP_PC_DFLT;
> +       inl_dev->lpb_drop_pc = NIX_AURA_DROP_PC_DFLT;
> +
> +       if (roc_inl_dev->spb_drop_pc)
> +               inl_dev->spb_drop_pc = roc_inl_dev->spb_drop_pc;
> +       if (roc_inl_dev->lpb_drop_pc)
> +               inl_dev->lpb_drop_pc = roc_inl_dev->lpb_drop_pc;
>
>         /* Initialize base device */
>         rc = dev_init(&inl_dev->dev, pci_dev);
> diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h
> index dcf752e..b6d8602 100644
> --- a/drivers/common/cnxk/roc_nix_inl_priv.h
> +++ b/drivers/common/cnxk/roc_nix_inl_priv.h
> @@ -43,6 +43,8 @@ struct nix_inl_dev {
>         struct roc_nix_rq rq;
>         uint16_t rq_refs;
>         bool is_nix1;
> +       uint8_t spb_drop_pc;
> +       uint8_t lpb_drop_pc;
>
>         /* NIX/CPT data */
>         void *inb_sa_base;
> diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c
> index a283d96..7d27185 100644
> --- a/drivers/common/cnxk/roc_nix_queue.c
> +++ b/drivers/common/cnxk/roc_nix_queue.c
> @@ -299,7 +299,9 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,
>         aq->rq.rq_int_ena = 0;
>         /* Many to one reduction */
>         aq->rq.qint_idx = rq->qid % qints;
> -       aq->rq.xqe_drop_ena = 1;
> +       aq->rq.xqe_drop_ena = 0;
> +       aq->rq.lpb_drop_ena = rq->lpb_drop_ena;
> +       aq->rq.spb_drop_ena = rq->spb_drop_ena;
>
>         /* If RED enabled, then fill enable for all cases */
>         if (rq->red_pass && (rq->red_pass >= rq->red_drop)) {
> @@ -366,6 +368,8 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,
>                 aq->rq_mask.rq_int_ena = ~aq->rq_mask.rq_int_ena;
>                 aq->rq_mask.qint_idx = ~aq->rq_mask.qint_idx;
>                 aq->rq_mask.xqe_drop_ena = ~aq->rq_mask.xqe_drop_ena;
> +               aq->rq_mask.lpb_drop_ena = ~aq->rq_mask.lpb_drop_ena;
> +               aq->rq_mask.spb_drop_ena = ~aq->rq_mask.spb_drop_ena;
>
>                 if (rq->red_pass && (rq->red_pass >= rq->red_drop)) {
>                         aq->rq_mask.spb_pool_pass = ~aq->rq_mask.spb_pool_pass;
> diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c
> index 75fc224..1e60f44 100644
> --- a/drivers/common/cnxk/roc_npa.c
> +++ b/drivers/common/cnxk/roc_npa.c
> @@ -193,6 +193,35 @@ roc_npa_pool_op_pc_reset(uint64_t aura_handle)
>         }
>         return 0;
>  }
> +
> +int
> +roc_npa_aura_drop_set(uint64_t aura_handle, uint64_t limit, bool ena)
> +{
> +       struct npa_aq_enq_req *aura_req;
> +       struct npa_lf *lf;
> +       int rc;
> +
> +       lf = idev_npa_obj_get();
> +       if (lf == NULL)
> +               return NPA_ERR_DEVICE_NOT_BOUNDED;
> +
> +       aura_req = mbox_alloc_msg_npa_aq_enq(lf->mbox);
> +       if (aura_req == NULL)
> +               return -ENOMEM;
> +       aura_req->aura_id = roc_npa_aura_handle_to_aura(aura_handle);
> +       aura_req->ctype = NPA_AQ_CTYPE_AURA;
> +       aura_req->op = NPA_AQ_INSTOP_WRITE;
> +
> +       aura_req->aura.aura_drop_ena = ena;
> +       aura_req->aura.aura_drop = limit;
> +       aura_req->aura_mask.aura_drop_ena =
> +               ~(aura_req->aura_mask.aura_drop_ena);
> +       aura_req->aura_mask.aura_drop = ~(aura_req->aura_mask.aura_drop);
> +       rc = mbox_process(lf->mbox);
> +
> +       return rc;
> +}
> +
>  static inline char *
>  npa_stack_memzone_name(struct npa_lf *lf, int pool_id, char *name)
>  {
> @@ -299,7 +328,7 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size,
>         aura->err_int_ena |= BIT(NPA_AURA_ERR_INT_AURA_ADD_UNDER);
>         aura->err_int_ena |= BIT(NPA_AURA_ERR_INT_AURA_FREE_UNDER);
>         aura->err_int_ena |= BIT(NPA_AURA_ERR_INT_POOL_DIS);
> -       aura->avg_con = ROC_NPA_AVG_CONT;
> +       aura->avg_con = 0;
>         /* Many to one reduction */
>         aura->err_qint_idx = aura_id % lf->qints;
>
> @@ -316,7 +345,7 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size,
>         pool->err_int_ena = BIT(NPA_POOL_ERR_INT_OVFLS);
>         pool->err_int_ena |= BIT(NPA_POOL_ERR_INT_RANGE);
>         pool->err_int_ena |= BIT(NPA_POOL_ERR_INT_PERR);
> -       pool->avg_con = ROC_NPA_AVG_CONT;
> +       pool->avg_con = 0;
>
>         /* Many to one reduction */
>         pool->err_qint_idx = pool_id % lf->qints;
> diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h
> index 9f5fe5a..0339876bf 100644
> --- a/drivers/common/cnxk/roc_npa.h
> +++ b/drivers/common/cnxk/roc_npa.h
> @@ -731,4 +731,7 @@ int __roc_api roc_npa_dump(void);
>  /* Reset operation performance counter. */
>  int __roc_api roc_npa_pool_op_pc_reset(uint64_t aura_handle);
>
> +int __roc_api roc_npa_aura_drop_set(uint64_t aura_handle, uint64_t limit,
> +                                   bool ena);
> +
>  #endif /* _ROC_NPA_H_ */
> diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
> index a5ea244..7a8aff1 100644
> --- a/drivers/common/cnxk/version.map
> +++ b/drivers/common/cnxk/version.map
> @@ -285,6 +285,7 @@ INTERNAL {
>         roc_nix_vlan_mcam_entry_write;
>         roc_nix_vlan_strip_vtag_ena_dis;
>         roc_nix_vlan_tpid_set;
> +       roc_npa_aura_drop_set;
>         roc_npa_aura_limit_modify;
>         roc_npa_aura_op_range_set;
>         roc_npa_ctx_dump;
> --
> 2.8.4
>

[PATCH 08/20] common/cnxk: use SSO time counter threshold for IRQ

[Nithin Dabilpuram]

Enable time counter based threshold for raising SSO
EXE_INT instead of IAQ threshold.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/common/cnxk/roc_nix_inl_dev_irq.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix_inl_dev_irq.c b/drivers/common/cnxk/roc_nix_inl_dev_irq.c
index d758e0c..8a0cb74 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev_irq.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev_irq.c
@@ -5,6 +5,8 @@
 #include "roc_api.h"
 #include "roc_priv.h"
 
+#define WORK_LIMIT 1000
+
 static void
 nix_inl_sso_work_cb(struct nix_inl_dev *inl_dev)
 {
@@ -15,6 +17,7 @@ nix_inl_sso_work_cb(struct nix_inl_dev *inl_dev)
 		__uint128_t get_work;
 		uint64_t u64[2];
 	} gw;
+	uint16_t cnt = 0;
 	uint64_t work;
 
 again:
@@ -33,7 +36,9 @@ nix_inl_sso_work_cb(struct nix_inl_dev *inl_dev)
 		else
 			plt_warn("Undelivered inl dev work gw0: %p gw1: %p",
 				 (void *)gw.u64[0], (void *)gw.u64[1]);
-		goto again;
+		cnt++;
+		if (cnt < WORK_LIMIT)
+			goto again;
 	}
 
 	plt_atomic_thread_fence(__ATOMIC_ACQ_REL);
@@ -138,8 +143,10 @@ nix_inl_sso_register_irqs(struct nix_inl_dev *inl_dev)
 	/* Enable hw interrupt */
 	plt_write64(~0ull, sso_base + SSO_LF_GGRP_INT_ENA_W1S);
 
-	/* Setup threshold for work exec interrupt to 1 wqe in IAQ */
-	plt_write64(0x1ull, sso_base + SSO_LF_GGRP_INT_THR);
+	/* Setup threshold for work exec interrupt to 100us timeout
+	 * based on time counter.
+	 */
+	plt_write64(BIT_ULL(63) | 10ULL << 48, sso_base + SSO_LF_GGRP_INT_THR);
 
 	return rc;
 }
-- 
2.8.4

Re: [PATCH 08/20] common/cnxk: use SSO time counter threshold for IRQ

[Jerin Jacob]

On Mon, Feb 7, 2022 at 1:00 PM Nithin Dabilpuram
<ndabilpuram@marvell.com> wrote:
>
> Enable time counter based threshold for raising SSO
> EXE_INT instead of IAQ threshold.

Please update the reason for doing the same.

>
> Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
> ---
>  drivers/common/cnxk/roc_nix_inl_dev_irq.c | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/common/cnxk/roc_nix_inl_dev_irq.c b/drivers/common/cnxk/roc_nix_inl_dev_irq.c
> index d758e0c..8a0cb74 100644
> --- a/drivers/common/cnxk/roc_nix_inl_dev_irq.c
> +++ b/drivers/common/cnxk/roc_nix_inl_dev_irq.c
> @@ -5,6 +5,8 @@
>  #include "roc_api.h"
>  #include "roc_priv.h"
>
> +#define WORK_LIMIT 1000
> +
>  static void
>  nix_inl_sso_work_cb(struct nix_inl_dev *inl_dev)
>  {
> @@ -15,6 +17,7 @@ nix_inl_sso_work_cb(struct nix_inl_dev *inl_dev)
>                 __uint128_t get_work;
>                 uint64_t u64[2];
>         } gw;
> +       uint16_t cnt = 0;
>         uint64_t work;
>
>  again:
> @@ -33,7 +36,9 @@ nix_inl_sso_work_cb(struct nix_inl_dev *inl_dev)
>                 else
>                         plt_warn("Undelivered inl dev work gw0: %p gw1: %p",
>                                  (void *)gw.u64[0], (void *)gw.u64[1]);
> -               goto again;
> +               cnt++;
> +               if (cnt < WORK_LIMIT)
> +                       goto again;
>         }
>
>         plt_atomic_thread_fence(__ATOMIC_ACQ_REL);
> @@ -138,8 +143,10 @@ nix_inl_sso_register_irqs(struct nix_inl_dev *inl_dev)
>         /* Enable hw interrupt */
>         plt_write64(~0ull, sso_base + SSO_LF_GGRP_INT_ENA_W1S);
>
> -       /* Setup threshold for work exec interrupt to 1 wqe in IAQ */
> -       plt_write64(0x1ull, sso_base + SSO_LF_GGRP_INT_THR);
> +       /* Setup threshold for work exec interrupt to 100us timeout
> +        * based on time counter.
> +        */
> +       plt_write64(BIT_ULL(63) | 10ULL << 48, sso_base + SSO_LF_GGRP_INT_THR);
>
>         return rc;
>  }
> --
> 2.8.4
>

[PATCH 09/20] common/cnxk: allow force use of SSO pffunc for outb inline

[Nithin Dabilpuram]

Allow force use of SSO pffunc even when inline dev is available
so that in case driver needs events directly delivered to
event device.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/common/cnxk/roc_nix.h     | 1 +
 drivers/common/cnxk/roc_nix_inl.c | 7 ++++++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 0122b98..57a595f 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -386,6 +386,7 @@ struct roc_nix {
 	uint16_t outb_nb_crypto_qs;
 	uint16_t ipsec_in_max_spi;
 	uint16_t ipsec_out_max_sa;
+	bool ipsec_out_sso_pffunc;
 	/* End of input parameters */
 	/* LMT line base for "Per Core Tx LMT line" mode*/
 	uintptr_t lmt_base;
diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index ac17e95..003f972 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -311,6 +311,10 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
 	/* Retrieve inline device if present */
 	inl_dev = idev->nix_inl_dev;
 	sso_pffunc = inl_dev ? inl_dev->dev.pf_func : idev_sso_pffunc_get();
+	/* Use sso_pffunc if explicitly requested */
+	if (roc_nix->ipsec_out_sso_pffunc)
+		sso_pffunc = idev_sso_pffunc_get();
+
 	if (!sso_pffunc) {
 		plt_err("Failed to setup inline outb, need either "
 			"inline device or sso device");
@@ -328,7 +332,8 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
 	eng_grpmask = (1ULL << ROC_CPT_DFLT_ENG_GRP_SE |
 		       1ULL << ROC_CPT_DFLT_ENG_GRP_SE_IE |
 		       1ULL << ROC_CPT_DFLT_ENG_GRP_AE);
-	rc = cpt_lfs_alloc(dev, eng_grpmask, blkaddr, true);
+	rc = cpt_lfs_alloc(dev, eng_grpmask, blkaddr,
+			   !roc_nix->ipsec_out_sso_pffunc);
 	if (rc) {
 		plt_err("Failed to alloc CPT LF resources, rc=%d", rc);
 		goto lf_detach;
-- 
2.8.4

[PATCH 10/20] net/cnxk: added Rx metadata negotiate operation

[Nithin Dabilpuram]

From: Satha Rao <skoteshwar@marvell.com>

Added rx_metadata_negotiate api to enable mark update RX offload.
Removed software logic to enable/disable mark update inside flow
create/destroy apis.

Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---
 drivers/net/cnxk/cn10k_ethdev.c   | 26 ++++++++++++++++++++++++++
 drivers/net/cnxk/cn10k_rte_flow.c | 20 ++------------------
 drivers/net/cnxk/cn9k_ethdev.c    | 25 +++++++++++++++++++++++++
 drivers/net/cnxk/cn9k_rte_flow.c  | 20 ++------------------
 drivers/net/cnxk/cnxk_ethdev.h    |  1 +
 5 files changed, 56 insertions(+), 36 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c
index 8378cbf..169e70e 100644
--- a/drivers/net/cnxk/cn10k_ethdev.c
+++ b/drivers/net/cnxk/cn10k_ethdev.c
@@ -39,6 +39,9 @@ nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
 	if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)
 		flags |= NIX_RX_OFFLOAD_SECURITY_F;
 
+	if (dev->rx_mark_update)
+		flags |= NIX_RX_OFFLOAD_MARK_UPDATE_F;
+
 	return flags;
 }
 
@@ -470,6 +473,27 @@ cn10k_nix_dev_start(struct rte_eth_dev *eth_dev)
 	return 0;
 }
 
+static int
+cn10k_nix_rx_metadata_negotiate(struct rte_eth_dev *eth_dev, uint64_t *features)
+{
+	struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+
+	*features &=
+		(RTE_ETH_RX_METADATA_USER_FLAG | RTE_ETH_RX_METADATA_USER_MARK);
+
+	if (*features) {
+		dev->rx_offload_flags |= NIX_RX_OFFLOAD_MARK_UPDATE_F;
+		dev->rx_mark_update = true;
+	} else {
+		dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_MARK_UPDATE_F;
+		dev->rx_mark_update = false;
+	}
+
+	cn10k_eth_set_rx_function(eth_dev);
+
+	return 0;
+}
+
 /* Update platform specific eth dev ops */
 static void
 nix_eth_dev_ops_override(void)
@@ -489,6 +513,8 @@ nix_eth_dev_ops_override(void)
 	cnxk_eth_dev_ops.dev_ptypes_set = cn10k_nix_ptypes_set;
 	cnxk_eth_dev_ops.timesync_enable = cn10k_nix_timesync_enable;
 	cnxk_eth_dev_ops.timesync_disable = cn10k_nix_timesync_disable;
+	cnxk_eth_dev_ops.rx_metadata_negotiate =
+		cn10k_nix_rx_metadata_negotiate;
 }
 
 static void
diff --git a/drivers/net/cnxk/cn10k_rte_flow.c b/drivers/net/cnxk/cn10k_rte_flow.c
index 529fb0e..ea71efa 100644
--- a/drivers/net/cnxk/cn10k_rte_flow.c
+++ b/drivers/net/cnxk/cn10k_rte_flow.c
@@ -131,9 +131,9 @@ cn10k_flow_create(struct rte_eth_dev *eth_dev, const struct rte_flow_attr *attr,
 	const struct rte_flow_action *action_rss = NULL;
 	const struct rte_flow_action_meter *mtr = NULL;
 	const struct rte_flow_action *act_q = NULL;
-	int mark_actions = 0, vtag_actions = 0;
 	struct roc_npc *npc = &dev->npc;
 	struct roc_npc_flow *flow;
+	int vtag_actions = 0;
 	uint32_t req_act = 0;
 	int i, rc;
 
@@ -197,13 +197,6 @@ cn10k_flow_create(struct rte_eth_dev *eth_dev, const struct rte_flow_attr *attr,
 			cn10k_mtr_connect(eth_dev, mtr->mtr_id);
 	}
 
-	mark_actions = roc_npc_mark_actions_get(npc);
-
-	if (mark_actions) {
-		dev->rx_offload_flags |= NIX_RX_OFFLOAD_MARK_UPDATE_F;
-		cn10k_eth_set_rx_function(eth_dev);
-	}
-
 	vtag_actions = roc_npc_vtag_actions_get(npc);
 
 	if (vtag_actions) {
@@ -220,20 +213,11 @@ cn10k_flow_destroy(struct rte_eth_dev *eth_dev, struct rte_flow *rte_flow,
 {
 	struct roc_npc_flow *flow = (struct roc_npc_flow *)rte_flow;
 	struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
-	int mark_actions = 0, vtag_actions = 0;
 	struct roc_npc *npc = &dev->npc;
+	int vtag_actions = 0;
 	uint32_t mtr_id;
 	int rc;
 
-	mark_actions = roc_npc_mark_actions_get(npc);
-	if (mark_actions) {
-		mark_actions = roc_npc_mark_actions_sub_return(npc, 1);
-		if (mark_actions == 0) {
-			dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_MARK_UPDATE_F;
-			cn10k_eth_set_rx_function(eth_dev);
-		}
-	}
-
 	vtag_actions = roc_npc_vtag_actions_get(npc);
 	if (vtag_actions) {
 		if (flow->nix_intf == ROC_NPC_INTF_RX) {
diff --git a/drivers/net/cnxk/cn9k_ethdev.c b/drivers/net/cnxk/cn9k_ethdev.c
index d34bc68..c44b5b4 100644
--- a/drivers/net/cnxk/cn9k_ethdev.c
+++ b/drivers/net/cnxk/cn9k_ethdev.c
@@ -39,6 +39,9 @@ nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
 	if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)
 		flags |= NIX_RX_OFFLOAD_SECURITY_F;
 
+	if (dev->rx_mark_update)
+		flags |= NIX_RX_OFFLOAD_MARK_UPDATE_F;
+
 	return flags;
 }
 
@@ -467,6 +470,27 @@ cn9k_nix_dev_start(struct rte_eth_dev *eth_dev)
 	return 0;
 }
 
+static int
+cn9k_nix_rx_metadata_negotiate(struct rte_eth_dev *eth_dev, uint64_t *features)
+{
+	struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+
+	*features &=
+		(RTE_ETH_RX_METADATA_USER_FLAG | RTE_ETH_RX_METADATA_USER_MARK);
+
+	if (*features) {
+		dev->rx_offload_flags |= NIX_RX_OFFLOAD_MARK_UPDATE_F;
+		dev->rx_mark_update = true;
+	} else {
+		dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_MARK_UPDATE_F;
+		dev->rx_mark_update = false;
+	}
+
+	cn9k_eth_set_rx_function(eth_dev);
+
+	return 0;
+}
+
 /* Update platform specific eth dev ops */
 static void
 nix_eth_dev_ops_override(void)
@@ -487,6 +511,7 @@ nix_eth_dev_ops_override(void)
 	cnxk_eth_dev_ops.timesync_enable = cn9k_nix_timesync_enable;
 	cnxk_eth_dev_ops.timesync_disable = cn9k_nix_timesync_disable;
 	cnxk_eth_dev_ops.mtr_ops_get = NULL;
+	cnxk_eth_dev_ops.rx_metadata_negotiate = cn9k_nix_rx_metadata_negotiate;
 }
 
 static void
diff --git a/drivers/net/cnxk/cn9k_rte_flow.c b/drivers/net/cnxk/cn9k_rte_flow.c
index b94d29e..7b98eb0 100644
--- a/drivers/net/cnxk/cn9k_rte_flow.c
+++ b/drivers/net/cnxk/cn9k_rte_flow.c
@@ -13,21 +13,14 @@ cn9k_flow_create(struct rte_eth_dev *eth_dev, const struct rte_flow_attr *attr,
 		 struct rte_flow_error *error)
 {
 	struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
-	int mark_actions = 0, vtag_actions = 0;
 	struct roc_npc *npc = &dev->npc;
 	struct roc_npc_flow *flow;
+	int vtag_actions = 0;
 
 	flow = cnxk_flow_create(eth_dev, attr, pattern, actions, error);
 	if (!flow)
 		return NULL;
 
-	mark_actions = roc_npc_mark_actions_get(npc);
-
-	if (mark_actions) {
-		dev->rx_offload_flags |= NIX_RX_OFFLOAD_MARK_UPDATE_F;
-		cn9k_eth_set_rx_function(eth_dev);
-	}
-
 	vtag_actions = roc_npc_vtag_actions_get(npc);
 
 	if (vtag_actions) {
@@ -44,17 +37,8 @@ cn9k_flow_destroy(struct rte_eth_dev *eth_dev, struct rte_flow *rte_flow,
 {
 	struct roc_npc_flow *flow = (struct roc_npc_flow *)rte_flow;
 	struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
-	int mark_actions = 0, vtag_actions = 0;
 	struct roc_npc *npc = &dev->npc;
-
-	mark_actions = roc_npc_mark_actions_get(npc);
-	if (mark_actions) {
-		mark_actions = roc_npc_mark_actions_sub_return(npc, 1);
-		if (mark_actions == 0) {
-			dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_MARK_UPDATE_F;
-			cn9k_eth_set_rx_function(eth_dev);
-		}
-	}
+	int vtag_actions = 0;
 
 	vtag_actions = roc_npc_vtag_actions_get(npc);
 	if (vtag_actions) {
diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h
index fadc8aa..f1363af 100644
--- a/drivers/net/cnxk/cnxk_ethdev.h
+++ b/drivers/net/cnxk/cnxk_ethdev.h
@@ -339,6 +339,7 @@ struct cnxk_eth_dev {
 	uint8_t ptype_disable;
 	bool scalar_ena;
 	bool ptp_en;
+	bool rx_mark_update; /* Enable/Disable mark update to mbuf */
 
 	/* Pointer back to rte */
 	struct rte_eth_dev *eth_dev;
-- 
2.8.4

Re: [PATCH 10/20] net/cnxk: added Rx metadata negotiate operation

[Jerin Jacob]

On Mon, Feb 7, 2022 at 1:01 PM Nithin Dabilpuram
<ndabilpuram@marvell.com> wrote:
>
> From: Satha Rao <skoteshwar@marvell.com>
>
> Added rx_metadata_negotiate api to enable mark update RX offload.
> Removed software logic to enable/disable mark update inside flow
> create/destroy apis.

APIs

> Signed-off-by: Satha Rao <skoteshwar@marvell.com>
> ---

> +static int
> +cn10k_nix_rx_metadata_negotiate(struct rte_eth_dev *eth_dev, uint64_t *features)
> +{
> +       struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
> +
> +       *features &=
> +               (RTE_ETH_RX_METADATA_USER_FLAG | RTE_ETH_RX_METADATA_USER_MARK);
> +
> +       if (*features) {
> +               dev->rx_offload_flags |= NIX_RX_OFFLOAD_MARK_UPDATE_F;
> +               dev->rx_mark_update = true;
> +       } else {
> +               dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_MARK_UPDATE_F;
> +               dev->rx_mark_update = false;
> +       }
> +
> +       cn10k_eth_set_rx_function(eth_dev);
> +
> +       return 0;
> +}

See below.

>
> +static int
> +cn9k_nix_rx_metadata_negotiate(struct rte_eth_dev *eth_dev, uint64_t *features)
> +{
> +       struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
> +
> +       *features &=
> +               (RTE_ETH_RX_METADATA_USER_FLAG | RTE_ETH_RX_METADATA_USER_MARK);
> +
> +       if (*features) {
> +               dev->rx_offload_flags |= NIX_RX_OFFLOAD_MARK_UPDATE_F;
> +               dev->rx_mark_update = true;
> +       } else {
> +               dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_MARK_UPDATE_F;
> +               dev->rx_mark_update = false;
> +       }
> +
> +       cn9k_eth_set_rx_function(eth_dev);
> +
> +       return 0;
> +}
> +

The above two functions are duplicates, Please pass the function
pointer and make it as one function
for common code.

Re: [PATCH 10/20] net/cnxk: added Rx metadata negotiate operation

[Nithin Kumar Dabilpuram]

Please see inline.

Thanks
Nithin

On 2/17/22 7:03 PM, Jerin Jacob wrote:
> On Mon, Feb 7, 2022 at 1:01 PM Nithin Dabilpuram
> <ndabilpuram@marvell.com> wrote:
>>
>> From: Satha Rao <skoteshwar@marvell.com>
>>
>> Added rx_metadata_negotiate api to enable mark update RX offload.
>> Removed software logic to enable/disable mark update inside flow
>> create/destroy apis.
> 
> APIs

Ack.
> 
>> Signed-off-by: Satha Rao <skoteshwar@marvell.com>
>> ---
> 
>> +static int
>> +cn10k_nix_rx_metadata_negotiate(struct rte_eth_dev *eth_dev, uint64_t *features)
>> +{
>> +       struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
>> +
>> +       *features &=
>> +               (RTE_ETH_RX_METADATA_USER_FLAG | RTE_ETH_RX_METADATA_USER_MARK);
>> +
>> +       if (*features) {
>> +               dev->rx_offload_flags |= NIX_RX_OFFLOAD_MARK_UPDATE_F;
>> +               dev->rx_mark_update = true;
>> +       } else {
>> +               dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_MARK_UPDATE_F;
>> +               dev->rx_mark_update = false;
>> +       }
>> +
>> +       cn10k_eth_set_rx_function(eth_dev);
>> +
>> +       return 0;
>> +}
> 
> See below.
> 
>>
>> +static int
>> +cn9k_nix_rx_metadata_negotiate(struct rte_eth_dev *eth_dev, uint64_t *features)
>> +{
>> +       struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
>> +
>> +       *features &=
>> +               (RTE_ETH_RX_METADATA_USER_FLAG | RTE_ETH_RX_METADATA_USER_MARK);
>> +
>> +       if (*features) {
>> +               dev->rx_offload_flags |= NIX_RX_OFFLOAD_MARK_UPDATE_F;
>> +               dev->rx_mark_update = true;
>> +       } else {
>> +               dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_MARK_UPDATE_F;
>> +               dev->rx_mark_update = false;
>> +       }
>> +
>> +       cn9k_eth_set_rx_function(eth_dev);
>> +
>> +       return 0;
>> +}
>> +
> 
> The above two functions are duplicates, Please pass the function
> pointer and make it as one function
> for common code.

Though the two functions are same, the fast path offload flags used 
within them are defined per platform so that in future CN9K and CN10K
can have different set of fast path offloads though the two hash defines
are same now. They are also in mutually exclusive files.

[PATCH 11/20] common/cnxk: removed tracking of mark actions

[Nithin Dabilpuram]

From: Satha Rao <skoteshwar@marvell.com>

Removed roc npc apis which tracks addition and deletion of
mark actions.

Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---
 drivers/common/cnxk/roc_npc.c      | 21 ---------------------
 drivers/common/cnxk/roc_npc.h      |  3 ---
 drivers/common/cnxk/roc_npc_priv.h |  1 -
 drivers/common/cnxk/version.map    |  2 --
 4 files changed, 27 deletions(-)

diff --git a/drivers/common/cnxk/roc_npc.c b/drivers/common/cnxk/roc_npc.c
index e3961bf..d2ebe61 100644
--- a/drivers/common/cnxk/roc_npc.c
+++ b/drivers/common/cnxk/roc_npc.c
@@ -166,8 +166,6 @@ roc_npc_init(struct roc_npc *roc_npc)
 	roc_npc->kex_capability = npc_get_kex_capability(npc);
 	roc_npc->rx_parse_nibble = npc->keyx_supp_nmask[NPC_MCAM_RX];
 
-	npc->mark_actions = 0;
-
 	npc->mcam_entries = npc_mcam_tot_entries() >> npc->keyw[NPC_MCAM_RX];
 
 	/* Free, free_rev, live and live_rev entries */
@@ -323,13 +321,11 @@ npc_parse_actions(struct roc_npc *roc_npc, const struct roc_npc_attr *attr,
 			}
 			mark = act_mark->id + 1;
 			req_act |= ROC_NPC_ACTION_TYPE_MARK;
-			npc->mark_actions += 1;
 			break;
 
 		case ROC_NPC_ACTION_TYPE_FLAG:
 			mark = NPC_FLOW_FLAG_VAL;
 			req_act |= ROC_NPC_ACTION_TYPE_FLAG;
-			npc->mark_actions += 1;
 			break;
 
 		case ROC_NPC_ACTION_TYPE_COUNT:
@@ -812,23 +808,6 @@ npc_rss_action_program(struct roc_npc *roc_npc,
 	return 0;
 }
 
-int
-roc_npc_mark_actions_get(struct roc_npc *roc_npc)
-{
-	struct npc *npc = roc_npc_to_npc_priv(roc_npc);
-
-	return npc->mark_actions;
-}
-
-int
-roc_npc_mark_actions_sub_return(struct roc_npc *roc_npc, uint32_t count)
-{
-	struct npc *npc = roc_npc_to_npc_priv(roc_npc);
-
-	npc->mark_actions -= count;
-	return npc->mark_actions;
-}
-
 static int
 npc_vtag_cfg_delete(struct roc_npc *roc_npc, struct roc_npc_flow *flow)
 {
diff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h
index b836e26..6dcdd29 100644
--- a/drivers/common/cnxk/roc_npc.h
+++ b/drivers/common/cnxk/roc_npc.h
@@ -337,9 +337,6 @@ int __roc_api roc_npc_mcam_free_all_resources(struct roc_npc *roc_npc);
 void __roc_api roc_npc_flow_dump(FILE *file, struct roc_npc *roc_npc);
 void __roc_api roc_npc_flow_mcam_dump(FILE *file, struct roc_npc *roc_npc,
 				      struct roc_npc_flow *mcam);
-int __roc_api roc_npc_mark_actions_get(struct roc_npc *roc_npc);
-int __roc_api roc_npc_mark_actions_sub_return(struct roc_npc *roc_npc,
-					      uint32_t count);
 int __roc_api roc_npc_vtag_actions_get(struct roc_npc *roc_npc);
 int __roc_api roc_npc_vtag_actions_sub_return(struct roc_npc *roc_npc,
 					      uint32_t count);
diff --git a/drivers/common/cnxk/roc_npc_priv.h b/drivers/common/cnxk/roc_npc_priv.h
index afd11ad..a04f621 100644
--- a/drivers/common/cnxk/roc_npc_priv.h
+++ b/drivers/common/cnxk/roc_npc_priv.h
@@ -380,7 +380,6 @@ struct npc {
 	uint16_t flow_prealloc_size;		/* Pre allocated mcam size */
 	uint16_t flow_max_priority;		/* Max priority for flow */
 	uint16_t switch_header_type; /* Supported switch header type */
-	uint32_t mark_actions;	     /* Number of mark actions */
 	uint32_t vtag_strip_actions; /* vtag insert/strip actions */
 	uint16_t pf_func;	     /* pf_func of device */
 	npc_dxcfg_t prx_dxcfg;	     /* intf, lid, lt, extract */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 7a8aff1..0f990d3 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -305,8 +305,6 @@ INTERNAL {
 	roc_npc_flow_parse;
 	roc_npc_get_low_priority_mcam;
 	roc_npc_init;
-	roc_npc_mark_actions_get;
-	roc_npc_mark_actions_sub_return;
 	roc_npc_vtag_actions_get;
 	roc_npc_vtag_actions_sub_return;
 	roc_npc_mcam_alloc_entries;
-- 
2.8.4

Re: [PATCH 11/20] common/cnxk: removed tracking of mark actions

[Jerin Jacob]

On Mon, Feb 7, 2022 at 1:01 PM Nithin Dabilpuram
<ndabilpuram@marvell.com> wrote:
>
> From: Satha Rao <skoteshwar@marvell.com>

Subject change removed to remove

>
> Removed roc npc apis which tracks addition and deletion of

NPC and APIs

> mark actions.

Tell why it is removed.


>
> Signed-off-by: Satha Rao <skoteshwar@marvell.com>
> ---
>  drivers/common/cnxk/roc_npc.c      | 21 ---------------------
>  drivers/common/cnxk/roc_npc.h      |  3 ---
>  drivers/common/cnxk/roc_npc_priv.h |  1 -
>  drivers/common/cnxk/version.map    |  2 --
>  4 files changed, 27 deletions(-)
>
> diff --git a/drivers/common/cnxk/roc_npc.c b/drivers/common/cnxk/roc_npc.c
> index e3961bf..d2ebe61 100644
> --- a/drivers/common/cnxk/roc_npc.c
> +++ b/drivers/common/cnxk/roc_npc.c
> @@ -166,8 +166,6 @@ roc_npc_init(struct roc_npc *roc_npc)
>         roc_npc->kex_capability = npc_get_kex_capability(npc);
>         roc_npc->rx_parse_nibble = npc->keyx_supp_nmask[NPC_MCAM_RX];
>
> -       npc->mark_actions = 0;
> -
>         npc->mcam_entries = npc_mcam_tot_entries() >> npc->keyw[NPC_MCAM_RX];
>
>         /* Free, free_rev, live and live_rev entries */
> @@ -323,13 +321,11 @@ npc_parse_actions(struct roc_npc *roc_npc, const struct roc_npc_attr *attr,
>                         }
>                         mark = act_mark->id + 1;
>                         req_act |= ROC_NPC_ACTION_TYPE_MARK;
> -                       npc->mark_actions += 1;
>                         break;
>
>                 case ROC_NPC_ACTION_TYPE_FLAG:
>                         mark = NPC_FLOW_FLAG_VAL;
>                         req_act |= ROC_NPC_ACTION_TYPE_FLAG;
> -                       npc->mark_actions += 1;
>                         break;
>
>                 case ROC_NPC_ACTION_TYPE_COUNT:
> @@ -812,23 +808,6 @@ npc_rss_action_program(struct roc_npc *roc_npc,
>         return 0;
>  }
>
> -int
> -roc_npc_mark_actions_get(struct roc_npc *roc_npc)
> -{
> -       struct npc *npc = roc_npc_to_npc_priv(roc_npc);
> -
> -       return npc->mark_actions;
> -}
> -
> -int
> -roc_npc_mark_actions_sub_return(struct roc_npc *roc_npc, uint32_t count)
> -{
> -       struct npc *npc = roc_npc_to_npc_priv(roc_npc);
> -
> -       npc->mark_actions -= count;
> -       return npc->mark_actions;
> -}
> -
>  static int
>  npc_vtag_cfg_delete(struct roc_npc *roc_npc, struct roc_npc_flow *flow)
>  {
> diff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h
> index b836e26..6dcdd29 100644
> --- a/drivers/common/cnxk/roc_npc.h
> +++ b/drivers/common/cnxk/roc_npc.h
> @@ -337,9 +337,6 @@ int __roc_api roc_npc_mcam_free_all_resources(struct roc_npc *roc_npc);
>  void __roc_api roc_npc_flow_dump(FILE *file, struct roc_npc *roc_npc);
>  void __roc_api roc_npc_flow_mcam_dump(FILE *file, struct roc_npc *roc_npc,
>                                       struct roc_npc_flow *mcam);
> -int __roc_api roc_npc_mark_actions_get(struct roc_npc *roc_npc);
> -int __roc_api roc_npc_mark_actions_sub_return(struct roc_npc *roc_npc,
> -                                             uint32_t count);
>  int __roc_api roc_npc_vtag_actions_get(struct roc_npc *roc_npc);
>  int __roc_api roc_npc_vtag_actions_sub_return(struct roc_npc *roc_npc,
>                                               uint32_t count);
> diff --git a/drivers/common/cnxk/roc_npc_priv.h b/drivers/common/cnxk/roc_npc_priv.h
> index afd11ad..a04f621 100644
> --- a/drivers/common/cnxk/roc_npc_priv.h
> +++ b/drivers/common/cnxk/roc_npc_priv.h
> @@ -380,7 +380,6 @@ struct npc {
>         uint16_t flow_prealloc_size;            /* Pre allocated mcam size */
>         uint16_t flow_max_priority;             /* Max priority for flow */
>         uint16_t switch_header_type; /* Supported switch header type */
> -       uint32_t mark_actions;       /* Number of mark actions */
>         uint32_t vtag_strip_actions; /* vtag insert/strip actions */
>         uint16_t pf_func;            /* pf_func of device */
>         npc_dxcfg_t prx_dxcfg;       /* intf, lid, lt, extract */
> diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
> index 7a8aff1..0f990d3 100644
> --- a/drivers/common/cnxk/version.map
> +++ b/drivers/common/cnxk/version.map
> @@ -305,8 +305,6 @@ INTERNAL {
>         roc_npc_flow_parse;
>         roc_npc_get_low_priority_mcam;
>         roc_npc_init;
> -       roc_npc_mark_actions_get;
> -       roc_npc_mark_actions_sub_return;
>         roc_npc_vtag_actions_get;
>         roc_npc_vtag_actions_sub_return;
>         roc_npc_mcam_alloc_entries;
> --
> 2.8.4
>

[PATCH 12/20] net/cnxk: fix inline device RQ tag mask

[Nithin Dabilpuram]

Fix inline device rq tagmask to get packets with receive errors
as type ETHDEV packets to callback handler so that packet buffers
can get freed. Currently only ipsec denied packets get the right
tag mask.

Fixes: ee48f711f3b0 ("common/cnxk: support NIX inline inbound and outbound setup")
Cc: stable@dpdk.org

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/common/cnxk/roc_nix_inl.c | 2 +-
 drivers/net/cnxk/cnxk_ethdev.c    | 9 +++++++++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index 003f972..11a1691 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -584,7 +584,7 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq)
 
 	inl_rq->flow_tag_width = 20;
 	/* Special tag mask */
-	inl_rq->tag_mask = 0xFFF00000;
+	inl_rq->tag_mask = rq->tag_mask;
 	inl_rq->tt = SSO_TT_ORDERED;
 	inl_rq->hwgrp = 0;
 	inl_rq->wqe_skip = inl_dev->wqe_skip;
diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index 53dfb5e..9ede66e 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -3,6 +3,8 @@
  */
 #include <cnxk_ethdev.h>
 
+#include <rte_eventdev.h>
+
 static inline uint64_t
 nix_get_rx_offload_capa(struct cnxk_eth_dev *dev)
 {
@@ -597,6 +599,13 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 	rxq_sp->qconf.mp = mp;
 
 	if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
+		/* Pass a tagmask used to handle error packets in inline device.
+		 * Ethdev rq's tag_mask field will be overwritten later
+		 * when sso is setup.
+		 */
+		rq->tag_mask =
+			0x0FF00000 | ((uint32_t)RTE_EVENT_TYPE_ETHDEV << 28);
+
 		/* Setup rq reference for inline dev if present */
 		rc = roc_nix_inl_dev_rq_get(rq);
 		if (rc)
-- 
2.8.4

[PATCH 13/20] net/cnxk: register callback early to handle initial packets

[Nithin Dabilpuram]

Register callback early to handle initial error packets from
inline device.

Fixes: 69daa9e5022b ("net/cnxk: support inline security setup for cn10k")
Cc: stable@dpdk.org

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/net/cnxk/cn10k_ethdev.c     | 6 ++++++
 drivers/net/cnxk/cn10k_ethdev.h     | 3 +++
 drivers/net/cnxk/cn10k_ethdev_sec.c | 5 +----
 3 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c
index 169e70e..af4fa75 100644
--- a/drivers/net/cnxk/cn10k_ethdev.c
+++ b/drivers/net/cnxk/cn10k_ethdev.c
@@ -316,6 +316,12 @@ cn10k_nix_configure(struct rte_eth_dev *eth_dev)
 	if (rc)
 		return rc;
 
+	if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY ||
+	    dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
+		/* Register callback to handle security error work */
+		roc_nix_inl_cb_register(cn10k_eth_sec_sso_work_cb, NULL);
+	}
+
 	/* Update offload flags */
 	dev->rx_offload_flags = nix_rx_offload_flags(eth_dev);
 	dev->tx_offload_flags = nix_tx_offload_flags(eth_dev);
diff --git a/drivers/net/cnxk/cn10k_ethdev.h b/drivers/net/cnxk/cn10k_ethdev.h
index 0982158..13403e1 100644
--- a/drivers/net/cnxk/cn10k_ethdev.h
+++ b/drivers/net/cnxk/cn10k_ethdev.h
@@ -82,6 +82,9 @@ void cn10k_eth_set_tx_function(struct rte_eth_dev *eth_dev);
 /* Security context setup */
 void cn10k_eth_sec_ops_override(void);
 
+/* SSO Work callback */
+void cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args);
+
 #define LMT_OFF(lmt_addr, lmt_num, offset)                                     \
 	(void *)((uintptr_t)(lmt_addr) +                                       \
 		 ((uint64_t)(lmt_num) << ROC_LMT_LINE_SIZE_LOG2) + (offset))
diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c
index 6fbf444..ac45056 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -138,7 +138,7 @@ static const struct rte_security_capability cn10k_eth_sec_capabilities[] = {
 	}
 };
 
-static void
+void
 cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args)
 {
 	struct rte_eth_event_ipsec_desc desc;
@@ -251,9 +251,6 @@ cn10k_eth_sec_session_create(void *device,
 	if (rte_security_dynfield_register() < 0)
 		return -ENOTSUP;
 
-	if (rte_eal_process_type() == RTE_PROC_PRIMARY)
-		roc_nix_inl_cb_register(cn10k_eth_sec_sso_work_cb, NULL);
-
 	ipsec = &conf->ipsec;
 	crypto = conf->crypto_xform;
 	inbound = !!(ipsec->direction == RTE_SECURITY_IPSEC_SA_DIR_INGRESS);
-- 
2.8.4

[PATCH 14/20] net/cnxk: realloc inline dev XAQ for security

[Nithin Dabilpuram]

Realloc inline dev XAQ when Rx/Tx security ie enabled with
new packet pool as XAQ should be large enough to hold all
mbufs if inline outbound reports error or all mbufs.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/net/cnxk/cnxk_ethdev.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index 9ede66e..9a1f97b 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -545,6 +545,11 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 		nb_desc = RTE_MAX(nb_desc, pkt_pool_limit);
 	}
 
+	/* Its a no-op when inline device is not used */
+	if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY ||
+	    dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY)
+		roc_nix_inl_dev_xaq_realloc(mp->pool_id);
+
 	/* Setup ROC CQ */
 	cq = &dev->cqs[qid];
 	cq->qid = qid;
-- 
2.8.4

[PATCH 15/20] net/cnxk: use raw mbuf free on inline sec err

[Nithin Dabilpuram]

Use raw mbuf free on inline sec error to simulate
HW NPA free instead of doing rte_pktmbuf_free(). This
is needed as the callback will not be called from
DPDK lcore.

Fixes: 69daa9e5022b ("net/cnxk: support inline security setup for cn10k")
Cc: stable@dpdk.org

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/net/cnxk/cn10k_ethdev_sec.c | 37 ++++++++++++++++++++++++++++++++-----
 1 file changed, 32 insertions(+), 5 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c
index ac45056..044b20c 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -138,6 +138,20 @@ static const struct rte_security_capability cn10k_eth_sec_capabilities[] = {
 	}
 };
 
+static inline void
+cnxk_pktmbuf_free_no_cache(struct rte_mbuf *mbuf)
+{
+	struct rte_mbuf *next;
+
+	if (!mbuf)
+		return;
+	do {
+		next = mbuf->next;
+		roc_npa_aura_op_free(mbuf->pool->pool_id, 1, (rte_iova_t)mbuf);
+		mbuf = next;
+	} while (mbuf != NULL);
+}
+
 void
 cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args)
 {
@@ -148,6 +162,7 @@ cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args)
 	struct cpt_cn10k_res_s *res;
 	struct rte_eth_dev *eth_dev;
 	struct cnxk_eth_dev *dev;
+	static uint64_t warn_cnt;
 	uint16_t dlen_adj, rlen;
 	struct rte_mbuf *mbuf;
 	uintptr_t sa_base;
@@ -161,7 +176,7 @@ cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args)
 		/* Event from inbound inline dev due to IPSEC packet bad L4 */
 		mbuf = (struct rte_mbuf *)(gw[1] - sizeof(struct rte_mbuf));
 		plt_nix_dbg("Received mbuf %p from inline dev inbound", mbuf);
-		rte_pktmbuf_free(mbuf);
+		cnxk_pktmbuf_free_no_cache(mbuf);
 		return;
 	case RTE_EVENT_TYPE_CPU:
 		/* Check for subtype */
@@ -212,17 +227,29 @@ cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args)
 	case ROC_IE_OT_UCC_ERR_SA_OVERFLOW:
 		desc.subtype = RTE_ETH_EVENT_IPSEC_ESN_OVERFLOW;
 		break;
+	case ROC_IE_OT_UCC_ERR_PKT_IP:
+		warn_cnt++;
+		if (warn_cnt % 10000 == 0)
+			plt_warn("Outbound error, bad ip pkt, mbuf %p,"
+				 " sa_index %u (total warnings %" PRIu64 ")",
+				 mbuf, sess_priv.sa_idx, warn_cnt);
+		desc.subtype = RTE_ETH_EVENT_IPSEC_UNKNOWN;
+		break;
 	default:
-		plt_warn("Outbound error, mbuf %p, sa_index %u, "
-			 "compcode %x uc %x", mbuf, sess_priv.sa_idx,
-			 res->compcode, res->uc_compcode);
+		warn_cnt++;
+		if (warn_cnt % 10000 == 0)
+			plt_warn("Outbound error, mbuf %p, sa_index %u,"
+				 " compcode %x uc %x,"
+				 " (total warnings %" PRIu64 ")",
+				 mbuf, sess_priv.sa_idx, res->compcode,
+				 res->uc_compcode, warn_cnt);
 		desc.subtype = RTE_ETH_EVENT_IPSEC_UNKNOWN;
 		break;
 	}
 
 	desc.metadata = (uint64_t)priv->userdata;
 	rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_IPSEC, &desc);
-	rte_pktmbuf_free(mbuf);
+	cnxk_pktmbuf_free_no_cache(mbuf);
 }
 
 static int
-- 
2.8.4

Re: [PATCH 15/20] net/cnxk: use raw mbuf free on inline sec err

[Jerin Jacob]

On Mon, Feb 7, 2022 at 1:01 PM Nithin Dabilpuram
<ndabilpuram@marvell.com> wrote:

You could change the subject as net/cnxk: fix inline IPsec security
error handling

>
> Use raw mbuf free on inline sec error to simulate

sec- > security

> HW NPA free instead of doing rte_pktmbuf_free(). This
> is needed as the callback will not be called from
> DPDK lcore.
>
> Fixes: 69daa9e5022b ("net/cnxk: support inline security setup for cn10k")
> Cc: stable@dpdk.org
>
> Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
> ---
>  drivers/net/cnxk/cn10k_ethdev_sec.c | 37 ++++++++++++++++++++++++++++++++-----
>  1 file changed, 32 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c
> index ac45056..044b20c 100644
> --- a/drivers/net/cnxk/cn10k_ethdev_sec.c
> +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
> @@ -138,6 +138,20 @@ static const struct rte_security_capability cn10k_eth_sec_capabilities[] = {
>         }
>  };
>
> +static inline void
> +cnxk_pktmbuf_free_no_cache(struct rte_mbuf *mbuf)
> +{
> +       struct rte_mbuf *next;
> +
> +       if (!mbuf)
> +               return;
> +       do {
> +               next = mbuf->next;
> +               roc_npa_aura_op_free(mbuf->pool->pool_id, 1, (rte_iova_t)mbuf);
> +               mbuf = next;
> +       } while (mbuf != NULL);
> +}
> +
>  void
>  cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args)
>  {
> @@ -148,6 +162,7 @@ cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args)
>         struct cpt_cn10k_res_s *res;
>         struct rte_eth_dev *eth_dev;
>         struct cnxk_eth_dev *dev;
> +       static uint64_t warn_cnt;
>         uint16_t dlen_adj, rlen;
>         struct rte_mbuf *mbuf;
>         uintptr_t sa_base;
> @@ -161,7 +176,7 @@ cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args)
>                 /* Event from inbound inline dev due to IPSEC packet bad L4 */
>                 mbuf = (struct rte_mbuf *)(gw[1] - sizeof(struct rte_mbuf));
>                 plt_nix_dbg("Received mbuf %p from inline dev inbound", mbuf);
> -               rte_pktmbuf_free(mbuf);
> +               cnxk_pktmbuf_free_no_cache(mbuf);
>                 return;
>         case RTE_EVENT_TYPE_CPU:
>                 /* Check for subtype */
> @@ -212,17 +227,29 @@ cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args)
>         case ROC_IE_OT_UCC_ERR_SA_OVERFLOW:
>                 desc.subtype = RTE_ETH_EVENT_IPSEC_ESN_OVERFLOW;
>                 break;
> +       case ROC_IE_OT_UCC_ERR_PKT_IP:
> +               warn_cnt++;
> +               if (warn_cnt % 10000 == 0)
> +                       plt_warn("Outbound error, bad ip pkt, mbuf %p,"
> +                                " sa_index %u (total warnings %" PRIu64 ")",
> +                                mbuf, sess_priv.sa_idx, warn_cnt);
> +               desc.subtype = RTE_ETH_EVENT_IPSEC_UNKNOWN;
> +               break;
>         default:
> -               plt_warn("Outbound error, mbuf %p, sa_index %u, "
> -                        "compcode %x uc %x", mbuf, sess_priv.sa_idx,
> -                        res->compcode, res->uc_compcode);
> +               warn_cnt++;
> +               if (warn_cnt % 10000 == 0)
> +                       plt_warn("Outbound error, mbuf %p, sa_index %u,"
> +                                " compcode %x uc %x,"
> +                                " (total warnings %" PRIu64 ")",
> +                                mbuf, sess_priv.sa_idx, res->compcode,
> +                                res->uc_compcode, warn_cnt);
>                 desc.subtype = RTE_ETH_EVENT_IPSEC_UNKNOWN;
>                 break;
>         }
>
>         desc.metadata = (uint64_t)priv->userdata;
>         rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_IPSEC, &desc);
> -       rte_pktmbuf_free(mbuf);
> +       cnxk_pktmbuf_free_no_cache(mbuf);
>  }
>
>  static int
> --
> 2.8.4
>

[PATCH 16/20] net/cnxk: use NPA batch burst free for meta buffers

[Nithin Dabilpuram]

Currently meta buffers are freed in bursts of one LMT line
i.e 15 pointers. Instead free them in bursts of 16 LMTlines
which is 240 ptrs for better perf.

Also mark mempool objects as get and put in missing places.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/event/cnxk/cn10k_worker.h |  13 ++++-
 drivers/net/cnxk/cn10k_rx.h       | 114 +++++++++++++++++++++++++++++++-------
 2 files changed, 107 insertions(+), 20 deletions(-)

diff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h
index 78d029b..42be92d 100644
--- a/drivers/event/cnxk/cn10k_worker.h
+++ b/drivers/event/cnxk/cn10k_worker.h
@@ -93,12 +93,16 @@ cn10k_sso_hws_forward_event(struct cn10k_sso_hws *ws,
 }
 
 static __rte_always_inline void
-cn10k_wqe_to_mbuf(uint64_t wqe, const uint64_t mbuf, uint8_t port_id,
+cn10k_wqe_to_mbuf(uint64_t wqe, const uint64_t __mbuf, uint8_t port_id,
 		  const uint32_t tag, const uint32_t flags,
 		  const void *const lookup_mem)
 {
 	const uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM |
 				   (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);
+	struct rte_mbuf *mbuf = (struct rte_mbuf *)__mbuf;
+
+	/* Mark mempool obj as "get" as it is alloc'ed by NIX */
+	RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
 
 	cn10k_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag,
 			      (struct rte_mbuf *)mbuf, lookup_mem,
@@ -154,6 +158,9 @@ cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags,
 		mbuf = (struct rte_mbuf *)((char *)cqe -
 					   sizeof(struct rte_mbuf));
 
+		/* Mark mempool obj as "get" as it is alloc'ed by NIX */
+		RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
+
 		/* Translate meta to mbuf */
 		if (flags & NIX_RX_OFFLOAD_SECURITY_F) {
 			const uint64_t cq_w1 = *((const uint64_t *)cqe + 1);
@@ -275,6 +282,10 @@ cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev,
 			*(uint64_t *)gw.u64[1] = (uint64_t)vwqe_hdr;
 			cn10k_process_vwqe(gw.u64[1], port, flags, lookup_mem,
 					   ws->tstamp, ws->lmt_base);
+			/* Mark vector mempool object as get */
+			RTE_MEMPOOL_CHECK_COOKIES(
+				rte_mempool_from_obj((void *)gw.u64[1]),
+				(void **)&gw.u64[1], 1, 1);
 		}
 	}
 
diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h
index a2442d3..a8a4e65 100644
--- a/drivers/net/cnxk/cn10k_rx.h
+++ b/drivers/net/cnxk/cn10k_rx.h
@@ -67,6 +67,24 @@ nix_get_mbuf_from_cqe(void *cq, const uint64_t data_off)
 }
 
 static __rte_always_inline void
+nix_sec_flush_meta_burst(uint16_t lmt_id, uint64_t data, uint16_t lnum,
+			 uintptr_t aura_handle)
+{
+	uint64_t pa;
+
+	/* Prepare PA and Data */
+	pa = roc_npa_aura_handle_to_base(aura_handle) + NPA_LF_AURA_BATCH_FREE0;
+	pa |= ((data & 0x7) << 4);
+
+	data >>= 3;
+	data <<= 19;
+	data |= (uint64_t)lmt_id;
+	data |= (uint64_t)(lnum - 1) << 12;
+
+	roc_lmt_submit_steorl(data, pa);
+}
+
+static __rte_always_inline void
 nix_sec_flush_meta(uintptr_t laddr, uint16_t lmt_id, uint8_t loff,
 		   uintptr_t aura_handle)
 {
@@ -82,7 +100,7 @@ nix_sec_flush_meta(uintptr_t laddr, uint16_t lmt_id, uint8_t loff,
 	*(uint64_t *)laddr = (((uint64_t)(loff & 0x1) << 32) |
 			      roc_npa_aura_handle_to_aura(aura_handle));
 
-	pa |= ((loff >> 1) << 4);
+	pa |= ((uint64_t)(loff >> 1) << 4);
 	roc_lmt_submit_steorl(lmt_id, pa);
 }
 
@@ -122,6 +140,12 @@ nix_sec_meta_to_mbuf_sc(uint64_t cq_w1, const uint64_t sa_base, uintptr_t laddr,
 		*(uint64_t *)(laddr + (*loff << 3)) = (uint64_t)mbuf;
 		*loff = *loff + 1;
 
+		/* Mark meta mbuf as put */
+		RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 0);
+
+		/* Mark inner mbuf as get */
+		RTE_MEMPOOL_CHECK_COOKIES(inner->pool, (void **)&inner, 1, 1);
+
 		return inner;
 	}
 	return mbuf;
@@ -181,6 +205,12 @@ nix_sec_meta_to_mbuf(uint64_t cq_w1, uintptr_t sa_base, uintptr_t laddr,
 		*(uint64_t *)(laddr + (*loff << 3)) = (uint64_t)mbuf;
 		*loff = *loff + 1;
 
+		/* Mark meta mbuf as put */
+		RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 0);
+
+		/* Mark inner mbuf as get */
+		RTE_MEMPOOL_CHECK_COOKIES(inner->pool, (void **)&inner, 1, 1);
+
 		/* Return inner mbuf */
 		return inner;
 	}
@@ -306,9 +336,6 @@ cn10k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag,
 	uint16_t len = rx->pkt_lenm1 + 1;
 	uint64_t ol_flags = 0;
 
-	/* Mark mempool obj as "get" as it is alloc'ed by NIX */
-	RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
-
 	if (flag & NIX_RX_OFFLOAD_PTYPE_F)
 		mbuf->packet_type = nix_ptype_get(lookup_mem, w1);
 	else
@@ -440,6 +467,9 @@ cn10k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts,
 
 		mbuf = nix_get_mbuf_from_cqe(cq, data_off);
 
+		/* Mark mempool obj as "get" as it is alloc'ed by NIX */
+		RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
+
 		/* Translate meta to mbuf */
 		if (flags & NIX_RX_OFFLOAD_SECURITY_F) {
 			const uint64_t cq_w1 = *((const uint64_t *)cq + 1);
@@ -538,7 +568,7 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,
 	uint64x2_t rearm3 = vdupq_n_u64(mbuf_initializer);
 	struct rte_mbuf *mbuf0, *mbuf1, *mbuf2, *mbuf3;
 	uint64_t aura_handle, lbase, laddr;
-	uint8_t loff = 0, lnum = 0;
+	uint8_t loff = 0, lnum = 0, shft = 0;
 	uint8x16_t f0, f1, f2, f3;
 	uint16_t lmt_id, d_off;
 	uint16_t packets = 0;
@@ -709,6 +739,12 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,
 			ol_flags3 |= nix_rx_olflags_get(lookup_mem, cq3_w1);
 		}
 
+		/* Mark mempool obj as "get" as it is alloc'ed by NIX */
+		RTE_MEMPOOL_CHECK_COOKIES(mbuf0->pool, (void **)&mbuf0, 1, 1);
+		RTE_MEMPOOL_CHECK_COOKIES(mbuf1->pool, (void **)&mbuf1, 1, 1);
+		RTE_MEMPOOL_CHECK_COOKIES(mbuf2->pool, (void **)&mbuf2, 1, 1);
+		RTE_MEMPOOL_CHECK_COOKIES(mbuf3->pool, (void **)&mbuf3, 1, 1);
+
 		/* Translate meta to mbuf */
 		if (flags & NIX_RX_OFFLOAD_SECURITY_F) {
 			/* Checksum ol_flags will be cleared if mbuf is meta */
@@ -905,12 +941,6 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,
 		roc_prefetch_store_keep(mbuf2);
 		roc_prefetch_store_keep(mbuf3);
 
-		/* Mark mempool obj as "get" as it is alloc'ed by NIX */
-		RTE_MEMPOOL_CHECK_COOKIES(mbuf0->pool, (void **)&mbuf0, 1, 1);
-		RTE_MEMPOOL_CHECK_COOKIES(mbuf1->pool, (void **)&mbuf1, 1, 1);
-		RTE_MEMPOOL_CHECK_COOKIES(mbuf2->pool, (void **)&mbuf2, 1, 1);
-		RTE_MEMPOOL_CHECK_COOKIES(mbuf3->pool, (void **)&mbuf3, 1, 1);
-
 		packets += NIX_DESCS_PER_LOOP;
 
 		if (!(flags & NIX_RX_VWQE_F)) {
@@ -920,22 +950,68 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,
 		}
 
 		if (flags & NIX_RX_OFFLOAD_SECURITY_F) {
-			/* Flush when we don't have space for 4 meta */
-			if ((15 - loff) < 4) {
-				nix_sec_flush_meta(laddr, lmt_id + lnum, loff,
-						   aura_handle);
+			/* Check if lmtline border is crossed and adjust lnum */
+			if (loff > 15) {
+				/* Update aura handle */
+				*(uint64_t *)(laddr - 8) =
+					(((uint64_t)(15 & 0x1) << 32) |
+					 roc_npa_aura_handle_to_aura(
+						 aura_handle));
+				loff = loff - 15;
+				shft += 3;
+
 				lnum++;
-				lnum &= BIT_ULL(ROC_LMT_LINES_PER_CORE_LOG2) -
-					1;
-				/* First pointer starts at 8B offset */
 				laddr = (uintptr_t)LMT_OFF(lbase, lnum, 8);
+				/* Pick the pointer from 16th index and put it
+				 * at end of this new line.
+				 */
+				*(uint64_t *)(laddr + (loff << 3) - 8) =
+					*(uint64_t *)(laddr - 8);
+			}
+
+			/* Flush it when we are in 16th line and might
+			 * overflow it
+			 */
+			if (lnum >= 15 && loff >= 12) {
+				/* 16 LMT Line size m1 */
+				uint64_t data = BIT_ULL(48) - 1;
+
+				/* Update aura handle */
+				*(uint64_t *)(laddr - 8) =
+					(((uint64_t)(loff & 0x1) << 32) |
+					 roc_npa_aura_handle_to_aura(
+						 aura_handle));
+
+				data = (data & ~(0x7UL << shft)) |
+				       (((uint64_t)loff >> 1) << shft);
+
+				/* Send up to 16 lmt lines of pointers */
+				nix_sec_flush_meta_burst(lmt_id, data, lnum + 1,
+							 aura_handle);
+				rte_io_wmb();
+				lnum = 0;
 				loff = 0;
+				shft = 0;
+				/* First pointer starts at 8B offset */
+				laddr = (uintptr_t)LMT_OFF(lbase, lnum, 8);
 			}
 		}
 	}
 
 	if (flags & NIX_RX_OFFLOAD_SECURITY_F && loff) {
-		nix_sec_flush_meta(laddr, lmt_id + lnum, loff, aura_handle);
+		/* 16 LMT Line size m1 */
+		uint64_t data = BIT_ULL(48) - 1;
+
+		/* Update aura handle */
+		*(uint64_t *)(laddr - 8) =
+			(((uint64_t)(loff & 0x1) << 32) |
+			 roc_npa_aura_handle_to_aura(aura_handle));
+
+		data = (data & ~(0x7UL << shft)) |
+		       (((uint64_t)loff >> 1) << shft);
+
+		/* Send up to 16 lmt lines of pointers */
+		nix_sec_flush_meta_burst(lmt_id, data, lnum + 1, aura_handle);
 		if (flags & NIX_RX_VWQE_F)
 			plt_io_wmb();
 	}
-- 
2.8.4

[PATCH 17/20] net/cnxk: enable packet pool tail drop

[Nithin Dabilpuram]

Enable packet pool tail drop on RQ when inbound security is not
enabled. This is only part of the config. It is a NOP if
tail drop is not enabled on NPA_AURA_CTX_S. And tail drop
on packet pool AURA is enabled only when that packet pool aura
is used by inline device RQ.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/net/cnxk/cnxk_ethdev.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index 9a1f97b..aa76d87 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -574,6 +574,7 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 	rq->first_skip = first_skip;
 	rq->later_skip = sizeof(struct rte_mbuf);
 	rq->lpb_size = mp->elt_size;
+	rq->lpb_drop_ena = !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY);
 
 	/* Enable Inline IPSec on RQ, will not be used for Poll mode */
 	if (roc_nix_inl_inb_is_enabled(nix))
-- 
2.8.4

[PATCH 18/20] net/cnxk: enable flow control by default on device configure

[Nithin Dabilpuram]

Enable flow control by default on device configuration
instead of basing it on Kernel behaviour.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/net/cnxk/cnxk_ethdev.c | 24 +++++++-----------------
 1 file changed, 7 insertions(+), 17 deletions(-)

diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index aa76d87..e4fbb09 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -306,25 +306,15 @@ static int
 nix_init_flow_ctrl_config(struct rte_eth_dev *eth_dev)
 {
 	struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
-	struct cnxk_fc_cfg *fc = &dev->fc_cfg;
-	struct rte_eth_fc_conf fc_conf = {0};
-	int rc;
+	enum roc_nix_fc_mode fc_mode = ROC_NIX_FC_FULL;
 
-	/* Both Rx & Tx flow ctrl get enabled(RTE_ETH_FC_FULL) in HW
-	 * by AF driver, update those info in PMD structure.
-	 */
-	rc = cnxk_nix_flow_ctrl_get(eth_dev, &fc_conf);
-	if (rc)
-		goto exit;
+	/* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */
+	if (roc_model_is_cn96_ax() &&
+	    dev->npc.switch_header_type != ROC_PRIV_FLAGS_HIGIG)
+		fc_mode = ROC_NIX_FC_TX;
 
-	fc->mode = fc_conf.mode;
-	fc->rx_pause = (fc_conf.mode == RTE_ETH_FC_FULL) ||
-			(fc_conf.mode == RTE_ETH_FC_RX_PAUSE);
-	fc->tx_pause = (fc_conf.mode == RTE_ETH_FC_FULL) ||
-			(fc_conf.mode == RTE_ETH_FC_TX_PAUSE);
-
-exit:
-	return rc;
+	/* By default enable flow control */
+	return roc_nix_fc_mode_set(&dev->nix, fc_mode);
 }
 
 static int
-- 
2.8.4

[PATCH 19/20] net/cnxk: add dev args for min-max spi

[Nithin Dabilpuram]

Add support for inline inbound SPI range via devargs
instead of just max SPI value and range being 0..max.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 doc/guides/nics/cnxk.rst               | 28 +++++++++++++-
 drivers/common/cnxk/roc_nix.h          |  5 ++-
 drivers/common/cnxk/roc_nix_inl.c      | 68 ++++++++++++++++++++--------------
 drivers/common/cnxk/roc_nix_inl.h      |  8 ++--
 drivers/common/cnxk/roc_nix_inl_dev.c  | 22 +++++++----
 drivers/common/cnxk/roc_nix_inl_priv.h |  4 +-
 drivers/common/cnxk/roc_nix_priv.h     |  1 +
 drivers/common/cnxk/version.map        |  2 +-
 drivers/net/cnxk/cn10k_ethdev_sec.c    | 13 +++++--
 drivers/net/cnxk/cn9k_ethdev_sec.c     | 10 +++--
 drivers/net/cnxk/cnxk_ethdev_devargs.c | 25 +++++++++----
 drivers/net/cnxk/cnxk_ethdev_sec.c     | 16 ++++++--
 drivers/net/cnxk/cnxk_lookup.c         |  3 +-
 13 files changed, 142 insertions(+), 63 deletions(-)

diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst
index 27a9420..e7c5ea5 100644
--- a/doc/guides/nics/cnxk.rst
+++ b/doc/guides/nics/cnxk.rst
@@ -214,6 +214,18 @@ Runtime Config Options
 
       -a 0002:02:00.0,tag_as_xor=1
 
+- ``Min SPI for inbound inline IPsec`` (default ``0``)
+
+   Min SPI supported for inbound inline IPsec processing can be specified by
+   ``ipsec_in_min_spi`` ``devargs`` parameter.
+
+   For example::
+
+      -a 0002:02:00.0,ipsec_in_min_spi=6
+
+   With the above configuration, application can enable inline IPsec processing
+   for inbound SA with min SPI of 6.
+
 - ``Max SPI for inbound inline IPsec`` (default ``255``)
 
    Max SPI supported for inbound inline IPsec processing can be specified by
@@ -224,7 +236,7 @@ Runtime Config Options
       -a 0002:02:00.0,ipsec_in_max_spi=128
 
    With the above configuration, application can enable inline IPsec processing
-   for 128 inbound SAs (SPI 0-127).
+   with max SPI of 128.
 
 - ``Max SA's for outbound inline IPsec`` (default ``4096``)
 
@@ -413,6 +425,18 @@ VF ``177D:A0F1``.
 Runtime Config Options for inline device
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
+- ``Min SPI for inbound inline IPsec`` (default ``0``)
+
+   Min SPI supported for inbound inline IPsec processing can be specified by
+   ``ipsec_in_min_spi`` ``devargs`` parameter.
+
+   For example::
+
+      -a 0002:1d:00.0,ipsec_in_min_spi=6
+
+   With the above configuration, application can enable inline IPsec processing
+   for inbound SA with min SPI of 6 for traffic aggregated on inline device.
+
 - ``Max SPI for inbound inline IPsec`` (default ``255``)
 
    Max SPI supported for inbound inline IPsec processing can be specified by
@@ -423,7 +447,7 @@ Runtime Config Options for inline device
       -a 0002:1d:00.0,ipsec_in_max_spi=128
 
    With the above configuration, application can enable inline IPsec processing
-   for 128 inbound SAs (SPI 0-127) for traffic aggregated on inline device.
+   for inbound SA with max SPI of 128 for traffic aggregated on inline device.
 
 
 Debugging Options
diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 57a595f..ea58e06 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -384,8 +384,9 @@ struct roc_nix {
 	uint8_t lock_rx_ctx;
 	uint32_t outb_nb_desc;
 	uint16_t outb_nb_crypto_qs;
-	uint16_t ipsec_in_max_spi;
-	uint16_t ipsec_out_max_sa;
+	uint32_t ipsec_in_min_spi;
+	uint32_t ipsec_in_max_spi;
+	uint32_t ipsec_out_max_sa;
 	bool ipsec_out_sso_pffunc;
 	/* End of input parameters */
 	/* LMT line base for "Per Core Tx LMT line" mode*/
diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index 11a1691..7bf89a4 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -19,12 +19,16 @@ PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ ==
 static int
 nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
 {
-	uint16_t ipsec_in_max_spi = roc_nix->ipsec_in_max_spi;
+	uint32_t ipsec_in_min_spi = roc_nix->ipsec_in_min_spi;
+	uint32_t ipsec_in_max_spi = roc_nix->ipsec_in_max_spi;
 	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
 	struct roc_nix_ipsec_cfg cfg;
+	uint64_t max_sa, i;
 	size_t inb_sa_sz;
-	int rc, i;
 	void *sa;
+	int rc;
+
+	max_sa = plt_align32pow2(ipsec_in_max_spi - ipsec_in_min_spi + 1);
 
 	/* CN9K SA size is different */
 	if (roc_model_is_cn9k())
@@ -34,14 +38,15 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
 
 	/* Alloc contiguous memory for Inbound SA's */
 	nix->inb_sa_sz = inb_sa_sz;
-	nix->inb_sa_base = plt_zmalloc(inb_sa_sz * ipsec_in_max_spi,
+	nix->inb_spi_mask = max_sa - 1;
+	nix->inb_sa_base = plt_zmalloc(inb_sa_sz * max_sa,
 				       ROC_NIX_INL_SA_BASE_ALIGN);
 	if (!nix->inb_sa_base) {
 		plt_err("Failed to allocate memory for Inbound SA");
 		return -ENOMEM;
 	}
 	if (roc_model_is_cn10k()) {
-		for (i = 0; i < ipsec_in_max_spi; i++) {
+		for (i = 0; i < max_sa; i++) {
 			sa = ((uint8_t *)nix->inb_sa_base) + (i * inb_sa_sz);
 			roc_ot_ipsec_inb_sa_init(sa, true);
 		}
@@ -50,7 +55,7 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
 	memset(&cfg, 0, sizeof(cfg));
 	cfg.sa_size = inb_sa_sz;
 	cfg.iova = (uintptr_t)nix->inb_sa_base;
-	cfg.max_sa = ipsec_in_max_spi + 1;
+	cfg.max_sa = max_sa;
 	cfg.tt = SSO_TT_ORDERED;
 
 	/* Setup device specific inb SA table */
@@ -135,11 +140,13 @@ roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix, bool inb_inl_dev)
 }
 
 uint32_t
-roc_nix_inl_inb_sa_max_spi(struct roc_nix *roc_nix, bool inb_inl_dev)
+roc_nix_inl_inb_spi_range(struct roc_nix *roc_nix, bool inb_inl_dev,
+			  uint32_t *min_spi, uint32_t *max_spi)
 {
 	struct idev_cfg *idev = idev_get_cfg();
+	uint32_t min = 0, max = 0, mask = 0;
 	struct nix_inl_dev *inl_dev;
-	struct nix *nix;
+	struct nix *nix = NULL;
 
 	if (idev == NULL)
 		return 0;
@@ -147,20 +154,25 @@ roc_nix_inl_inb_sa_max_spi(struct roc_nix *roc_nix, bool inb_inl_dev)
 	if (!inb_inl_dev && roc_nix == NULL)
 		return -EINVAL;
 
-	if (roc_nix) {
+	inl_dev = idev->nix_inl_dev;
+	if (inb_inl_dev) {
+		min = inl_dev->ipsec_in_min_spi;
+		max = inl_dev->ipsec_in_max_spi;
+		mask = inl_dev->inb_spi_mask;
+	} else {
 		nix = roc_nix_to_nix_priv(roc_nix);
 		if (!nix->inl_inb_ena)
-			return 0;
+			goto exit;
+		min = roc_nix->ipsec_in_min_spi;
+		max = roc_nix->ipsec_in_max_spi;
+		mask = nix->inb_spi_mask;
 	}
-
-	if (inb_inl_dev) {
-		inl_dev = idev->nix_inl_dev;
-		if (inl_dev)
-			return inl_dev->ipsec_in_max_spi;
-		return 0;
-	}
-
-	return roc_nix->ipsec_in_max_spi;
+exit:
+	if (min_spi)
+		*min_spi = min;
+	if (max_spi)
+		*max_spi = max;
+	return mask;
 }
 
 uint32_t
@@ -194,8 +206,8 @@ roc_nix_inl_inb_sa_sz(struct roc_nix *roc_nix, bool inl_dev_sa)
 uintptr_t
 roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool inb_inl_dev, uint32_t spi)
 {
+	uint32_t max_spi, min_spi, mask;
 	uintptr_t sa_base;
-	uint32_t max_spi;
 	uint64_t sz;
 
 	sa_base = roc_nix_inl_inb_sa_base_get(roc_nix, inb_inl_dev);
@@ -204,11 +216,11 @@ roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool inb_inl_dev, uint32_t spi)
 		return 0;
 
 	/* Check if SPI is in range */
-	max_spi = roc_nix_inl_inb_sa_max_spi(roc_nix, inb_inl_dev);
-	if (spi > max_spi) {
-		plt_err("Inbound SA SPI %u exceeds max %u", spi, max_spi);
-		return 0;
-	}
+	mask = roc_nix_inl_inb_spi_range(roc_nix, inb_inl_dev, &min_spi,
+					 &max_spi);
+	if (spi > max_spi || spi < min_spi)
+		plt_warn("Inbound SA SPI %u not in range (%u..%u)", spi,
+			 min_spi, max_spi);
 
 	/* Get SA size */
 	sz = roc_nix_inl_inb_sa_sz(roc_nix, inb_inl_dev);
@@ -216,7 +228,7 @@ roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool inb_inl_dev, uint32_t spi)
 		return 0;
 
 	/* Basic logic of SPI->SA for now */
-	return (sa_base + (spi * sz));
+	return (sa_base + ((spi & mask) * sz));
 }
 
 int
@@ -295,11 +307,11 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
 	struct nix_inl_dev *inl_dev;
 	uint16_t sso_pffunc;
 	uint8_t eng_grpmask;
-	uint64_t blkaddr;
+	uint64_t blkaddr, i;
 	uint16_t nb_lf;
 	void *sa_base;
 	size_t sa_sz;
-	int i, j, rc;
+	int j, rc;
 	void *sa;
 
 	if (idev == NULL)
@@ -775,7 +787,7 @@ roc_nix_inl_inb_tag_update(struct roc_nix *roc_nix, uint32_t tag_const,
 	memset(&cfg, 0, sizeof(cfg));
 	cfg.sa_size = nix->inb_sa_sz;
 	cfg.iova = (uintptr_t)nix->inb_sa_base;
-	cfg.max_sa = roc_nix->ipsec_in_max_spi + 1;
+	cfg.max_sa = nix->inb_spi_mask + 1;
 	cfg.tt = tt;
 	cfg.tag_const = tag_const;
 
diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h
index 728225b..5eb1a81 100644
--- a/drivers/common/cnxk/roc_nix_inl.h
+++ b/drivers/common/cnxk/roc_nix_inl.h
@@ -105,7 +105,8 @@ typedef void (*roc_nix_inl_sso_work_cb_t)(uint64_t *gw, void *args);
 struct roc_nix_inl_dev {
 	/* Input parameters */
 	struct plt_pci_device *pci_dev;
-	uint16_t ipsec_in_max_spi;
+	uint32_t ipsec_in_min_spi;
+	uint32_t ipsec_in_max_spi;
 	bool selftest;
 	bool is_multi_channel;
 	uint16_t channel;
@@ -136,8 +137,9 @@ int __roc_api roc_nix_inl_inb_fini(struct roc_nix *roc_nix);
 bool __roc_api roc_nix_inl_inb_is_enabled(struct roc_nix *roc_nix);
 uintptr_t __roc_api roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix,
 						bool inl_dev_sa);
-uint32_t __roc_api roc_nix_inl_inb_sa_max_spi(struct roc_nix *roc_nix,
-					      bool inl_dev_sa);
+uint32_t __roc_api roc_nix_inl_inb_spi_range(struct roc_nix *roc_nix,
+					     bool inl_dev_sa, uint32_t *min,
+					     uint32_t *max);
 uint32_t __roc_api roc_nix_inl_inb_sa_sz(struct roc_nix *roc_nix,
 					 bool inl_dev_sa);
 uintptr_t __roc_api roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix,
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c
index 4c1d85a..aeec406 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -120,6 +120,7 @@ nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool ena)
 {
 	struct nix_inline_ipsec_lf_cfg *lf_cfg;
 	struct mbox *mbox = (&inl_dev->dev)->mbox;
+	uint64_t max_sa;
 	uint32_t sa_w;
 
 	lf_cfg = mbox_alloc_msg_nix_inline_ipsec_lf_cfg(mbox);
@@ -127,8 +128,9 @@ nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool ena)
 		return -ENOSPC;
 
 	if (ena) {
-		sa_w = plt_align32pow2(inl_dev->ipsec_in_max_spi + 1);
-		sa_w = plt_log2_u32(sa_w);
+
+		max_sa = inl_dev->inb_spi_mask + 1;
+		sa_w = plt_log2_u32(max_sa);
 
 		lf_cfg->enable = 1;
 		lf_cfg->sa_base_addr = (uintptr_t)inl_dev->inb_sa_base;
@@ -138,7 +140,7 @@ nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool ena)
 			lf_cfg->ipsec_cfg0.lenm1_max = NIX_CN9K_MAX_HW_FRS - 1;
 		else
 			lf_cfg->ipsec_cfg0.lenm1_max = NIX_RPM_MAX_HW_FRS - 1;
-		lf_cfg->ipsec_cfg1.sa_idx_max = inl_dev->ipsec_in_max_spi;
+		lf_cfg->ipsec_cfg1.sa_idx_max = max_sa - 1;
 		lf_cfg->ipsec_cfg0.sa_pow2_size =
 			plt_log2_u32(inl_dev->inb_sa_sz);
 
@@ -319,16 +321,20 @@ nix_inl_sso_release(struct nix_inl_dev *inl_dev)
 static int
 nix_inl_nix_setup(struct nix_inl_dev *inl_dev)
 {
-	uint16_t ipsec_in_max_spi = inl_dev->ipsec_in_max_spi;
+	uint32_t ipsec_in_min_spi = inl_dev->ipsec_in_min_spi;
+	uint32_t ipsec_in_max_spi = inl_dev->ipsec_in_max_spi;
 	struct dev *dev = &inl_dev->dev;
 	struct mbox *mbox = dev->mbox;
 	struct nix_lf_alloc_rsp *rsp;
 	struct nix_lf_alloc_req *req;
 	struct nix_hw_info *hw_info;
+	uint64_t max_sa, i;
 	size_t inb_sa_sz;
-	int i, rc = -ENOSPC;
+	int rc = -ENOSPC;
 	void *sa;
 
+	max_sa = plt_align32pow2(ipsec_in_max_spi - ipsec_in_min_spi + 1);
+
 	/* Alloc NIX LF needed for single RQ */
 	req = mbox_alloc_msg_nix_lf_alloc(mbox);
 	if (req == NULL)
@@ -387,7 +393,8 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev)
 
 	/* Alloc contiguous memory for Inbound SA's */
 	inl_dev->inb_sa_sz = inb_sa_sz;
-	inl_dev->inb_sa_base = plt_zmalloc(inb_sa_sz * ipsec_in_max_spi,
+	inl_dev->inb_spi_mask = max_sa - 1;
+	inl_dev->inb_sa_base = plt_zmalloc(inb_sa_sz * max_sa,
 					   ROC_NIX_INL_SA_BASE_ALIGN);
 	if (!inl_dev->inb_sa_base) {
 		plt_err("Failed to allocate memory for Inbound SA");
@@ -396,7 +403,7 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev)
 	}
 
 	if (roc_model_is_cn10k()) {
-		for (i = 0; i < ipsec_in_max_spi; i++) {
+		for (i = 0; i < max_sa; i++) {
 			sa = ((uint8_t *)inl_dev->inb_sa_base) +
 			     (i * inb_sa_sz);
 			roc_ot_ipsec_inb_sa_init(sa, true);
@@ -657,6 +664,7 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)
 	memset(inl_dev, 0, sizeof(*inl_dev));
 
 	inl_dev->pci_dev = pci_dev;
+	inl_dev->ipsec_in_min_spi = roc_inl_dev->ipsec_in_min_spi;
 	inl_dev->ipsec_in_max_spi = roc_inl_dev->ipsec_in_max_spi;
 	inl_dev->selftest = roc_inl_dev->selftest;
 	inl_dev->is_multi_channel = roc_inl_dev->is_multi_channel;
diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h
index b6d8602..24dabbc 100644
--- a/drivers/common/cnxk/roc_nix_inl_priv.h
+++ b/drivers/common/cnxk/roc_nix_inl_priv.h
@@ -58,7 +58,9 @@ struct nix_inl_dev {
 	uint16_t channel;
 	uint16_t chan_mask;
 	bool is_multi_channel;
-	uint16_t ipsec_in_max_spi;
+	uint32_t ipsec_in_min_spi;
+	uint32_t ipsec_in_max_spi;
+	uint32_t inb_spi_mask;
 	bool attach_cptlf;
 	bool wqe_skip;
 };
diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h
index ec6f106..51b022e 100644
--- a/drivers/common/cnxk/roc_nix_priv.h
+++ b/drivers/common/cnxk/roc_nix_priv.h
@@ -174,6 +174,7 @@ struct nix {
 	bool inl_outb_ena;
 	void *inb_sa_base;
 	size_t inb_sa_sz;
+	uint32_t inb_spi_mask;
 	void *outb_sa_base;
 	size_t outb_sa_sz;
 	uint16_t outb_err_sso_pffunc;
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 0f990d3..2a64090 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -142,7 +142,7 @@ INTERNAL {
 	roc_nix_inl_inb_init;
 	roc_nix_inl_inb_sa_base_get;
 	roc_nix_inl_inb_sa_get;
-	roc_nix_inl_inb_sa_max_spi;
+	roc_nix_inl_inb_spi_range;
 	roc_nix_inl_inb_sa_sz;
 	roc_nix_inl_inb_tag_update;
 	roc_nix_inl_inb_fini;
diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c
index 044b20c..a2a53c1 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -264,6 +264,7 @@ cn10k_eth_sec_session_create(void *device,
 	struct cn10k_sec_sess_priv sess_priv;
 	struct rte_crypto_sym_xform *crypto;
 	struct cnxk_eth_sec_sess *eth_sec;
+	struct roc_nix *nix = &dev->nix;
 	bool inbound, inl_dev;
 	rte_spinlock_t *lock;
 	char tbuf[128] = {0};
@@ -308,13 +309,16 @@ cn10k_eth_sec_session_create(void *device,
 	if (inbound) {
 		struct roc_ot_ipsec_inb_sa *inb_sa, *inb_sa_dptr;
 		struct cn10k_inb_priv_data *inb_priv;
+		uint32_t spi_mask;
 		uintptr_t sa;
 
 		PLT_STATIC_ASSERT(sizeof(struct cn10k_inb_priv_data) <
 				  ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD);
 
+		spi_mask = roc_nix_inl_inb_spi_range(nix, inl_dev, NULL, NULL);
+
 		/* Get Inbound SA from NIX_RX_IPSEC_SA_BASE */
-		sa = roc_nix_inl_inb_sa_get(&dev->nix, inl_dev, ipsec->spi);
+		sa = roc_nix_inl_inb_sa_get(nix, inl_dev, ipsec->spi);
 		if (!sa && dev->inb.inl_dev) {
 			snprintf(tbuf, sizeof(tbuf),
 				 "Failed to create ingress sa, inline dev "
@@ -358,16 +362,17 @@ cn10k_eth_sec_session_create(void *device,
 		inb_priv->userdata = conf->userdata;
 
 		/* Save SA index/SPI in cookie for now */
-		inb_sa_dptr->w1.s.cookie = rte_cpu_to_be_32(ipsec->spi);
+		inb_sa_dptr->w1.s.cookie =
+			rte_cpu_to_be_32(ipsec->spi & spi_mask);
 
 		/* Prepare session priv */
 		sess_priv.inb_sa = 1;
-		sess_priv.sa_idx = ipsec->spi;
+		sess_priv.sa_idx = ipsec->spi & spi_mask;
 
 		/* Pointer from eth_sec -> inb_sa */
 		eth_sec->sa = inb_sa;
 		eth_sec->sess = sess;
-		eth_sec->sa_idx = ipsec->spi;
+		eth_sec->sa_idx = ipsec->spi & spi_mask;
 		eth_sec->spi = ipsec->spi;
 		eth_sec->inl_dev = !!dev->inb.inl_dev;
 		eth_sec->inb = true;
diff --git a/drivers/net/cnxk/cn9k_ethdev_sec.c b/drivers/net/cnxk/cn9k_ethdev_sec.c
index 27930d1..fa72424 100644
--- a/drivers/net/cnxk/cn9k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn9k_ethdev_sec.c
@@ -146,6 +146,7 @@ cn9k_eth_sec_session_create(void *device,
 	struct cn9k_sec_sess_priv sess_priv;
 	struct rte_crypto_sym_xform *crypto;
 	struct cnxk_eth_sec_sess *eth_sec;
+	struct roc_nix *nix = &dev->nix;
 	rte_spinlock_t *lock;
 	char tbuf[128] = {0};
 	bool inbound;
@@ -185,15 +186,18 @@ cn9k_eth_sec_session_create(void *device,
 	if (inbound) {
 		struct cn9k_inb_priv_data *inb_priv;
 		struct roc_onf_ipsec_inb_sa *inb_sa;
+		uint32_t spi_mask;
 
 		PLT_STATIC_ASSERT(sizeof(struct cn9k_inb_priv_data) <
 				  ROC_NIX_INL_ONF_IPSEC_INB_SW_RSVD);
 
+		spi_mask = roc_nix_inl_inb_spi_range(nix, false, NULL, NULL);
+
 		/* Get Inbound SA from NIX_RX_IPSEC_SA_BASE. Assume no inline
 		 * device always for CN9K.
 		 */
 		inb_sa = (struct roc_onf_ipsec_inb_sa *)
-			 roc_nix_inl_inb_sa_get(&dev->nix, false, ipsec->spi);
+			 roc_nix_inl_inb_sa_get(nix, false, ipsec->spi);
 		if (!inb_sa) {
 			snprintf(tbuf, sizeof(tbuf),
 				 "Failed to create ingress sa");
@@ -236,12 +240,12 @@ cn9k_eth_sec_session_create(void *device,
 
 		/* Prepare session priv */
 		sess_priv.inb_sa = 1;
-		sess_priv.sa_idx = ipsec->spi;
+		sess_priv.sa_idx = ipsec->spi & spi_mask;
 
 		/* Pointer from eth_sec -> inb_sa */
 		eth_sec->sa = inb_sa;
 		eth_sec->sess = sess;
-		eth_sec->sa_idx = ipsec->spi;
+		eth_sec->sa_idx = ipsec->spi & spi_mask;
 		eth_sec->spi = ipsec->spi;
 		eth_sec->inb = true;
 
diff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c
index 157b27d..8a71644 100644
--- a/drivers/net/cnxk/cnxk_ethdev_devargs.c
+++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c
@@ -49,14 +49,17 @@ parse_outb_nb_crypto_qs(const char *key, const char *value, void *extra_args)
 }
 
 static int
-parse_ipsec_in_max_spi(const char *key, const char *value, void *extra_args)
+parse_ipsec_in_spi_range(const char *key, const char *value, void *extra_args)
 {
 	RTE_SET_USED(key);
 	uint32_t val;
 
-	val = atoi(value);
+	errno = 0;
+	val = strtoul(value, NULL, 0);
+	if (errno)
+		val = 0;
 
-	*(uint16_t *)extra_args = val;
+	*(uint32_t *)extra_args = val;
 
 	return 0;
 }
@@ -67,7 +70,10 @@ parse_ipsec_out_max_sa(const char *key, const char *value, void *extra_args)
 	RTE_SET_USED(key);
 	uint32_t val;
 
-	val = atoi(value);
+	errno = 0;
+	val = strtoul(value, NULL, 0);
+	if (errno)
+		val = 0;
 
 	*(uint16_t *)extra_args = val;
 
@@ -231,6 +237,7 @@ parse_sdp_channel_mask(const char *key, const char *value, void *extra_args)
 #define CNXK_SWITCH_HEADER_TYPE "switch_header"
 #define CNXK_RSS_TAG_AS_XOR	"tag_as_xor"
 #define CNXK_LOCK_RX_CTX	"lock_rx_ctx"
+#define CNXK_IPSEC_IN_MIN_SPI	"ipsec_in_min_spi"
 #define CNXK_IPSEC_IN_MAX_SPI	"ipsec_in_max_spi"
 #define CNXK_IPSEC_OUT_MAX_SA	"ipsec_out_max_sa"
 #define CNXK_OUTB_NB_DESC	"outb_nb_desc"
@@ -245,13 +252,14 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
 	uint16_t reta_sz = ROC_NIX_RSS_RETA_SZ_64;
 	uint16_t sqb_count = CNXK_NIX_TX_MAX_SQB;
 	struct flow_pre_l2_size_info pre_l2_info;
-	uint16_t ipsec_in_max_spi = BIT(8) - 1;
-	uint16_t ipsec_out_max_sa = BIT(12);
+	uint32_t ipsec_in_max_spi = BIT(8) - 1;
+	uint32_t ipsec_out_max_sa = BIT(12);
 	uint16_t flow_prealloc_size = 1;
 	uint16_t switch_header_type = 0;
 	uint16_t flow_max_priority = 3;
 	uint16_t force_inb_inl_dev = 0;
 	uint16_t outb_nb_crypto_qs = 1;
+	uint32_t ipsec_in_min_spi = 0;
 	uint16_t outb_nb_desc = 8200;
 	struct sdp_channel sdp_chan;
 	uint16_t rss_tag_as_xor = 0;
@@ -284,8 +292,10 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
 	rte_kvargs_process(kvlist, CNXK_RSS_TAG_AS_XOR, &parse_flag,
 			   &rss_tag_as_xor);
 	rte_kvargs_process(kvlist, CNXK_LOCK_RX_CTX, &parse_flag, &lock_rx_ctx);
+	rte_kvargs_process(kvlist, CNXK_IPSEC_IN_MIN_SPI,
+			   &parse_ipsec_in_spi_range, &ipsec_in_min_spi);
 	rte_kvargs_process(kvlist, CNXK_IPSEC_IN_MAX_SPI,
-			   &parse_ipsec_in_max_spi, &ipsec_in_max_spi);
+			   &parse_ipsec_in_spi_range, &ipsec_in_max_spi);
 	rte_kvargs_process(kvlist, CNXK_IPSEC_OUT_MAX_SA,
 			   &parse_ipsec_out_max_sa, &ipsec_out_max_sa);
 	rte_kvargs_process(kvlist, CNXK_OUTB_NB_DESC, &parse_outb_nb_desc,
@@ -307,6 +317,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
 	dev->outb.max_sa = ipsec_out_max_sa;
 	dev->outb.nb_desc = outb_nb_desc;
 	dev->outb.nb_crypto_qs = outb_nb_crypto_qs;
+	dev->nix.ipsec_in_min_spi = ipsec_in_min_spi;
 	dev->nix.ipsec_in_max_spi = ipsec_in_max_spi;
 	dev->nix.ipsec_out_max_sa = ipsec_out_max_sa;
 	dev->nix.rss_tag_as_xor = !!rss_tag_as_xor;
diff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c
index ea204ca..3831889 100644
--- a/drivers/net/cnxk/cnxk_ethdev_sec.c
+++ b/drivers/net/cnxk/cnxk_ethdev_sec.c
@@ -5,6 +5,7 @@
 #include <cnxk_ethdev.h>
 
 #define CNXK_NIX_INL_SELFTEST	      "selftest"
+#define CNXK_NIX_INL_IPSEC_IN_MIN_SPI "ipsec_in_min_spi"
 #define CNXK_NIX_INL_IPSEC_IN_MAX_SPI "ipsec_in_max_spi"
 #define CNXK_INL_CPT_CHANNEL	      "inl_cpt_channel"
 
@@ -119,14 +120,17 @@ struct rte_security_ops cnxk_eth_sec_ops = {
 };
 
 static int
-parse_ipsec_in_max_spi(const char *key, const char *value, void *extra_args)
+parse_ipsec_in_spi_range(const char *key, const char *value, void *extra_args)
 {
 	RTE_SET_USED(key);
 	uint32_t val;
 
-	val = atoi(value);
+	errno = 0;
+	val = strtoul(value, NULL, 0);
+	if (errno)
+		val = 0;
 
-	*(uint16_t *)extra_args = val;
+	*(uint32_t *)extra_args = val;
 
 	return 0;
 }
@@ -169,6 +173,7 @@ nix_inl_parse_devargs(struct rte_devargs *devargs,
 		      struct roc_nix_inl_dev *inl_dev)
 {
 	uint32_t ipsec_in_max_spi = BIT(8) - 1;
+	uint32_t ipsec_in_min_spi = 0;
 	struct inl_cpt_channel cpt_channel;
 	struct rte_kvargs *kvlist;
 	uint8_t selftest = 0;
@@ -184,13 +189,16 @@ nix_inl_parse_devargs(struct rte_devargs *devargs,
 
 	rte_kvargs_process(kvlist, CNXK_NIX_INL_SELFTEST, &parse_selftest,
 			   &selftest);
+	rte_kvargs_process(kvlist, CNXK_NIX_INL_IPSEC_IN_MIN_SPI,
+			   &parse_ipsec_in_spi_range, &ipsec_in_min_spi);
 	rte_kvargs_process(kvlist, CNXK_NIX_INL_IPSEC_IN_MAX_SPI,
-			   &parse_ipsec_in_max_spi, &ipsec_in_max_spi);
+			   &parse_ipsec_in_spi_range, &ipsec_in_max_spi);
 	rte_kvargs_process(kvlist, CNXK_INL_CPT_CHANNEL, &parse_inl_cpt_channel,
 			   &cpt_channel);
 	rte_kvargs_free(kvlist);
 
 null_devargs:
+	inl_dev->ipsec_in_min_spi = ipsec_in_min_spi;
 	inl_dev->ipsec_in_max_spi = ipsec_in_max_spi;
 	inl_dev->selftest = selftest;
 	inl_dev->channel = cpt_channel.channel;
diff --git a/drivers/net/cnxk/cnxk_lookup.c b/drivers/net/cnxk/cnxk_lookup.c
index 4eb1ecf..f36fb8f 100644
--- a/drivers/net/cnxk/cnxk_lookup.c
+++ b/drivers/net/cnxk/cnxk_lookup.c
@@ -337,7 +337,8 @@ cnxk_nix_lookup_mem_sa_base_set(struct cnxk_eth_dev *dev)
 	if (!sa_base)
 		return -ENOTSUP;
 
-	sa_w = plt_log2_u32(dev->nix.ipsec_in_max_spi + 1);
+	sa_w = plt_log2_u32(dev->nix.ipsec_in_max_spi + 1 -
+			    dev->nix.ipsec_in_min_spi);
 
 	/* Set SA Base in lookup mem */
 	sa_base_tbl = (uintptr_t)lookup_mem;
-- 
2.8.4

[PATCH 20/20] net/cnxk: add option to override outbound inline sa iv

[Nithin Dabilpuram]

Add option to override outbound inline sa iv for debug
purposes via environment variable. User can set env variable as:
export CN10K_ETH_SEC_IV_OVR="0x0, 0x0,..."

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/net/cnxk/cn10k_ethdev_sec.c | 62 +++++++++++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c
index a2a53c1..a514345 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -252,6 +252,63 @@ cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args)
 	cnxk_pktmbuf_free_no_cache(mbuf);
 }
 
+static void
+outb_dbg_iv_update(struct roc_ot_ipsec_outb_sa *outb_sa, const char *__iv_str)
+{
+	uint8_t *iv_dbg = outb_sa->iv.iv_dbg;
+	char *iv_str = strdup(__iv_str);
+	char *iv_b = NULL, len = 16;
+	char *save;
+	int i;
+
+	if (!iv_str)
+		return;
+
+	if (outb_sa->w2.s.enc_type == ROC_IE_OT_SA_ENC_AES_GCM ||
+	    outb_sa->w2.s.enc_type == ROC_IE_OT_SA_ENC_AES_CTR ||
+	    outb_sa->w2.s.enc_type == ROC_IE_OT_SA_ENC_AES_CCM ||
+	    outb_sa->w2.s.auth_type == ROC_IE_OT_SA_AUTH_AES_GMAC) {
+		memset(outb_sa->iv.s.iv_dbg1, 0, sizeof(outb_sa->iv.s.iv_dbg1));
+		memset(outb_sa->iv.s.iv_dbg2, 0, sizeof(outb_sa->iv.s.iv_dbg2));
+
+		iv_dbg = outb_sa->iv.s.iv_dbg1;
+		for (i = 0; i < 4; i++) {
+			iv_b = strtok_r(i ? NULL : iv_str, ",", &save);
+			if (!iv_b)
+				break;
+			iv_dbg[i] = strtoul(iv_b, NULL, 0);
+		}
+		*(uint32_t *)iv_dbg = rte_be_to_cpu_32(*(uint32_t *)iv_dbg);
+
+		iv_dbg = outb_sa->iv.s.iv_dbg2;
+		for (i = 0; i < 4; i++) {
+			iv_b = strtok_r(NULL, ",", &save);
+			if (!iv_b)
+				break;
+			iv_dbg[i] = strtoul(iv_b, NULL, 0);
+		}
+		*(uint32_t *)iv_dbg = rte_be_to_cpu_32(*(uint32_t *)iv_dbg);
+
+	} else {
+		iv_dbg = outb_sa->iv.iv_dbg;
+		memset(iv_dbg, 0, sizeof(outb_sa->iv.iv_dbg));
+
+		for (i = 0; i < len; i++) {
+			iv_b = strtok_r(i ? NULL : iv_str, ",", &save);
+			if (!iv_b)
+				break;
+			iv_dbg[i] = strtoul(iv_b, NULL, 0);
+		}
+		*(uint64_t *)iv_dbg = rte_be_to_cpu_64(*(uint64_t *)iv_dbg);
+		*(uint64_t *)&iv_dbg[8] =
+			rte_be_to_cpu_64(*(uint64_t *)&iv_dbg[8]);
+	}
+
+	/* Update source of IV */
+	outb_sa->w2.s.iv_src = ROC_IE_OT_SA_IV_SRC_FROM_SA;
+	free(iv_str);
+}
+
 static int
 cn10k_eth_sec_session_create(void *device,
 			     struct rte_security_session_conf *conf,
@@ -390,6 +447,7 @@ cn10k_eth_sec_session_create(void *device,
 		struct cn10k_outb_priv_data *outb_priv;
 		struct cnxk_ipsec_outb_rlens *rlens;
 		uint64_t sa_base = dev->outb.sa_base;
+		const char *iv_str;
 		uint32_t sa_idx;
 
 		PLT_STATIC_ASSERT(sizeof(struct cn10k_outb_priv_data) <
@@ -416,6 +474,10 @@ cn10k_eth_sec_session_create(void *device,
 			goto mempool_put;
 		}
 
+		iv_str = getenv("CN10K_ETH_SEC_IV_OVR");
+		if (iv_str)
+			outb_dbg_iv_update(outb_sa_dptr, iv_str);
+
 		/* Save userdata */
 		outb_priv->userdata = conf->userdata;
 		outb_priv->sa_idx = sa_idx;
-- 
2.8.4

Re: [PATCH 20/20] net/cnxk: add option to override outbound inline sa iv

[Jerin Jacob]

On Mon, Feb 7, 2022 at 1:02 PM Nithin Dabilpuram
<ndabilpuram@marvell.com> wrote:
>
> Add option to override outbound inline sa iv for debug

sa -> SA
IV -> IV

Please check the subject too

> purposes via environment variable. User can set env variable as:
> export CN10K_ETH_SEC_IV_OVR="0x0, 0x0,..."

Please add a table for environment variables and usage in
doc/guides/platform/cnxk.rst
for the following ones as a separate patch and extended the new one there.

rivers/common/cnxk/roc_bphy_irq.c:     env = getenv("BPHY_INTR_MLOCK_DISABLE");
drivers/common/cnxk/roc_mbox.c: var = getenv("ROC_CN10K_MBOX_TIMEOUT");
drivers/common/cnxk/roc_mbox.c: var_to = getenv("ROC_MBOX_TIMEOUT");

>
> Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
> ---
>  drivers/net/cnxk/cn10k_ethdev_sec.c | 62 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 62 insertions(+)
>
> diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c
> index a2a53c1..a514345 100644
> --- a/drivers/net/cnxk/cn10k_ethdev_sec.c
> +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
> @@ -252,6 +252,63 @@ cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args)
>         cnxk_pktmbuf_free_no_cache(mbuf);
>  }
>
> +static void
> +outb_dbg_iv_update(struct roc_ot_ipsec_outb_sa *outb_sa, const char *__iv_str)
> +{
> +       uint8_t *iv_dbg = outb_sa->iv.iv_dbg;
> +       char *iv_str = strdup(__iv_str);
> +       char *iv_b = NULL, len = 16;
> +       char *save;
> +       int i;
> +
> +       if (!iv_str)
> +               return;
> +
> +       if (outb_sa->w2.s.enc_type == ROC_IE_OT_SA_ENC_AES_GCM ||
> +           outb_sa->w2.s.enc_type == ROC_IE_OT_SA_ENC_AES_CTR ||
> +           outb_sa->w2.s.enc_type == ROC_IE_OT_SA_ENC_AES_CCM ||
> +           outb_sa->w2.s.auth_type == ROC_IE_OT_SA_AUTH_AES_GMAC) {
> +               memset(outb_sa->iv.s.iv_dbg1, 0, sizeof(outb_sa->iv.s.iv_dbg1));
> +               memset(outb_sa->iv.s.iv_dbg2, 0, sizeof(outb_sa->iv.s.iv_dbg2));
> +
> +               iv_dbg = outb_sa->iv.s.iv_dbg1;
> +               for (i = 0; i < 4; i++) {
> +                       iv_b = strtok_r(i ? NULL : iv_str, ",", &save);
> +                       if (!iv_b)
> +                               break;
> +                       iv_dbg[i] = strtoul(iv_b, NULL, 0);
> +               }
> +               *(uint32_t *)iv_dbg = rte_be_to_cpu_32(*(uint32_t *)iv_dbg);
> +
> +               iv_dbg = outb_sa->iv.s.iv_dbg2;
> +               for (i = 0; i < 4; i++) {
> +                       iv_b = strtok_r(NULL, ",", &save);
> +                       if (!iv_b)
> +                               break;
> +                       iv_dbg[i] = strtoul(iv_b, NULL, 0);
> +               }
> +               *(uint32_t *)iv_dbg = rte_be_to_cpu_32(*(uint32_t *)iv_dbg);
> +
> +       } else {
> +               iv_dbg = outb_sa->iv.iv_dbg;
> +               memset(iv_dbg, 0, sizeof(outb_sa->iv.iv_dbg));
> +
> +               for (i = 0; i < len; i++) {
> +                       iv_b = strtok_r(i ? NULL : iv_str, ",", &save);
> +                       if (!iv_b)
> +                               break;
> +                       iv_dbg[i] = strtoul(iv_b, NULL, 0);
> +               }
> +               *(uint64_t *)iv_dbg = rte_be_to_cpu_64(*(uint64_t *)iv_dbg);
> +               *(uint64_t *)&iv_dbg[8] =
> +                       rte_be_to_cpu_64(*(uint64_t *)&iv_dbg[8]);
> +       }
> +
> +       /* Update source of IV */
> +       outb_sa->w2.s.iv_src = ROC_IE_OT_SA_IV_SRC_FROM_SA;
> +       free(iv_str);
> +}
> +
>  static int
>  cn10k_eth_sec_session_create(void *device,
>                              struct rte_security_session_conf *conf,
> @@ -390,6 +447,7 @@ cn10k_eth_sec_session_create(void *device,
>                 struct cn10k_outb_priv_data *outb_priv;
>                 struct cnxk_ipsec_outb_rlens *rlens;
>                 uint64_t sa_base = dev->outb.sa_base;
> +               const char *iv_str;
>                 uint32_t sa_idx;
>
>                 PLT_STATIC_ASSERT(sizeof(struct cn10k_outb_priv_data) <
> @@ -416,6 +474,10 @@ cn10k_eth_sec_session_create(void *device,
>                         goto mempool_put;
>                 }
>
> +               iv_str = getenv("CN10K_ETH_SEC_IV_OVR");
> +               if (iv_str)
> +                       outb_dbg_iv_update(outb_sa_dptr, iv_str);
> +
>                 /* Save userdata */
>                 outb_priv->userdata = conf->userdata;
>                 outb_priv->sa_idx = sa_idx;
> --
> 2.8.4
>

Re: [PATCH 01/20] common/cnxk: increase resource count for bitmap alloc

[Jerin Jacob]

On Mon, Feb 7, 2022 at 1:00 PM Nithin Dabilpuram
<ndabilpuram@marvell.com> wrote:
>
> From: Satha Rao <skoteshwar@marvell.com>
>
> CN10K supports up to 832 resources at SMQ level, so increase
> bitmap count to 1024.
>
> Signed-off-by: Satha Rao <skoteshwar@marvell.com>


Please rebase to next-net-mrvl and fix the following checkpatch issues.

[for-next-net]dell[dpdk-next-net-mrvl] $ git pw series apply 21483
Failed to apply patch:
Applying: common/cnxk: increase resource count for bitmap alloc
Applying: common/cnxk: realloc inline device XAQ AURA
Applying: common/cnxk: adjust shaper rates to lower boundaries
Applying: common/cnxk: support inline device API without ROC NIX
Applying: common/cnxk: use common SA init API for default options
error: sha1 information is lacking or useless (drivers/common/cnxk/version.map).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0005 common/cnxk: use common SA init API for default options
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".


check patch issues:


CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#2065: FILE: drivers/net/cnxk/cn10k_rx.h:963:
+                                        roc_npa_aura_handle_to_aura(

CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#2092: FILE: drivers/net/cnxk/cn10k_rx.h:987:
+                                        roc_npa_aura_handle_to_aura(

total: 0 errors, 0 warnings, 3 checks, 2235 lines checked

> ---
>
> Depends-on: Series-20935 ("common/cnxk: use XAQ create API for inline device")
> Depends-on: Series-20934 ("common/cnxk: add workaround for vWQE flush")
>  drivers/common/cnxk/roc_nix_priv.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h
> index deb2a6b..4d2a7d8 100644
> --- a/drivers/common/cnxk/roc_nix_priv.h
> +++ b/drivers/common/cnxk/roc_nix_priv.h
> @@ -31,7 +31,7 @@ struct nix_qint {
>  };
>
>  /* Traffic Manager */
> -#define NIX_TM_MAX_HW_TXSCHQ 512
> +#define NIX_TM_MAX_HW_TXSCHQ 1024
>  #define NIX_TM_HW_ID_INVALID UINT32_MAX
>
>  /* TM flags */
> --
> 2.8.4
>

Re: [PATCH 01/20] common/cnxk: increase resource count for bitmap alloc

[Jerin Jacob]

On Mon, Feb 7, 2022 at 1:00 PM Nithin Dabilpuram
<ndabilpuram@marvell.com> wrote:
>
> From: Satha Rao <skoteshwar@marvell.com>
>
> CN10K supports up to 832 resources at SMQ level, so increase
> bitmap count to 1024.
>
> Signed-off-by: Satha Rao <skoteshwar@marvell.com>
> ---

Please change the subject as common/cnxk: increase SMQ resource count

> Depends-on: Series-20935 ("common/cnxk: use XAQ create API for inline device")
> Depends-on: Series-20934 ("common/cnxk: add workaround for vWQE flush")
>  drivers/common/cnxk/roc_nix_priv.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h
> index deb2a6b..4d2a7d8 100644
> --- a/drivers/common/cnxk/roc_nix_priv.h
> +++ b/drivers/common/cnxk/roc_nix_priv.h
> @@ -31,7 +31,7 @@ struct nix_qint {
>  };
>
>  /* Traffic Manager */
> -#define NIX_TM_MAX_HW_TXSCHQ 512
> +#define NIX_TM_MAX_HW_TXSCHQ 1024
>  #define NIX_TM_HW_ID_INVALID UINT32_MAX
>
>  /* TM flags */
> --
> 2.8.4
>

[PATCH v2 01/21] common/cnxk: increase SMQ resource count

[Nithin Dabilpuram]

From: Satha Rao <skoteshwar@marvell.com>

CN10K supports up to 832 resources at SMQ level, so increase
bitmap count to 1024.

Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---

v2:
- Addressed comments from Jerin on patches 1/20, 3/20, 7/20,
  8/20, 10/20, 11/20, 15/20 and 20/20.
- Added another patch to update documentation on environment variables
- Fixed functional issues with patch 18/20.

 drivers/common/cnxk/roc_nix_priv.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h
index deb2a6b..4d2a7d8 100644
--- a/drivers/common/cnxk/roc_nix_priv.h
+++ b/drivers/common/cnxk/roc_nix_priv.h
@@ -31,7 +31,7 @@ struct nix_qint {
 };
 
 /* Traffic Manager */
-#define NIX_TM_MAX_HW_TXSCHQ 512
+#define NIX_TM_MAX_HW_TXSCHQ 1024
 #define NIX_TM_HW_ID_INVALID UINT32_MAX
 
 /* TM flags */
-- 
2.8.4

[PATCH v2 02/21] common/cnxk: realloc inline device XAQ AURA

[Nithin Dabilpuram]

Add support to realloc inline device XAQ AURA with more
buffers of new packet pool AURA.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/common/cnxk/roc_nix_inl.h         |   1 +
 drivers/common/cnxk/roc_nix_inl_dev.c     | 110 +++++++++++++++++++++++++++++-
 drivers/common/cnxk/roc_nix_inl_dev_irq.c |   2 +-
 drivers/common/cnxk/roc_nix_inl_priv.h    |   3 +
 drivers/common/cnxk/roc_platform.h        |   1 +
 drivers/common/cnxk/version.map           |   3 +-
 6 files changed, 115 insertions(+), 5 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h
index abbeac6..bbdcbc8 100644
--- a/drivers/common/cnxk/roc_nix_inl.h
+++ b/drivers/common/cnxk/roc_nix_inl.h
@@ -124,6 +124,7 @@ void __roc_api roc_nix_inl_dev_dump(struct roc_nix_inl_dev *roc_inl_dev);
 bool __roc_api roc_nix_inl_dev_is_probed(void);
 void __roc_api roc_nix_inl_dev_lock(void);
 void __roc_api roc_nix_inl_dev_unlock(void);
+int __roc_api roc_nix_inl_dev_xaq_realloc(uint64_t aura_handle);
 
 /* NIX Inline Inbound API */
 int __roc_api roc_nix_inl_inb_init(struct roc_nix *roc_nix);
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c
index dd93765..1d14f04 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -219,7 +219,6 @@ nix_inl_sso_setup(struct nix_inl_dev *inl_dev)
 	struct sso_lf_alloc_rsp *sso_rsp;
 	struct dev *dev = &inl_dev->dev;
 	uint16_t hwgrp[1] = {0};
-	uint32_t xae_cnt;
 	int rc;
 
 	/* Alloc SSOW LF */
@@ -240,8 +239,8 @@ nix_inl_sso_setup(struct nix_inl_dev *inl_dev)
 	inl_dev->xae_waes = sso_rsp->xaq_wq_entries;
 	inl_dev->iue = sso_rsp->in_unit_entries;
 
-	xae_cnt = inl_dev->iue;
-	rc = sso_hwgrp_init_xaq_aura(dev, &inl_dev->xaq, xae_cnt,
+	inl_dev->nb_xae = inl_dev->iue;
+	rc = sso_hwgrp_init_xaq_aura(dev, &inl_dev->xaq, inl_dev->nb_xae,
 				     inl_dev->xae_waes, inl_dev->xaq_buf_size,
 				     1);
 	if (rc) {
@@ -518,6 +517,111 @@ nix_inl_lf_detach(struct nix_inl_dev *inl_dev)
 	return mbox_process(dev->mbox);
 }
 
+static int
+nix_inl_dev_wait_for_sso_empty(struct nix_inl_dev *inl_dev)
+{
+	uintptr_t sso_base = inl_dev->sso_base;
+	int wait_ms = 3000;
+
+	while (wait_ms > 0) {
+		/* Break when empty */
+		if (!plt_read64(sso_base + SSO_LF_GGRP_XAQ_CNT) &&
+		    !plt_read64(sso_base + SSO_LF_GGRP_AQ_CNT))
+			return 0;
+
+		plt_delay_us(1000);
+		wait_ms -= 1;
+	}
+
+	return -ETIMEDOUT;
+}
+
+int
+roc_nix_inl_dev_xaq_realloc(uint64_t aura_handle)
+{
+	struct idev_cfg *idev = idev_get_cfg();
+	struct nix_inl_dev *inl_dev;
+	int rc, i;
+
+	if (idev == NULL)
+		return 0;
+
+	inl_dev = idev->nix_inl_dev;
+	/* Nothing to do if no inline device */
+	if (!inl_dev)
+		return 0;
+
+	if (!aura_handle) {
+		inl_dev->nb_xae = inl_dev->iue;
+		goto no_pool;
+	}
+
+	/* Check if aura is already considered */
+	for (i = 0; i < inl_dev->pkt_pools_cnt; i++) {
+		if (inl_dev->pkt_pools[i] == aura_handle)
+			return 0;
+	}
+
+no_pool:
+	/* Disable RQ if enabled */
+	if (inl_dev->rq_refs) {
+		rc = nix_rq_ena_dis(&inl_dev->dev, &inl_dev->rq, false);
+		if (rc) {
+			plt_err("Failed to disable inline dev RQ, rc=%d", rc);
+			return rc;
+		}
+	}
+
+	/* Wait for events to be removed */
+	rc = nix_inl_dev_wait_for_sso_empty(inl_dev);
+	if (rc) {
+		plt_err("Timeout waiting for inline device event cleanup");
+		goto exit;
+	}
+
+	/* Disable HWGRP */
+	plt_write64(0, inl_dev->sso_base + SSO_LF_GGRP_QCTL);
+
+	inl_dev->pkt_pools_cnt++;
+	inl_dev->pkt_pools =
+		plt_realloc(inl_dev->pkt_pools,
+			    sizeof(uint64_t *) * inl_dev->pkt_pools_cnt, 0);
+	if (!inl_dev->pkt_pools)
+		inl_dev->pkt_pools_cnt = 0;
+	else
+		inl_dev->pkt_pools[inl_dev->pkt_pools_cnt - 1] = aura_handle;
+	inl_dev->nb_xae += roc_npa_aura_op_limit_get(aura_handle);
+
+	/* Realloc XAQ aura */
+	rc = sso_hwgrp_init_xaq_aura(&inl_dev->dev, &inl_dev->xaq,
+				     inl_dev->nb_xae, inl_dev->xae_waes,
+				     inl_dev->xaq_buf_size, 1);
+	if (rc) {
+		plt_err("Failed to reinitialize xaq aura, rc=%d", rc);
+		return rc;
+	}
+
+	/* Setup xaq for hwgrps */
+	rc = sso_hwgrp_alloc_xaq(&inl_dev->dev, inl_dev->xaq.aura_handle, 1);
+	if (rc) {
+		plt_err("Failed to setup hwgrp xaq aura, rc=%d", rc);
+		return rc;
+	}
+
+	/* Enable HWGRP */
+	plt_write64(0x1, inl_dev->sso_base + SSO_LF_GGRP_QCTL);
+
+exit:
+	/* Renable RQ */
+	if (inl_dev->rq_refs) {
+		rc = nix_rq_ena_dis(&inl_dev->dev, &inl_dev->rq, true);
+		if (rc)
+			plt_err("Failed to enable inline dev RQ, rc=%d", rc);
+	}
+
+	return rc;
+}
+
 int
 roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)
 {
diff --git a/drivers/common/cnxk/roc_nix_inl_dev_irq.c b/drivers/common/cnxk/roc_nix_inl_dev_irq.c
index 848523b..d758e0c 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev_irq.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev_irq.c
@@ -72,7 +72,7 @@ nix_inl_sso_hwgrp_irq(void *param)
 	if (intr & BIT(1))
 		nix_inl_sso_work_cb(inl_dev);
 
-	if (!(intr & BIT(1)))
+	if (intr & ~BIT(1))
 		plt_err("GGRP 0 GGRP_INT=0x%" PRIx64 "", intr);
 
 	/* Clear interrupt */
diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h
index 2cdab6dc..17df23f 100644
--- a/drivers/common/cnxk/roc_nix_inl_priv.h
+++ b/drivers/common/cnxk/roc_nix_inl_priv.h
@@ -27,9 +27,12 @@ struct nix_inl_dev {
 	uint32_t xaq_buf_size;
 	uint32_t xae_waes;
 	uint32_t iue;
+	uint32_t nb_xae;
 	struct roc_sso_xaq_data xaq;
 	roc_nix_inl_sso_work_cb_t work_cb;
 	void *cb_args;
+	uint64_t *pkt_pools;
+	uint16_t pkt_pools_cnt;
 
 	/* NIX data */
 	uint8_t lf_tx_stats;
diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h
index adfb88c..3b10bfb 100644
--- a/drivers/common/cnxk/roc_platform.h
+++ b/drivers/common/cnxk/roc_platform.h
@@ -148,6 +148,7 @@
 #define plt_intr_handle rte_intr_handle
 
 #define plt_zmalloc(sz, align) rte_zmalloc("cnxk", sz, align)
+#define plt_realloc	       rte_realloc
 #define plt_free	       rte_free
 
 #define plt_read64(addr) rte_read64_relaxed((volatile void *)(addr))
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 75a260f..ff3c1e8 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -133,11 +133,12 @@ INTERNAL {
 	roc_nix_inl_dev_init;
 	roc_nix_inl_dev_is_probed;
 	roc_nix_inl_dev_lock;
-	roc_nix_inl_dev_unlock;
 	roc_nix_inl_dev_rq;
 	roc_nix_inl_dev_rq_get;
 	roc_nix_inl_dev_rq_put;
 	roc_nix_inl_dev_rq_limit_get;
+	roc_nix_inl_dev_unlock;
+	roc_nix_inl_dev_xaq_realloc;
 	roc_nix_inl_inb_is_enabled;
 	roc_nix_inl_inb_init;
 	roc_nix_inl_inb_sa_base_get;
-- 
2.8.4

[PATCH v2 03/21] common/cnxk: adjust shaper rates to lower boundaries

[Nithin Dabilpuram]

From: Satha Rao <skoteshwar@marvell.com>

Provide a method to get floor values for a requested shaper rate,
which can assure packets should never be transmitted at a rate higher
than configured.

Keep the old API to get HW suggested values.
And introduce new parameter to select appropriate API.

Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---
 drivers/common/cnxk/roc_nix.h          |  1 +
 drivers/common/cnxk/roc_nix_priv.h     |  4 +-
 drivers/common/cnxk/roc_nix_tm_ops.c   | 10 ++--
 drivers/common/cnxk/roc_nix_tm_utils.c | 90 ++++++++++++++++++++++++++++++++--
 4 files changed, 96 insertions(+), 9 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 755212c..250e1c0 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -531,6 +531,7 @@ struct roc_nix_tm_shaper_profile {
 	uint64_t peak_sz;
 	int32_t pkt_len_adj;
 	bool pkt_mode;
+	int8_t accuracy;
 	/* Function to free this memory */
 	void (*free_fn)(void *profile);
 };
diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h
index 4d2a7d8..ec6f106 100644
--- a/drivers/common/cnxk/roc_nix_priv.h
+++ b/drivers/common/cnxk/roc_nix_priv.h
@@ -95,6 +95,7 @@ struct nix_tm_shaper_profile {
 	int32_t pkt_mode_adj;
 	bool pkt_mode;
 	uint32_t id;
+	int8_t accuracy;
 	void (*free_fn)(void *profile);
 
 	uint32_t ref_cnt;
@@ -399,7 +400,8 @@ uint32_t nix_tm_check_rr(struct nix *nix, uint32_t parent_id,
 			 uint32_t *max_prio);
 uint64_t nix_tm_shaper_profile_rate_min(struct nix *nix);
 uint64_t nix_tm_shaper_rate_conv(uint64_t value, uint64_t *exponent_p,
-				 uint64_t *mantissa_p, uint64_t *div_exp_p);
+				 uint64_t *mantissa_p, uint64_t *div_exp_p,
+				 int8_t accuracy);
 uint64_t nix_tm_shaper_burst_conv(uint64_t value, uint64_t *exponent_p,
 				  uint64_t *mantissa_p);
 bool nix_tm_child_res_valid(struct nix_tm_node_list *list,
diff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c
index 3d81247..a1f5f0e 100644
--- a/drivers/common/cnxk/roc_nix_tm_ops.c
+++ b/drivers/common/cnxk/roc_nix_tm_ops.c
@@ -173,8 +173,8 @@ nix_tm_shaper_profile_add(struct roc_nix *roc_nix,
 	if (commit_rate || commit_sz) {
 		if (commit_sz < min_burst || commit_sz > max_burst)
 			return NIX_ERR_TM_INVALID_COMMIT_SZ;
-		else if (!nix_tm_shaper_rate_conv(commit_rate, NULL, NULL,
-						  NULL))
+		else if (!nix_tm_shaper_rate_conv(commit_rate, NULL, NULL, NULL,
+						  profile->accuracy))
 			return NIX_ERR_TM_INVALID_COMMIT_RATE;
 	}
 
@@ -182,7 +182,8 @@ nix_tm_shaper_profile_add(struct roc_nix *roc_nix,
 	if (peak_sz || peak_rate) {
 		if (peak_sz < min_burst || peak_sz > max_burst)
 			return NIX_ERR_TM_INVALID_PEAK_SZ;
-		else if (!nix_tm_shaper_rate_conv(peak_rate, NULL, NULL, NULL))
+		else if (!nix_tm_shaper_rate_conv(peak_rate, NULL, NULL, NULL,
+						  profile->accuracy))
 			return NIX_ERR_TM_INVALID_PEAK_RATE;
 	}
 
@@ -230,6 +231,7 @@ roc_nix_tm_shaper_profile_add(struct roc_nix *roc_nix,
 	profile->pkt_len_adj = roc_profile->pkt_len_adj;
 	profile->pkt_mode = roc_profile->pkt_mode;
 	profile->free_fn = roc_profile->free_fn;
+	profile->accuracy = roc_profile->accuracy;
 
 	return nix_tm_shaper_profile_add(roc_nix, profile, 0);
 }
@@ -246,6 +248,8 @@ roc_nix_tm_shaper_profile_update(struct roc_nix *roc_nix,
 	profile->peak.rate = roc_profile->peak_rate;
 	profile->commit.size = roc_profile->commit_sz;
 	profile->peak.size = roc_profile->peak_sz;
+	profile->pkt_len_adj = roc_profile->pkt_len_adj;
+	profile->accuracy = roc_profile->accuracy;
 
 	return nix_tm_shaper_profile_add(roc_nix, profile, 1);
 }
diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c
index 9e80c2a..bcdf990 100644
--- a/drivers/common/cnxk/roc_nix_tm_utils.c
+++ b/drivers/common/cnxk/roc_nix_tm_utils.c
@@ -125,9 +125,72 @@ nix_tm_node_search(struct nix *nix, uint32_t node_id, enum roc_nix_tm_tree tree)
 	return NULL;
 }
 
-uint64_t
-nix_tm_shaper_rate_conv(uint64_t value, uint64_t *exponent_p,
-			uint64_t *mantissa_p, uint64_t *div_exp_p)
+static uint64_t
+nix_tm_shaper_rate_conv_floor(uint64_t value, uint64_t *exponent_p,
+			      uint64_t *mantissa_p, uint64_t *div_exp_p)
+{
+	uint64_t div_exp, exponent, mantissa;
+
+	/* Boundary checks */
+	if (value < NIX_TM_MIN_SHAPER_RATE || value > NIX_TM_MAX_SHAPER_RATE)
+		return 0;
+
+	if (value <= NIX_TM_SHAPER_RATE(0, 0, 0)) {
+		/* Calculate rate div_exp and mantissa using
+		 * the following formula:
+		 *
+		 * value = (2E6 * (256 + mantissa)
+		 *              / ((1 << div_exp) * 256))
+		 */
+		div_exp = 0;
+		exponent = 0;
+		mantissa = NIX_TM_MAX_RATE_MANTISSA;
+
+		while (value <= (NIX_TM_SHAPER_RATE_CONST / (1 << div_exp)))
+			div_exp += 1;
+
+		while (value <= ((NIX_TM_SHAPER_RATE_CONST * (256 + mantissa)) /
+				 ((1 << div_exp) * 256)))
+			mantissa -= 1;
+	} else {
+		/* Calculate rate exponent and mantissa using
+		 * the following formula:
+		 *
+		 * value = (2E6 * ((256 + mantissa) << exponent)) / 256
+		 *
+		 */
+		div_exp = 0;
+		exponent = NIX_TM_MAX_RATE_EXPONENT;
+		mantissa = NIX_TM_MAX_RATE_MANTISSA;
+
+		while (value <= (NIX_TM_SHAPER_RATE_CONST * (1 << exponent)))
+			exponent -= 1;
+
+		while (value <= ((NIX_TM_SHAPER_RATE_CONST *
+				  ((256 + mantissa) << exponent)) /
+				 256))
+			mantissa -= 1;
+	}
+
+	if (div_exp > NIX_TM_MAX_RATE_DIV_EXP ||
+	    exponent > NIX_TM_MAX_RATE_EXPONENT ||
+	    mantissa > NIX_TM_MAX_RATE_MANTISSA)
+		return 0;
+
+	if (div_exp_p)
+		*div_exp_p = div_exp;
+	if (exponent_p)
+		*exponent_p = exponent;
+	if (mantissa_p)
+		*mantissa_p = mantissa;
+
+	/* Calculate real rate value */
+	return NIX_TM_SHAPER_RATE(exponent, mantissa, div_exp);
+}
+
+static uint64_t
+nix_tm_shaper_rate_conv_exact(uint64_t value, uint64_t *exponent_p,
+			      uint64_t *mantissa_p, uint64_t *div_exp_p)
 {
 	uint64_t div_exp, exponent, mantissa;
 
@@ -188,6 +251,23 @@ nix_tm_shaper_rate_conv(uint64_t value, uint64_t *exponent_p,
 	return NIX_TM_SHAPER_RATE(exponent, mantissa, div_exp);
 }
 
+/* With zero accuracy we will tune parameters as defined by HW,
+ * non zero accuracy will keep the parameters close to lower values
+ * and make sure long-term shaper rate will not exceed the requested rate.
+ */
+uint64_t
+nix_tm_shaper_rate_conv(uint64_t value, uint64_t *exponent_p,
+			uint64_t *mantissa_p, uint64_t *div_exp_p,
+			int8_t accuracy)
+{
+	if (!accuracy)
+		return nix_tm_shaper_rate_conv_exact(value, exponent_p,
+						     mantissa_p, div_exp_p);
+
+	return nix_tm_shaper_rate_conv_floor(value, exponent_p, mantissa_p,
+					     div_exp_p);
+}
+
 uint64_t
 nix_tm_shaper_burst_conv(uint64_t value, uint64_t *exponent_p,
 			 uint64_t *mantissa_p)
@@ -245,13 +325,13 @@ nix_tm_shaper_conf_get(struct nix_tm_shaper_profile *profile,
 	if (profile->commit.rate)
 		cir->rate = nix_tm_shaper_rate_conv(
 			profile->commit.rate, &cir->exponent, &cir->mantissa,
-			&cir->div_exp);
+			&cir->div_exp, profile->accuracy);
 
 	/* Calculate PIR exponent and mantissa */
 	if (profile->peak.rate)
 		pir->rate = nix_tm_shaper_rate_conv(
 			profile->peak.rate, &pir->exponent, &pir->mantissa,
-			&pir->div_exp);
+			&pir->div_exp, profile->accuracy);
 
 	/* Calculate CIR burst exponent and mantissa */
 	if (profile->commit.size)
-- 
2.8.4

[PATCH v2 04/21] common/cnxk: support inline device API without ROC NIX

[Nithin Dabilpuram]

From: Vidya Sagar Velumuri <vvelumuri@marvell.com>

Update the inline device functions to work when roc_nix is NULL.
This is required, as IPsec driver have to use these APIs to work
with inline IPsec device, but the IPsec driver might not have roc_nix
information.

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
---
 drivers/common/cnxk/roc_nix_inl.c      | 98 ++++++++++++++++++++++++----------
 drivers/common/cnxk/roc_nix_inl.h      |  2 +
 drivers/common/cnxk/roc_nix_inl_dev.c  |  7 +++
 drivers/common/cnxk/roc_nix_inl_priv.h |  1 +
 drivers/common/cnxk/version.map        |  1 +
 drivers/net/cnxk/cnxk_ethdev_sec.c     |  2 +
 6 files changed, 84 insertions(+), 27 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index e8981c4..356d11d 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -107,18 +107,24 @@ roc_nix_inl_outb_sa_base_get(struct roc_nix *roc_nix)
 uintptr_t
 roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix, bool inb_inl_dev)
 {
-	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
 	struct idev_cfg *idev = idev_get_cfg();
 	struct nix_inl_dev *inl_dev;
+	struct nix *nix = NULL;
 
 	if (idev == NULL)
 		return 0;
 
-	if (!nix->inl_inb_ena)
-		return 0;
+	if (!inb_inl_dev && roc_nix == NULL)
+		return -EINVAL;
+
+	if (roc_nix) {
+		nix = roc_nix_to_nix_priv(roc_nix);
+		if (!nix->inl_inb_ena)
+			return 0;
+	}
 
-	inl_dev = idev->nix_inl_dev;
 	if (inb_inl_dev) {
+		inl_dev = idev->nix_inl_dev;
 		/* Return inline dev sa base */
 		if (inl_dev)
 			return (uintptr_t)inl_dev->inb_sa_base;
@@ -131,18 +137,24 @@ roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix, bool inb_inl_dev)
 uint32_t
 roc_nix_inl_inb_sa_max_spi(struct roc_nix *roc_nix, bool inb_inl_dev)
 {
-	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
 	struct idev_cfg *idev = idev_get_cfg();
 	struct nix_inl_dev *inl_dev;
+	struct nix *nix;
 
 	if (idev == NULL)
 		return 0;
 
-	if (!nix->inl_inb_ena)
-		return 0;
+	if (!inb_inl_dev && roc_nix == NULL)
+		return -EINVAL;
+
+	if (roc_nix) {
+		nix = roc_nix_to_nix_priv(roc_nix);
+		if (!nix->inl_inb_ena)
+			return 0;
+	}
 
-	inl_dev = idev->nix_inl_dev;
 	if (inb_inl_dev) {
+		inl_dev = idev->nix_inl_dev;
 		if (inl_dev)
 			return inl_dev->ipsec_in_max_spi;
 		return 0;
@@ -154,21 +166,28 @@ roc_nix_inl_inb_sa_max_spi(struct roc_nix *roc_nix, bool inb_inl_dev)
 uint32_t
 roc_nix_inl_inb_sa_sz(struct roc_nix *roc_nix, bool inl_dev_sa)
 {
-	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
 	struct idev_cfg *idev = idev_get_cfg();
 	struct nix_inl_dev *inl_dev;
+	struct nix *nix;
 
 	if (idev == NULL)
 		return 0;
 
-	if (!inl_dev_sa)
-		return nix->inb_sa_sz;
+	if (!inl_dev_sa && roc_nix == NULL)
+		return -EINVAL;
 
-	inl_dev = idev->nix_inl_dev;
-	if (inl_dev_sa && inl_dev)
-		return inl_dev->inb_sa_sz;
+	if (roc_nix) {
+		nix = roc_nix_to_nix_priv(roc_nix);
+		if (!inl_dev_sa)
+			return nix->inb_sa_sz;
+	}
+
+	if (inl_dev_sa) {
+		inl_dev = idev->nix_inl_dev;
+		if (inl_dev)
+			return inl_dev->inb_sa_sz;
+	}
 
-	/* On error */
 	return 0;
 }
 
@@ -536,7 +555,7 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq)
 	inl_rq->tag_mask = 0xFFF00000;
 	inl_rq->tt = SSO_TT_ORDERED;
 	inl_rq->hwgrp = 0;
-	inl_rq->wqe_skip = 1;
+	inl_rq->wqe_skip = inl_dev->wqe_skip;
 	inl_rq->sso_ena = true;
 
 	/* Prepare and send RQ init mbox */
@@ -731,13 +750,14 @@ int
 roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa, bool inb,
 		    enum roc_nix_inl_sa_sync_op op)
 {
-	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
-	struct roc_cpt_lf *outb_lf = nix->cpt_lf_base;
 	struct idev_cfg *idev = idev_get_cfg();
 	struct nix_inl_dev *inl_dev = NULL;
+	struct roc_cpt_lf *outb_lf = NULL;
 	union cpt_lf_ctx_reload reload;
 	union cpt_lf_ctx_flush flush;
+	bool get_inl_lf = true;
 	uintptr_t rbase;
+	struct nix *nix;
 
 	/* Nothing much to do on cn9k */
 	if (roc_model_is_cn9k()) {
@@ -745,11 +765,22 @@ roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa, bool inb,
 		return 0;
 	}
 
-	if (inb && nix->inb_inl_dev) {
+	if (idev)
+		inl_dev = idev->nix_inl_dev;
+
+	if (!inl_dev && roc_nix == NULL)
+		return -EINVAL;
+
+	if (roc_nix) {
+		nix = roc_nix_to_nix_priv(roc_nix);
+		outb_lf = nix->cpt_lf_base;
+		if (inb && !nix->inb_inl_dev)
+			get_inl_lf = false;
+	}
+
+	if (inb && get_inl_lf) {
 		outb_lf = NULL;
-		if (idev)
-			inl_dev = idev->nix_inl_dev;
-		if (inl_dev)
+		if (inl_dev && inl_dev->attach_cptlf)
 			outb_lf = &inl_dev->cpt_lf;
 	}
 
@@ -783,12 +814,13 @@ int
 roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, void *sa_cptr,
 		      bool inb, uint16_t sa_len)
 {
-	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
-	struct roc_cpt_lf *outb_lf = nix->cpt_lf_base;
 	struct idev_cfg *idev = idev_get_cfg();
 	struct nix_inl_dev *inl_dev = NULL;
+	struct roc_cpt_lf *outb_lf = NULL;
 	union cpt_lf_ctx_flush flush;
+	bool get_inl_lf = true;
 	uintptr_t rbase;
+	struct nix *nix;
 	int rc;
 
 	/* Nothing much to do on cn9k */
@@ -797,10 +829,22 @@ roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, void *sa_cptr,
 		return 0;
 	}
 
-	if (inb && nix->inb_inl_dev) {
+	if (idev)
+		inl_dev = idev->nix_inl_dev;
+
+	if (!inl_dev && roc_nix == NULL)
+		return -EINVAL;
+
+	if (roc_nix) {
+		nix = roc_nix_to_nix_priv(roc_nix);
+		outb_lf = nix->cpt_lf_base;
+
+		if (inb && !nix->inb_inl_dev)
+			get_inl_lf = false;
+	}
+
+	if (inb && get_inl_lf) {
 		outb_lf = NULL;
-		if (idev)
-			inl_dev = idev->nix_inl_dev;
 		if (inl_dev && inl_dev->attach_cptlf)
 			outb_lf = &inl_dev->cpt_lf;
 	}
diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h
index bbdcbc8..ceeccab 100644
--- a/drivers/common/cnxk/roc_nix_inl.h
+++ b/drivers/common/cnxk/roc_nix_inl.h
@@ -111,6 +111,7 @@ struct roc_nix_inl_dev {
 	uint16_t channel;
 	uint16_t chan_mask;
 	bool attach_cptlf;
+	bool wqe_skip;
 	/* End of input parameters */
 
 #define ROC_NIX_INL_MEM_SZ (1280)
@@ -125,6 +126,7 @@ bool __roc_api roc_nix_inl_dev_is_probed(void);
 void __roc_api roc_nix_inl_dev_lock(void);
 void __roc_api roc_nix_inl_dev_unlock(void);
 int __roc_api roc_nix_inl_dev_xaq_realloc(uint64_t aura_handle);
+uint16_t __roc_api roc_nix_inl_dev_pffunc_get(void);
 
 /* NIX Inline Inbound API */
 int __roc_api roc_nix_inl_inb_init(struct roc_nix *roc_nix);
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c
index 1d14f04..12160e9 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -27,6 +27,12 @@ nix_inl_dev_pffunc_get(void)
 	return 0;
 }
 
+uint16_t
+roc_nix_inl_dev_pffunc_get(void)
+{
+	return nix_inl_dev_pffunc_get();
+}
+
 static void
 nix_inl_selftest_work_cb(uint64_t *gw, void *args)
 {
@@ -655,6 +661,7 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)
 	inl_dev->channel = roc_inl_dev->channel;
 	inl_dev->chan_mask = roc_inl_dev->chan_mask;
 	inl_dev->attach_cptlf = roc_inl_dev->attach_cptlf;
+	inl_dev->wqe_skip = roc_inl_dev->wqe_skip;
 
 	/* Initialize base device */
 	rc = dev_init(&inl_dev->dev, pci_dev);
diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h
index 17df23f..dcf752e 100644
--- a/drivers/common/cnxk/roc_nix_inl_priv.h
+++ b/drivers/common/cnxk/roc_nix_inl_priv.h
@@ -58,6 +58,7 @@ struct nix_inl_dev {
 	bool is_multi_channel;
 	uint16_t ipsec_in_max_spi;
 	bool attach_cptlf;
+	bool wqe_skip;
 };
 
 int nix_inl_sso_register_irqs(struct nix_inl_dev *inl_dev);
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index ff3c1e8..464df44 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -157,6 +157,7 @@ INTERNAL {
 	roc_nix_inl_outb_is_enabled;
 	roc_nix_inl_sa_sync;
 	roc_nix_inl_ctx_write;
+	roc_nix_inl_dev_pffunc_get;
 	roc_nix_inl_inb_sa_init;
 	roc_nix_inl_outb_sa_init;
 	roc_nix_cpt_ctx_cache_sync;
diff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c
index 3fef056..ea204ca 100644
--- a/drivers/net/cnxk/cnxk_ethdev_sec.c
+++ b/drivers/net/cnxk/cnxk_ethdev_sec.c
@@ -278,6 +278,8 @@ cnxk_nix_inl_dev_probe(struct rte_pci_driver *pci_drv,
 	}
 
 	inl_dev->attach_cptlf = true;
+	/* WQE skip is one for DPDK */
+	inl_dev->wqe_skip = true;
 	rc = roc_nix_inl_dev_init(inl_dev);
 	if (rc) {
 		plt_err("Failed to init nix inl device, rc=%d(%s)", rc,
-- 
2.8.4

[PATCH v2 05/21] common/cnxk: use common SA init API for default options

[Nithin Dabilpuram]

From: Vidya Sagar Velumuri <vvelumuri@marvell.com>

Use common SA init API before doing initialization based on
params. This is better so that all HW specific default values
are at single place for lookaside and inline.

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/common/cnxk/cnxk_security.c   | 21 +++++++-----------
 drivers/common/cnxk/cnxk_security.h   |  3 ++-
 drivers/common/cnxk/meson.build       |  1 +
 drivers/common/cnxk/roc_ie_ot.c       | 41 +++++++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_ie_ot.h       | 11 ++++++----
 drivers/common/cnxk/roc_nix_inl.c     | 31 ++------------------------
 drivers/common/cnxk/roc_nix_inl.h     |  2 --
 drivers/common/cnxk/roc_nix_inl_dev.c |  2 +-
 drivers/common/cnxk/version.map       |  4 ++--
 drivers/crypto/cnxk/cn10k_ipsec.c     |  3 ++-
 drivers/net/cnxk/cn10k_ethdev_sec.c   |  7 +++---
 11 files changed, 70 insertions(+), 56 deletions(-)
 create mode 100644 drivers/common/cnxk/roc_ie_ot.c

diff --git a/drivers/common/cnxk/cnxk_security.c b/drivers/common/cnxk/cnxk_security.c
index 6ddf589..d6006d3 100644
--- a/drivers/common/cnxk/cnxk_security.c
+++ b/drivers/common/cnxk/cnxk_security.c
@@ -304,13 +304,17 @@ ot_ipsec_inb_tunnel_hdr_fill(struct roc_ot_ipsec_inb_sa *sa,
 int
 cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa,
 			  struct rte_security_ipsec_xform *ipsec_xfrm,
-			  struct rte_crypto_sym_xform *crypto_xfrm)
+			  struct rte_crypto_sym_xform *crypto_xfrm,
+			  bool is_inline)
 {
 	union roc_ot_ipsec_sa_word2 w2;
 	uint32_t replay_win_sz;
 	size_t offset;
 	int rc;
 
+	/* Initialize the SA */
+	roc_ot_ipsec_inb_sa_init(sa, is_inline);
+
 	w2.u64 = 0;
 	rc = ot_ipsec_sa_common_param_fill(&w2, sa->cipher_key, sa->w8.s.salt,
 					   sa->hmac_opad_ipad, ipsec_xfrm,
@@ -335,13 +339,6 @@ cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa,
 	if (rc)
 		return rc;
 
-	/* Default options for pkt_out and pkt_fmt are with
-	 * second pass meta and no defrag.
-	 */
-	sa->w0.s.pkt_format = ROC_IE_OT_SA_PKT_FMT_META;
-	sa->w0.s.pkt_output = ROC_IE_OT_SA_PKT_OUTPUT_HW_BASED_DEFRAG;
-	sa->w0.s.pkind = ROC_OT_CPT_META_PKIND;
-
 	/* ESN */
 	sa->w2.s.esn_en = !!ipsec_xfrm->options.esn;
 	if (ipsec_xfrm->options.udp_encap) {
@@ -390,11 +387,6 @@ cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa,
 		sa->w0.s.hard_life_dec = 1;
 	}
 
-	/* There are two words of CPT_CTX_HW_S for ucode to skip */
-	sa->w0.s.ctx_hdr_size = 1;
-	sa->w0.s.aop_valid = 1;
-	sa->w0.s.et_ovrwr = 1;
-
 	rte_wmb();
 
 	/* Enable SA */
@@ -412,6 +404,9 @@ cnxk_ot_ipsec_outb_sa_fill(struct roc_ot_ipsec_outb_sa *sa,
 	size_t offset;
 	int rc;
 
+	/* Initialize the SA */
+	roc_ot_ipsec_outb_sa_init(sa);
+
 	w2.u64 = 0;
 	rc = ot_ipsec_sa_common_param_fill(&w2, sa->cipher_key, sa->iv.s.salt,
 					   sa->hmac_opad_ipad, ipsec_xfrm,
diff --git a/drivers/common/cnxk/cnxk_security.h b/drivers/common/cnxk/cnxk_security.h
index db97887..02cdad2 100644
--- a/drivers/common/cnxk/cnxk_security.h
+++ b/drivers/common/cnxk/cnxk_security.h
@@ -38,7 +38,8 @@ cnxk_ipsec_outb_roundup_byte(enum rte_crypto_cipher_algorithm c_algo,
 int __roc_api
 cnxk_ot_ipsec_inb_sa_fill(struct roc_ot_ipsec_inb_sa *sa,
 			  struct rte_security_ipsec_xform *ipsec_xfrm,
-			  struct rte_crypto_sym_xform *crypto_xfrm);
+			  struct rte_crypto_sym_xform *crypto_xfrm,
+			  bool is_inline);
 int __roc_api
 cnxk_ot_ipsec_outb_sa_fill(struct roc_ot_ipsec_outb_sa *sa,
 			   struct rte_security_ipsec_xform *ipsec_xfrm,
diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index f0721ef..2834846 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -24,6 +24,7 @@ sources = files(
         'roc_hash.c',
         'roc_idev.c',
         'roc_irq.c',
+        'roc_ie_ot.c',
         'roc_mbox.c',
         'roc_model.c',
         'roc_nix.c',
diff --git a/drivers/common/cnxk/roc_ie_ot.c b/drivers/common/cnxk/roc_ie_ot.c
new file mode 100644
index 0000000..1ea7bfd
--- /dev/null
+++ b/drivers/common/cnxk/roc_ie_ot.c
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2022 Marvell.
+ */
+
+#include "roc_api.h"
+#include "roc_priv.h"
+
+void
+roc_ot_ipsec_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa, bool is_inline)
+{
+	size_t offset;
+
+	memset(sa, 0, sizeof(struct roc_ot_ipsec_inb_sa));
+
+	if (is_inline) {
+		sa->w0.s.pkt_output = ROC_IE_OT_SA_PKT_OUTPUT_NO_FRAG;
+		sa->w0.s.pkt_format = ROC_IE_OT_SA_PKT_FMT_META;
+		sa->w0.s.pkind = ROC_IE_OT_CPT_PKIND;
+		sa->w0.s.et_ovrwr = 1;
+	}
+
+	offset = offsetof(struct roc_ot_ipsec_inb_sa, ctx);
+	sa->w0.s.hw_ctx_off = offset / ROC_CTX_UNIT_8B;
+	sa->w0.s.ctx_push_size = sa->w0.s.hw_ctx_off + 1;
+	sa->w0.s.ctx_size = ROC_IE_OT_CTX_ILEN;
+	sa->w0.s.ctx_hdr_size = ROC_IE_OT_SA_CTX_HDR_SIZE;
+	sa->w0.s.aop_valid = 1;
+}
+
+void
+roc_ot_ipsec_outb_sa_init(struct roc_ot_ipsec_outb_sa *sa)
+{
+	size_t offset;
+
+	memset(sa, 0, sizeof(struct roc_ot_ipsec_outb_sa));
+
+	offset = offsetof(struct roc_ot_ipsec_outb_sa, ctx);
+	sa->w0.s.ctx_push_size = (offset / ROC_CTX_UNIT_8B) + 1;
+	sa->w0.s.ctx_size = ROC_IE_OT_CTX_ILEN;
+	sa->w0.s.aop_valid = 1;
+}
diff --git a/drivers/common/cnxk/roc_ie_ot.h b/drivers/common/cnxk/roc_ie_ot.h
index c502c79..b5d4f4a 100644
--- a/drivers/common/cnxk/roc_ie_ot.h
+++ b/drivers/common/cnxk/roc_ie_ot.h
@@ -1,13 +1,10 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(C) 2021 Marvell.
+ * Copyright(C) 2022 Marvell.
  */
 
 #ifndef __ROC_IE_OT_H__
 #define __ROC_IE_OT_H__
 
-/* PKIND to be used for CPT Meta parsing */
-#define ROC_OT_CPT_META_PKIND 58
-
 /* CN10K IPSEC opcodes */
 #define ROC_IE_OT_MAJOR_OP_PROCESS_OUTBOUND_IPSEC 0x28UL
 #define ROC_IE_OT_MAJOR_OP_PROCESS_INBOUND_IPSEC  0x29UL
@@ -16,6 +13,9 @@
 #define ROC_IE_OT_MINOR_OP_WRITE_SA 0x09UL
 
 #define ROC_IE_OT_CTX_ILEN 2
+/* PKIND to be used for CPT Meta parsing */
+#define ROC_IE_OT_CPT_PKIND	  58
+#define ROC_IE_OT_SA_CTX_HDR_SIZE 1
 
 enum roc_ie_ot_ucc_ipsec {
 	ROC_IE_OT_UCC_SUCCESS = 0x00,
@@ -532,4 +532,7 @@ PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, hmac_opad_ipad) ==
 PLT_STATIC_ASSERT(offsetof(struct roc_ot_ipsec_outb_sa, ctx) ==
 		  31 * sizeof(uint64_t));
 
+void __roc_api roc_ot_ipsec_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa,
+					bool is_inline);
+void __roc_api roc_ot_ipsec_outb_sa_init(struct roc_ot_ipsec_outb_sa *sa);
 #endif /* __ROC_IE_OT_H__ */
diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index 356d11d..f57f1a4 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -43,7 +43,7 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
 	if (roc_model_is_cn10k()) {
 		for (i = 0; i < ipsec_in_max_spi; i++) {
 			sa = ((uint8_t *)nix->inb_sa_base) + (i * inb_sa_sz);
-			roc_nix_inl_inb_sa_init(sa);
+			roc_ot_ipsec_inb_sa_init(sa, true);
 		}
 	}
 
@@ -401,7 +401,7 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
 	if (roc_model_is_cn10k()) {
 		for (i = 0; i < roc_nix->ipsec_out_max_sa; i++) {
 			sa = ((uint8_t *)sa_base) + (i * sa_sz);
-			roc_nix_inl_outb_sa_init(sa);
+			roc_ot_ipsec_outb_sa_init(sa);
 		}
 	}
 	nix->outb_sa_base = sa_base;
@@ -867,33 +867,6 @@ roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, void *sa_cptr,
 }
 
 void
-roc_nix_inl_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa)
-{
-	size_t offset;
-
-	memset(sa, 0, sizeof(struct roc_ot_ipsec_inb_sa));
-
-	offset = offsetof(struct roc_ot_ipsec_inb_sa, ctx);
-	sa->w0.s.hw_ctx_off = offset / ROC_CTX_UNIT_8B;
-	sa->w0.s.ctx_push_size = sa->w0.s.hw_ctx_off + 1;
-	sa->w0.s.ctx_size = ROC_IE_OT_CTX_ILEN;
-	sa->w0.s.aop_valid = 1;
-}
-
-void
-roc_nix_inl_outb_sa_init(struct roc_ot_ipsec_outb_sa *sa)
-{
-	size_t offset;
-
-	memset(sa, 0, sizeof(struct roc_ot_ipsec_outb_sa));
-
-	offset = offsetof(struct roc_ot_ipsec_outb_sa, ctx);
-	sa->w0.s.ctx_push_size = (offset / ROC_CTX_UNIT_8B);
-	sa->w0.s.ctx_size = ROC_IE_OT_CTX_ILEN;
-	sa->w0.s.aop_valid = 1;
-}
-
-void
 roc_nix_inl_dev_lock(void)
 {
 	struct idev_cfg *idev = idev_get_cfg();
diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h
index ceeccab..224aaba 100644
--- a/drivers/common/cnxk/roc_nix_inl.h
+++ b/drivers/common/cnxk/roc_nix_inl.h
@@ -171,7 +171,5 @@ int __roc_api roc_nix_inl_sa_sync(struct roc_nix *roc_nix, void *sa, bool inb,
 				  enum roc_nix_inl_sa_sync_op op);
 int __roc_api roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr,
 				    void *sa_cptr, bool inb, uint16_t sa_len);
-void __roc_api roc_nix_inl_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa);
-void __roc_api roc_nix_inl_outb_sa_init(struct roc_ot_ipsec_outb_sa *sa);
 
 #endif /* _ROC_NIX_INL_H_ */
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c
index 12160e9..9dc0a62 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -397,7 +397,7 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev)
 		for (i = 0; i < ipsec_in_max_spi; i++) {
 			sa = ((uint8_t *)inl_dev->inb_sa_base) +
 			     (i * inb_sa_sz);
-			roc_nix_inl_inb_sa_init(sa);
+			roc_ot_ipsec_inb_sa_init(sa, true);
 		}
 	}
 	/* Setup device specific inb SA table */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 464df44..2ce6e2b 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -158,8 +158,6 @@ INTERNAL {
 	roc_nix_inl_sa_sync;
 	roc_nix_inl_ctx_write;
 	roc_nix_inl_dev_pffunc_get;
-	roc_nix_inl_inb_sa_init;
-	roc_nix_inl_outb_sa_init;
 	roc_nix_cpt_ctx_cache_sync;
 	roc_nix_is_lbk;
 	roc_nix_is_pf;
@@ -324,6 +322,8 @@ INTERNAL {
 	roc_npc_mcam_read_counter;
 	roc_npc_profile_name_get;
 	roc_npc_validate_portid_action;
+	roc_ot_ipsec_inb_sa_init;
+	roc_ot_ipsec_outb_sa_init;
 	roc_plt_init;
 	roc_plt_init_cb_register;
 	roc_sso_dev_fini;
diff --git a/drivers/crypto/cnxk/cn10k_ipsec.c b/drivers/crypto/cnxk/cn10k_ipsec.c
index c95c57a..847e1d0 100644
--- a/drivers/crypto/cnxk/cn10k_ipsec.c
+++ b/drivers/crypto/cnxk/cn10k_ipsec.c
@@ -180,7 +180,8 @@ cn10k_ipsec_inb_sa_create(struct roc_cpt *roc_cpt, struct roc_cpt_lf *lf,
 	}
 
 	/* Translate security parameters to SA */
-	ret = cnxk_ot_ipsec_inb_sa_fill(sa_dptr, ipsec_xfrm, crypto_xfrm);
+	ret = cnxk_ot_ipsec_inb_sa_fill(sa_dptr, ipsec_xfrm, crypto_xfrm,
+					false);
 	if (ret) {
 		plt_err("Could not fill inbound session parameters");
 		goto sa_dptr_free;
diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c
index 12cec0a..6fbf444 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -319,7 +319,8 @@ cn10k_eth_sec_session_create(void *device,
 		memset(inb_sa_dptr, 0, sizeof(struct roc_ot_ipsec_inb_sa));
 
 		/* Fill inbound sa params */
-		rc = cnxk_ot_ipsec_inb_sa_fill(inb_sa_dptr, ipsec, crypto);
+		rc = cnxk_ot_ipsec_inb_sa_fill(inb_sa_dptr, ipsec, crypto,
+					       true);
 		if (rc) {
 			snprintf(tbuf, sizeof(tbuf),
 				 "Failed to init inbound sa, rc=%d", rc);
@@ -464,7 +465,7 @@ cn10k_eth_sec_session_destroy(void *device, struct rte_security_session *sess)
 	if (eth_sec->inb) {
 		/* Disable SA */
 		sa_dptr = dev->inb.sa_dptr;
-		roc_nix_inl_inb_sa_init(sa_dptr);
+		roc_ot_ipsec_inb_sa_init(sa_dptr, true);
 
 		roc_nix_inl_ctx_write(&dev->nix, sa_dptr, eth_sec->sa,
 				      eth_sec->inb,
@@ -474,7 +475,7 @@ cn10k_eth_sec_session_destroy(void *device, struct rte_security_session *sess)
 	} else {
 		/* Disable SA */
 		sa_dptr = dev->outb.sa_dptr;
-		roc_nix_inl_outb_sa_init(sa_dptr);
+		roc_ot_ipsec_outb_sa_init(sa_dptr);
 
 		roc_nix_inl_ctx_write(&dev->nix, sa_dptr, eth_sec->sa,
 				      eth_sec->inb,
-- 
2.8.4

[PATCH v2 06/21] common/cnxk: enable l3hdr write back in SA

[Nithin Dabilpuram]

From: Vidya Sagar Velumuri <vvelumuri@marvell.com>

Enable the field in SA to write back l2, l3 hdrs in case of errors
during inline processing.

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
---
 drivers/common/cnxk/roc_ie_ot.c | 1 +
 drivers/common/cnxk/roc_ie_ot.h | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/roc_ie_ot.c b/drivers/common/cnxk/roc_ie_ot.c
index 1ea7bfd..d0b7ad3 100644
--- a/drivers/common/cnxk/roc_ie_ot.c
+++ b/drivers/common/cnxk/roc_ie_ot.c
@@ -17,6 +17,7 @@ roc_ot_ipsec_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa, bool is_inline)
 		sa->w0.s.pkt_format = ROC_IE_OT_SA_PKT_FMT_META;
 		sa->w0.s.pkind = ROC_IE_OT_CPT_PKIND;
 		sa->w0.s.et_ovrwr = 1;
+		sa->w2.s.l3hdr_on_err = 1;
 	}
 
 	offset = offsetof(struct roc_ot_ipsec_inb_sa, ctx);
diff --git a/drivers/common/cnxk/roc_ie_ot.h b/drivers/common/cnxk/roc_ie_ot.h
index b5d4f4a..202e2d2 100644
--- a/drivers/common/cnxk/roc_ie_ot.h
+++ b/drivers/common/cnxk/roc_ie_ot.h
@@ -351,7 +351,8 @@ struct roc_ot_ipsec_inb_sa {
 			uint64_t ip_hdr_verify : 2;
 			uint64_t udp_ports_verify : 1;
 
-			uint64_t rsvd6 : 7;
+			uint64_t l3hdr_on_err : 1;
+			uint64_t rsvd6 : 6;
 			uint64_t async_mode : 1;
 
 			uint64_t spi : 32;
-- 
2.8.4

[PATCH v2 07/21] common/cnxk: support to enable AURA tail drop for RQ

[Nithin Dabilpuram]

Add support to enable AURA tail drop via RQ specifically
for inline device RQ's pkt pool. This is better than RQ
RED drop as it can be applied to all RQ's that are not
having security enabled but using same packet pool.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/common/cnxk/roc_nix.h          |  4 ++++
 drivers/common/cnxk/roc_nix_inl.c      | 39 ++++++++++++++++++++++++++++++----
 drivers/common/cnxk/roc_nix_inl.h      |  2 ++
 drivers/common/cnxk/roc_nix_inl_dev.c  |  9 ++++++++
 drivers/common/cnxk/roc_nix_inl_priv.h |  2 ++
 drivers/common/cnxk/roc_nix_queue.c    |  6 +++++-
 drivers/common/cnxk/roc_npa.c          | 33 ++++++++++++++++++++++++++--
 drivers/common/cnxk/roc_npa.h          |  3 +++
 drivers/common/cnxk/version.map        |  1 +
 9 files changed, 92 insertions(+), 7 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 250e1c0..0122b98 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -286,6 +286,10 @@ struct roc_nix_rq {
 	uint8_t spb_red_drop;
 	/* Average SPB aura level pass threshold for RED */
 	uint8_t spb_red_pass;
+	/* LPB aura drop enable */
+	bool lpb_drop_ena;
+	/* SPB aura drop enable */
+	bool spb_drop_ena;
 	/* End of Input parameters */
 	struct roc_nix *roc_nix;
 	bool inl_dev_ref;
diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index f57f1a4..ac17e95 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -528,23 +528,50 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq)
 	inl_rq->first_skip = rq->first_skip;
 	inl_rq->later_skip = rq->later_skip;
 	inl_rq->lpb_size = rq->lpb_size;
+	inl_rq->lpb_drop_ena = true;
+	inl_rq->spb_ena = rq->spb_ena;
+	inl_rq->spb_aura_handle = rq->spb_aura_handle;
+	inl_rq->spb_size = rq->spb_size;
+	inl_rq->spb_drop_ena = !!rq->spb_ena;
 
 	if (!roc_model_is_cn9k()) {
 		uint64_t aura_limit =
 			roc_npa_aura_op_limit_get(inl_rq->aura_handle);
 		uint64_t aura_shift = plt_log2_u32(aura_limit);
+		uint64_t aura_drop, drop_pc;
 
 		if (aura_shift < 8)
 			aura_shift = 0;
 		else
 			aura_shift = aura_shift - 8;
 
-		/* Set first pass RQ to drop when half of the buffers are in
+		/* Set first pass RQ to drop after part of buffers are in
 		 * use to avoid metabuf alloc failure. This is needed as long
-		 * as we cannot use different
+		 * as we cannot use different aura.
 		 */
-		inl_rq->red_pass = (aura_limit / 2) >> aura_shift;
-		inl_rq->red_drop = ((aura_limit / 2) - 1) >> aura_shift;
+		drop_pc = inl_dev->lpb_drop_pc;
+		aura_drop = ((aura_limit * drop_pc) / 100) >> aura_shift;
+		roc_npa_aura_drop_set(inl_rq->aura_handle, aura_drop, true);
+	}
+
+	if (inl_rq->spb_ena) {
+		uint64_t aura_limit =
+			roc_npa_aura_op_limit_get(inl_rq->spb_aura_handle);
+		uint64_t aura_shift = plt_log2_u32(aura_limit);
+		uint64_t aura_drop, drop_pc;
+
+		if (aura_shift < 8)
+			aura_shift = 0;
+		else
+			aura_shift = aura_shift - 8;
+
+		/* Set first pass RQ to drop after part of buffers are in
+		 * use to avoid metabuf alloc failure. This is needed as long
+		 * as we cannot use different aura.
+		 */
+		drop_pc = inl_dev->spb_drop_pc;
+		aura_drop = ((aura_limit * drop_pc) / 100) >> aura_shift;
+		roc_npa_aura_drop_set(inl_rq->spb_aura_handle, aura_drop, true);
 	}
 
 	/* Enable IPSec */
@@ -613,6 +640,10 @@ roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq)
 	if (rc)
 		plt_err("Failed to disable inline device rq, rc=%d", rc);
 
+	roc_npa_aura_drop_set(inl_rq->aura_handle, 0, false);
+	if (inl_rq->spb_ena)
+		roc_npa_aura_drop_set(inl_rq->spb_aura_handle, 0, false);
+
 	/* Flush NIX LF for CN10K */
 	nix_rq_vwqe_flush(rq, inl_dev->vwqe_interval);
 
diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h
index 224aaba..728225b 100644
--- a/drivers/common/cnxk/roc_nix_inl.h
+++ b/drivers/common/cnxk/roc_nix_inl.h
@@ -112,6 +112,8 @@ struct roc_nix_inl_dev {
 	uint16_t chan_mask;
 	bool attach_cptlf;
 	bool wqe_skip;
+	uint8_t spb_drop_pc;
+	uint8_t lpb_drop_pc;
 	/* End of input parameters */
 
 #define ROC_NIX_INL_MEM_SZ (1280)
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c
index 9dc0a62..4c1d85a 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -5,6 +5,8 @@
 #include "roc_api.h"
 #include "roc_priv.h"
 
+#define NIX_AURA_DROP_PC_DFLT 40
+
 /* Default Rx Config for Inline NIX LF */
 #define NIX_INL_LF_RX_CFG                                                      \
 	(ROC_NIX_LF_RX_CFG_DROP_RE | ROC_NIX_LF_RX_CFG_L2_LEN_ERR |            \
@@ -662,6 +664,13 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)
 	inl_dev->chan_mask = roc_inl_dev->chan_mask;
 	inl_dev->attach_cptlf = roc_inl_dev->attach_cptlf;
 	inl_dev->wqe_skip = roc_inl_dev->wqe_skip;
+	inl_dev->spb_drop_pc = NIX_AURA_DROP_PC_DFLT;
+	inl_dev->lpb_drop_pc = NIX_AURA_DROP_PC_DFLT;
+
+	if (roc_inl_dev->spb_drop_pc)
+		inl_dev->spb_drop_pc = roc_inl_dev->spb_drop_pc;
+	if (roc_inl_dev->lpb_drop_pc)
+		inl_dev->lpb_drop_pc = roc_inl_dev->lpb_drop_pc;
 
 	/* Initialize base device */
 	rc = dev_init(&inl_dev->dev, pci_dev);
diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h
index dcf752e..b6d8602 100644
--- a/drivers/common/cnxk/roc_nix_inl_priv.h
+++ b/drivers/common/cnxk/roc_nix_inl_priv.h
@@ -43,6 +43,8 @@ struct nix_inl_dev {
 	struct roc_nix_rq rq;
 	uint16_t rq_refs;
 	bool is_nix1;
+	uint8_t spb_drop_pc;
+	uint8_t lpb_drop_pc;
 
 	/* NIX/CPT data */
 	void *inb_sa_base;
diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c
index a283d96..7d27185 100644
--- a/drivers/common/cnxk/roc_nix_queue.c
+++ b/drivers/common/cnxk/roc_nix_queue.c
@@ -299,7 +299,9 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,
 	aq->rq.rq_int_ena = 0;
 	/* Many to one reduction */
 	aq->rq.qint_idx = rq->qid % qints;
-	aq->rq.xqe_drop_ena = 1;
+	aq->rq.xqe_drop_ena = 0;
+	aq->rq.lpb_drop_ena = rq->lpb_drop_ena;
+	aq->rq.spb_drop_ena = rq->spb_drop_ena;
 
 	/* If RED enabled, then fill enable for all cases */
 	if (rq->red_pass && (rq->red_pass >= rq->red_drop)) {
@@ -366,6 +368,8 @@ nix_rq_cfg(struct dev *dev, struct roc_nix_rq *rq, uint16_t qints, bool cfg,
 		aq->rq_mask.rq_int_ena = ~aq->rq_mask.rq_int_ena;
 		aq->rq_mask.qint_idx = ~aq->rq_mask.qint_idx;
 		aq->rq_mask.xqe_drop_ena = ~aq->rq_mask.xqe_drop_ena;
+		aq->rq_mask.lpb_drop_ena = ~aq->rq_mask.lpb_drop_ena;
+		aq->rq_mask.spb_drop_ena = ~aq->rq_mask.spb_drop_ena;
 
 		if (rq->red_pass && (rq->red_pass >= rq->red_drop)) {
 			aq->rq_mask.spb_pool_pass = ~aq->rq_mask.spb_pool_pass;
diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c
index 75fc224..1e60f44 100644
--- a/drivers/common/cnxk/roc_npa.c
+++ b/drivers/common/cnxk/roc_npa.c
@@ -193,6 +193,35 @@ roc_npa_pool_op_pc_reset(uint64_t aura_handle)
 	}
 	return 0;
 }
+
+int
+roc_npa_aura_drop_set(uint64_t aura_handle, uint64_t limit, bool ena)
+{
+	struct npa_aq_enq_req *aura_req;
+	struct npa_lf *lf;
+	int rc;
+
+	lf = idev_npa_obj_get();
+	if (lf == NULL)
+		return NPA_ERR_DEVICE_NOT_BOUNDED;
+
+	aura_req = mbox_alloc_msg_npa_aq_enq(lf->mbox);
+	if (aura_req == NULL)
+		return -ENOMEM;
+	aura_req->aura_id = roc_npa_aura_handle_to_aura(aura_handle);
+	aura_req->ctype = NPA_AQ_CTYPE_AURA;
+	aura_req->op = NPA_AQ_INSTOP_WRITE;
+
+	aura_req->aura.aura_drop_ena = ena;
+	aura_req->aura.aura_drop = limit;
+	aura_req->aura_mask.aura_drop_ena =
+		~(aura_req->aura_mask.aura_drop_ena);
+	aura_req->aura_mask.aura_drop = ~(aura_req->aura_mask.aura_drop);
+	rc = mbox_process(lf->mbox);
+
+	return rc;
+}
+
 static inline char *
 npa_stack_memzone_name(struct npa_lf *lf, int pool_id, char *name)
 {
@@ -299,7 +328,7 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size,
 	aura->err_int_ena |= BIT(NPA_AURA_ERR_INT_AURA_ADD_UNDER);
 	aura->err_int_ena |= BIT(NPA_AURA_ERR_INT_AURA_FREE_UNDER);
 	aura->err_int_ena |= BIT(NPA_AURA_ERR_INT_POOL_DIS);
-	aura->avg_con = ROC_NPA_AVG_CONT;
+	aura->avg_con = 0;
 	/* Many to one reduction */
 	aura->err_qint_idx = aura_id % lf->qints;
 
@@ -316,7 +345,7 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size,
 	pool->err_int_ena = BIT(NPA_POOL_ERR_INT_OVFLS);
 	pool->err_int_ena |= BIT(NPA_POOL_ERR_INT_RANGE);
 	pool->err_int_ena |= BIT(NPA_POOL_ERR_INT_PERR);
-	pool->avg_con = ROC_NPA_AVG_CONT;
+	pool->avg_con = 0;
 
 	/* Many to one reduction */
 	pool->err_qint_idx = pool_id % lf->qints;
diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h
index 9f5fe5a..0339876bf 100644
--- a/drivers/common/cnxk/roc_npa.h
+++ b/drivers/common/cnxk/roc_npa.h
@@ -731,4 +731,7 @@ int __roc_api roc_npa_dump(void);
 /* Reset operation performance counter. */
 int __roc_api roc_npa_pool_op_pc_reset(uint64_t aura_handle);
 
+int __roc_api roc_npa_aura_drop_set(uint64_t aura_handle, uint64_t limit,
+				    bool ena);
+
 #endif /* _ROC_NPA_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 2ce6e2b..94c35af 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -286,6 +286,7 @@ INTERNAL {
 	roc_nix_vlan_mcam_entry_write;
 	roc_nix_vlan_strip_vtag_ena_dis;
 	roc_nix_vlan_tpid_set;
+	roc_npa_aura_drop_set;
 	roc_npa_aura_limit_modify;
 	roc_npa_aura_op_range_set;
 	roc_npa_ctx_dump;
-- 
2.8.4

[PATCH v2 08/21] common/cnxk: use SSO time counter threshold for IRQ

[Nithin Dabilpuram]

Enable time counter based threshold for raising SSO
EXE_INT instead of IAQ threshold. Time counter based
threshold helps getting periodic interrupts and process
pkts in burst instead of getting HW to raise an interrupt
for every new work.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/common/cnxk/roc_nix_inl_dev_irq.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/common/cnxk/roc_nix_inl_dev_irq.c b/drivers/common/cnxk/roc_nix_inl_dev_irq.c
index d758e0c..8a0cb74 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev_irq.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev_irq.c
@@ -5,6 +5,8 @@
 #include "roc_api.h"
 #include "roc_priv.h"
 
+#define WORK_LIMIT 1000
+
 static void
 nix_inl_sso_work_cb(struct nix_inl_dev *inl_dev)
 {
@@ -15,6 +17,7 @@ nix_inl_sso_work_cb(struct nix_inl_dev *inl_dev)
 		__uint128_t get_work;
 		uint64_t u64[2];
 	} gw;
+	uint16_t cnt = 0;
 	uint64_t work;
 
 again:
@@ -33,7 +36,9 @@ nix_inl_sso_work_cb(struct nix_inl_dev *inl_dev)
 		else
 			plt_warn("Undelivered inl dev work gw0: %p gw1: %p",
 				 (void *)gw.u64[0], (void *)gw.u64[1]);
-		goto again;
+		cnt++;
+		if (cnt < WORK_LIMIT)
+			goto again;
 	}
 
 	plt_atomic_thread_fence(__ATOMIC_ACQ_REL);
@@ -138,8 +143,10 @@ nix_inl_sso_register_irqs(struct nix_inl_dev *inl_dev)
 	/* Enable hw interrupt */
 	plt_write64(~0ull, sso_base + SSO_LF_GGRP_INT_ENA_W1S);
 
-	/* Setup threshold for work exec interrupt to 1 wqe in IAQ */
-	plt_write64(0x1ull, sso_base + SSO_LF_GGRP_INT_THR);
+	/* Setup threshold for work exec interrupt to 100us timeout
+	 * based on time counter.
+	 */
+	plt_write64(BIT_ULL(63) | 10ULL << 48, sso_base + SSO_LF_GGRP_INT_THR);
 
 	return rc;
 }
-- 
2.8.4

[PATCH v2 09/21] common/cnxk: allow force use of SSO pffunc for outb inline

[Nithin Dabilpuram]

Allow force use of SSO pffunc even when inline dev is available
so that in case driver needs events directly delivered to
event device.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/common/cnxk/roc_nix.h     | 1 +
 drivers/common/cnxk/roc_nix_inl.c | 7 ++++++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 0122b98..57a595f 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -386,6 +386,7 @@ struct roc_nix {
 	uint16_t outb_nb_crypto_qs;
 	uint16_t ipsec_in_max_spi;
 	uint16_t ipsec_out_max_sa;
+	bool ipsec_out_sso_pffunc;
 	/* End of input parameters */
 	/* LMT line base for "Per Core Tx LMT line" mode*/
 	uintptr_t lmt_base;
diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index ac17e95..003f972 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -311,6 +311,10 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
 	/* Retrieve inline device if present */
 	inl_dev = idev->nix_inl_dev;
 	sso_pffunc = inl_dev ? inl_dev->dev.pf_func : idev_sso_pffunc_get();
+	/* Use sso_pffunc if explicitly requested */
+	if (roc_nix->ipsec_out_sso_pffunc)
+		sso_pffunc = idev_sso_pffunc_get();
+
 	if (!sso_pffunc) {
 		plt_err("Failed to setup inline outb, need either "
 			"inline device or sso device");
@@ -328,7 +332,8 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
 	eng_grpmask = (1ULL << ROC_CPT_DFLT_ENG_GRP_SE |
 		       1ULL << ROC_CPT_DFLT_ENG_GRP_SE_IE |
 		       1ULL << ROC_CPT_DFLT_ENG_GRP_AE);
-	rc = cpt_lfs_alloc(dev, eng_grpmask, blkaddr, true);
+	rc = cpt_lfs_alloc(dev, eng_grpmask, blkaddr,
+			   !roc_nix->ipsec_out_sso_pffunc);
 	if (rc) {
 		plt_err("Failed to alloc CPT LF resources, rc=%d", rc);
 		goto lf_detach;
-- 
2.8.4

[PATCH v2 10/21] net/cnxk: added Rx metadata negotiate operation

[Nithin Dabilpuram]

From: Satha Rao <skoteshwar@marvell.com>

Added rx_metadata_negotiate api to enable mark update RX offload.
Removed software logic to enable/disable mark update inside flow
create/destroy APIs.

Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---
 drivers/net/cnxk/cn10k_ethdev.c   | 26 ++++++++++++++++++++++++++
 drivers/net/cnxk/cn10k_rte_flow.c | 20 ++------------------
 drivers/net/cnxk/cn9k_ethdev.c    | 25 +++++++++++++++++++++++++
 drivers/net/cnxk/cn9k_rte_flow.c  | 20 ++------------------
 drivers/net/cnxk/cnxk_ethdev.h    |  1 +
 5 files changed, 56 insertions(+), 36 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c
index 9bb08e1..6bf8275 100644
--- a/drivers/net/cnxk/cn10k_ethdev.c
+++ b/drivers/net/cnxk/cn10k_ethdev.c
@@ -39,6 +39,9 @@ nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
 	if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)
 		flags |= NIX_RX_OFFLOAD_SECURITY_F;
 
+	if (dev->rx_mark_update)
+		flags |= NIX_RX_OFFLOAD_MARK_UPDATE_F;
+
 	return flags;
 }
 
@@ -448,6 +451,27 @@ cn10k_nix_dev_start(struct rte_eth_dev *eth_dev)
 	return 0;
 }
 
+static int
+cn10k_nix_rx_metadata_negotiate(struct rte_eth_dev *eth_dev, uint64_t *features)
+{
+	struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+
+	*features &=
+		(RTE_ETH_RX_METADATA_USER_FLAG | RTE_ETH_RX_METADATA_USER_MARK);
+
+	if (*features) {
+		dev->rx_offload_flags |= NIX_RX_OFFLOAD_MARK_UPDATE_F;
+		dev->rx_mark_update = true;
+	} else {
+		dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_MARK_UPDATE_F;
+		dev->rx_mark_update = false;
+	}
+
+	cn10k_eth_set_rx_function(eth_dev);
+
+	return 0;
+}
+
 /* Update platform specific eth dev ops */
 static void
 nix_eth_dev_ops_override(void)
@@ -467,6 +491,8 @@ nix_eth_dev_ops_override(void)
 	cnxk_eth_dev_ops.dev_ptypes_set = cn10k_nix_ptypes_set;
 	cnxk_eth_dev_ops.timesync_enable = cn10k_nix_timesync_enable;
 	cnxk_eth_dev_ops.timesync_disable = cn10k_nix_timesync_disable;
+	cnxk_eth_dev_ops.rx_metadata_negotiate =
+		cn10k_nix_rx_metadata_negotiate;
 }
 
 static void
diff --git a/drivers/net/cnxk/cn10k_rte_flow.c b/drivers/net/cnxk/cn10k_rte_flow.c
index aed187c..87d5c91 100644
--- a/drivers/net/cnxk/cn10k_rte_flow.c
+++ b/drivers/net/cnxk/cn10k_rte_flow.c
@@ -131,9 +131,9 @@ cn10k_flow_create(struct rte_eth_dev *eth_dev, const struct rte_flow_attr *attr,
 	const struct rte_flow_action *action_rss = NULL;
 	const struct rte_flow_action_meter *mtr = NULL;
 	const struct rte_flow_action *act_q = NULL;
-	int mark_actions = 0, vtag_actions = 0;
 	struct roc_npc *npc = &dev->npc;
 	struct roc_npc_flow *flow;
+	int vtag_actions = 0;
 	uint32_t req_act = 0;
 	int i, rc;
 
@@ -197,13 +197,6 @@ cn10k_flow_create(struct rte_eth_dev *eth_dev, const struct rte_flow_attr *attr,
 			cn10k_mtr_connect(eth_dev, mtr->mtr_id);
 	}
 
-	mark_actions = roc_npc_mark_actions_get(npc);
-
-	if (mark_actions) {
-		dev->rx_offload_flags |= NIX_RX_OFFLOAD_MARK_UPDATE_F;
-		cn10k_eth_set_rx_function(eth_dev);
-	}
-
 	vtag_actions = roc_npc_vtag_actions_get(npc);
 
 	if (vtag_actions) {
@@ -220,20 +213,11 @@ cn10k_flow_destroy(struct rte_eth_dev *eth_dev, struct rte_flow *rte_flow,
 {
 	struct roc_npc_flow *flow = (struct roc_npc_flow *)rte_flow;
 	struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
-	int mark_actions = 0, vtag_actions = 0;
 	struct roc_npc *npc = &dev->npc;
+	int vtag_actions = 0;
 	uint32_t mtr_id;
 	int rc;
 
-	mark_actions = roc_npc_mark_actions_get(npc);
-	if (mark_actions) {
-		mark_actions = roc_npc_mark_actions_sub_return(npc, 1);
-		if (mark_actions == 0) {
-			dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_MARK_UPDATE_F;
-			cn10k_eth_set_rx_function(eth_dev);
-		}
-	}
-
 	vtag_actions = roc_npc_vtag_actions_get(npc);
 	if (vtag_actions) {
 		if (flow->nix_intf == ROC_NPC_INTF_RX) {
diff --git a/drivers/net/cnxk/cn9k_ethdev.c b/drivers/net/cnxk/cn9k_ethdev.c
index 01e3850..40215aa 100644
--- a/drivers/net/cnxk/cn9k_ethdev.c
+++ b/drivers/net/cnxk/cn9k_ethdev.c
@@ -39,6 +39,9 @@ nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
 	if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY)
 		flags |= NIX_RX_OFFLOAD_SECURITY_F;
 
+	if (dev->rx_mark_update)
+		flags |= NIX_RX_OFFLOAD_MARK_UPDATE_F;
+
 	return flags;
 }
 
@@ -447,6 +450,27 @@ cn9k_nix_dev_start(struct rte_eth_dev *eth_dev)
 	return 0;
 }
 
+static int
+cn9k_nix_rx_metadata_negotiate(struct rte_eth_dev *eth_dev, uint64_t *features)
+{
+	struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+
+	*features &=
+		(RTE_ETH_RX_METADATA_USER_FLAG | RTE_ETH_RX_METADATA_USER_MARK);
+
+	if (*features) {
+		dev->rx_offload_flags |= NIX_RX_OFFLOAD_MARK_UPDATE_F;
+		dev->rx_mark_update = true;
+	} else {
+		dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_MARK_UPDATE_F;
+		dev->rx_mark_update = false;
+	}
+
+	cn9k_eth_set_rx_function(eth_dev);
+
+	return 0;
+}
+
 /* Update platform specific eth dev ops */
 static void
 nix_eth_dev_ops_override(void)
@@ -467,6 +491,7 @@ nix_eth_dev_ops_override(void)
 	cnxk_eth_dev_ops.timesync_enable = cn9k_nix_timesync_enable;
 	cnxk_eth_dev_ops.timesync_disable = cn9k_nix_timesync_disable;
 	cnxk_eth_dev_ops.mtr_ops_get = NULL;
+	cnxk_eth_dev_ops.rx_metadata_negotiate = cn9k_nix_rx_metadata_negotiate;
 }
 
 static void
diff --git a/drivers/net/cnxk/cn9k_rte_flow.c b/drivers/net/cnxk/cn9k_rte_flow.c
index 6460672..fa9dd8d 100644
--- a/drivers/net/cnxk/cn9k_rte_flow.c
+++ b/drivers/net/cnxk/cn9k_rte_flow.c
@@ -13,21 +13,14 @@ cn9k_flow_create(struct rte_eth_dev *eth_dev, const struct rte_flow_attr *attr,
 		 struct rte_flow_error *error)
 {
 	struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
-	int mark_actions = 0, vtag_actions = 0;
 	struct roc_npc *npc = &dev->npc;
 	struct roc_npc_flow *flow;
+	int vtag_actions = 0;
 
 	flow = cnxk_flow_create(eth_dev, attr, pattern, actions, error);
 	if (!flow)
 		return NULL;
 
-	mark_actions = roc_npc_mark_actions_get(npc);
-
-	if (mark_actions) {
-		dev->rx_offload_flags |= NIX_RX_OFFLOAD_MARK_UPDATE_F;
-		cn9k_eth_set_rx_function(eth_dev);
-	}
-
 	vtag_actions = roc_npc_vtag_actions_get(npc);
 
 	if (vtag_actions) {
@@ -44,17 +37,8 @@ cn9k_flow_destroy(struct rte_eth_dev *eth_dev, struct rte_flow *rte_flow,
 {
 	struct roc_npc_flow *flow = (struct roc_npc_flow *)rte_flow;
 	struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
-	int mark_actions = 0, vtag_actions = 0;
 	struct roc_npc *npc = &dev->npc;
-
-	mark_actions = roc_npc_mark_actions_get(npc);
-	if (mark_actions) {
-		mark_actions = roc_npc_mark_actions_sub_return(npc, 1);
-		if (mark_actions == 0) {
-			dev->rx_offload_flags &= ~NIX_RX_OFFLOAD_MARK_UPDATE_F;
-			cn9k_eth_set_rx_function(eth_dev);
-		}
-	}
+	int vtag_actions = 0;
 
 	vtag_actions = roc_npc_vtag_actions_get(npc);
 	if (vtag_actions) {
diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h
index ad568c9..991969c 100644
--- a/drivers/net/cnxk/cnxk_ethdev.h
+++ b/drivers/net/cnxk/cnxk_ethdev.h
@@ -339,6 +339,7 @@ struct cnxk_eth_dev {
 	uint8_t ptype_disable;
 	bool scalar_ena;
 	bool ptp_en;
+	bool rx_mark_update; /* Enable/Disable mark update to mbuf */
 
 	/* Pointer back to rte */
 	struct rte_eth_dev *eth_dev;
-- 
2.8.4

[PATCH v2 11/21] common/cnxk: remove tracking of mark actions

[Nithin Dabilpuram]

From: Satha Rao <skoteshwar@marvell.com>

Removed roc NPC APIs which tracks addition and deletion of
mark actions. It was earlier needed to track number of mark
actions added as part of flow rules. If mark actions count
is > 0, then the function pointer for Rx would get updated
to even read mark value from CQE/WQE and populate in mbuf.
Now the same switch is done based on new Rx meta data negotiate
ethdev API.

Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---
 drivers/common/cnxk/roc_npc.c      | 21 ---------------------
 drivers/common/cnxk/roc_npc.h      |  3 ---
 drivers/common/cnxk/roc_npc_priv.h |  1 -
 drivers/common/cnxk/version.map    |  2 --
 4 files changed, 27 deletions(-)

diff --git a/drivers/common/cnxk/roc_npc.c b/drivers/common/cnxk/roc_npc.c
index 34c393f..fc88fd5 100644
--- a/drivers/common/cnxk/roc_npc.c
+++ b/drivers/common/cnxk/roc_npc.c
@@ -174,8 +174,6 @@ roc_npc_init(struct roc_npc *roc_npc)
 	roc_npc->kex_capability = npc_get_kex_capability(npc);
 	roc_npc->rx_parse_nibble = npc->keyx_supp_nmask[NPC_MCAM_RX];
 
-	npc->mark_actions = 0;
-
 	npc->mcam_entries = npc_mcam_tot_entries() >> npc->keyw[NPC_MCAM_RX];
 
 	/* Free, free_rev, live and live_rev entries */
@@ -331,13 +329,11 @@ npc_parse_actions(struct roc_npc *roc_npc, const struct roc_npc_attr *attr,
 			}
 			mark = act_mark->id + 1;
 			req_act |= ROC_NPC_ACTION_TYPE_MARK;
-			npc->mark_actions += 1;
 			break;
 
 		case ROC_NPC_ACTION_TYPE_FLAG:
 			mark = NPC_FLOW_FLAG_VAL;
 			req_act |= ROC_NPC_ACTION_TYPE_FLAG;
-			npc->mark_actions += 1;
 			break;
 
 		case ROC_NPC_ACTION_TYPE_COUNT:
@@ -820,23 +816,6 @@ npc_rss_action_program(struct roc_npc *roc_npc,
 	return 0;
 }
 
-int
-roc_npc_mark_actions_get(struct roc_npc *roc_npc)
-{
-	struct npc *npc = roc_npc_to_npc_priv(roc_npc);
-
-	return npc->mark_actions;
-}
-
-int
-roc_npc_mark_actions_sub_return(struct roc_npc *roc_npc, uint32_t count)
-{
-	struct npc *npc = roc_npc_to_npc_priv(roc_npc);
-
-	npc->mark_actions -= count;
-	return npc->mark_actions;
-}
-
 static int
 npc_vtag_cfg_delete(struct roc_npc *roc_npc, struct roc_npc_flow *flow)
 {
diff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h
index f9e5028..6204139 100644
--- a/drivers/common/cnxk/roc_npc.h
+++ b/drivers/common/cnxk/roc_npc.h
@@ -339,9 +339,6 @@ int __roc_api roc_npc_mcam_free_all_resources(struct roc_npc *roc_npc);
 void __roc_api roc_npc_flow_dump(FILE *file, struct roc_npc *roc_npc);
 void __roc_api roc_npc_flow_mcam_dump(FILE *file, struct roc_npc *roc_npc,
 				      struct roc_npc_flow *mcam);
-int __roc_api roc_npc_mark_actions_get(struct roc_npc *roc_npc);
-int __roc_api roc_npc_mark_actions_sub_return(struct roc_npc *roc_npc,
-					      uint32_t count);
 int __roc_api roc_npc_vtag_actions_get(struct roc_npc *roc_npc);
 int __roc_api roc_npc_vtag_actions_sub_return(struct roc_npc *roc_npc,
 					      uint32_t count);
diff --git a/drivers/common/cnxk/roc_npc_priv.h b/drivers/common/cnxk/roc_npc_priv.h
index 23e8675..e78d96e 100644
--- a/drivers/common/cnxk/roc_npc_priv.h
+++ b/drivers/common/cnxk/roc_npc_priv.h
@@ -380,7 +380,6 @@ struct npc {
 	uint16_t flow_prealloc_size;		/* Pre allocated mcam size */
 	uint16_t flow_max_priority;		/* Max priority for flow */
 	uint16_t switch_header_type; /* Supported switch header type */
-	uint32_t mark_actions;	     /* Number of mark actions */
 	uint32_t vtag_strip_actions; /* vtag insert/strip actions */
 	uint16_t pf_func;	     /* pf_func of device */
 	npc_dxcfg_t prx_dxcfg;	     /* intf, lid, lt, extract */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 94c35af..704dea7 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -306,8 +306,6 @@ INTERNAL {
 	roc_npc_flow_parse;
 	roc_npc_get_low_priority_mcam;
 	roc_npc_init;
-	roc_npc_mark_actions_get;
-	roc_npc_mark_actions_sub_return;
 	roc_npc_vtag_actions_get;
 	roc_npc_vtag_actions_sub_return;
 	roc_npc_mcam_alloc_entries;
-- 
2.8.4

[PATCH v2 12/21] net/cnxk: fix inline device RQ tag mask

[Nithin Dabilpuram]

Fix inline device rq tagmask to get packets with receive errors
as type ETHDEV packets to callback handler so that packet buffers
can get freed. Currently only ipsec denied packets get the right
tag mask.

Fixes: ee48f711f3b0 ("common/cnxk: support NIX inline inbound and outbound setup")
Cc: stable@dpdk.org

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/common/cnxk/roc_nix_inl.c | 2 +-
 drivers/net/cnxk/cnxk_ethdev.c    | 9 +++++++++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index 003f972..11a1691 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -584,7 +584,7 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq)
 
 	inl_rq->flow_tag_width = 20;
 	/* Special tag mask */
-	inl_rq->tag_mask = 0xFFF00000;
+	inl_rq->tag_mask = rq->tag_mask;
 	inl_rq->tt = SSO_TT_ORDERED;
 	inl_rq->hwgrp = 0;
 	inl_rq->wqe_skip = inl_dev->wqe_skip;
diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index 3468aab..b272ede 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -3,6 +3,8 @@
  */
 #include <cnxk_ethdev.h>
 
+#include <rte_eventdev.h>
+
 static inline uint64_t
 nix_get_rx_offload_capa(struct cnxk_eth_dev *dev)
 {
@@ -597,6 +599,13 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 	rxq_sp->qconf.mp = mp;
 
 	if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
+		/* Pass a tagmask used to handle error packets in inline device.
+		 * Ethdev rq's tag_mask field will be overwritten later
+		 * when sso is setup.
+		 */
+		rq->tag_mask =
+			0x0FF00000 | ((uint32_t)RTE_EVENT_TYPE_ETHDEV << 28);
+
 		/* Setup rq reference for inline dev if present */
 		rc = roc_nix_inl_dev_rq_get(rq);
 		if (rc)
-- 
2.8.4

[PATCH v2 13/21] net/cnxk: register callback early to handle initial packets

[Nithin Dabilpuram]

Register callback early to handle initial error packets from
inline device.

Fixes: 69daa9e5022b ("net/cnxk: support inline security setup for cn10k")
Cc: stable@dpdk.org

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/net/cnxk/cn10k_ethdev.c     | 6 ++++++
 drivers/net/cnxk/cn10k_ethdev.h     | 3 +++
 drivers/net/cnxk/cn10k_ethdev_sec.c | 5 +----
 3 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c
index 6bf8275..e47e04d 100644
--- a/drivers/net/cnxk/cn10k_ethdev.c
+++ b/drivers/net/cnxk/cn10k_ethdev.c
@@ -294,6 +294,12 @@ cn10k_nix_configure(struct rte_eth_dev *eth_dev)
 	if (rc)
 		return rc;
 
+	if (dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY ||
+	    dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {
+		/* Register callback to handle security error work */
+		roc_nix_inl_cb_register(cn10k_eth_sec_sso_work_cb, NULL);
+	}
+
 	/* Update offload flags */
 	dev->rx_offload_flags = nix_rx_offload_flags(eth_dev);
 	dev->tx_offload_flags = nix_tx_offload_flags(eth_dev);
diff --git a/drivers/net/cnxk/cn10k_ethdev.h b/drivers/net/cnxk/cn10k_ethdev.h
index ec40e53..fd72730 100644
--- a/drivers/net/cnxk/cn10k_ethdev.h
+++ b/drivers/net/cnxk/cn10k_ethdev.h
@@ -81,6 +81,9 @@ void cn10k_eth_set_tx_function(struct rte_eth_dev *eth_dev);
 /* Security context setup */
 void cn10k_eth_sec_ops_override(void);
 
+/* SSO Work callback */
+void cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args);
+
 #define LMT_OFF(lmt_addr, lmt_num, offset)                                     \
 	(void *)((uintptr_t)(lmt_addr) +                                       \
 		 ((uint64_t)(lmt_num) << ROC_LMT_LINE_SIZE_LOG2) + (offset))
diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c
index 6fbf444..ac45056 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -138,7 +138,7 @@ static const struct rte_security_capability cn10k_eth_sec_capabilities[] = {
 	}
 };
 
-static void
+void
 cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args)
 {
 	struct rte_eth_event_ipsec_desc desc;
@@ -251,9 +251,6 @@ cn10k_eth_sec_session_create(void *device,
 	if (rte_security_dynfield_register() < 0)
 		return -ENOTSUP;
 
-	if (rte_eal_process_type() == RTE_PROC_PRIMARY)
-		roc_nix_inl_cb_register(cn10k_eth_sec_sso_work_cb, NULL);
-
 	ipsec = &conf->ipsec;
 	crypto = conf->crypto_xform;
 	inbound = !!(ipsec->direction == RTE_SECURITY_IPSEC_SA_DIR_INGRESS);
-- 
2.8.4

[PATCH v2 14/21] net/cnxk: realloc inline dev XAQ for security

[Nithin Dabilpuram]

Realloc inline dev XAQ when Rx/Tx security ie enabled with
new packet pool as XAQ should be large enough to hold all
mbufs if inline outbound reports error or all mbufs.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/net/cnxk/cnxk_ethdev.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index b272ede..a6b6331 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -545,6 +545,11 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 		nb_desc = RTE_MAX(nb_desc, pkt_pool_limit);
 	}
 
+	/* Its a no-op when inline device is not used */
+	if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY ||
+	    dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY)
+		roc_nix_inl_dev_xaq_realloc(mp->pool_id);
+
 	/* Setup ROC CQ */
 	cq = &dev->cqs[qid];
 	cq->qid = qid;
-- 
2.8.4

[PATCH v2 15/21] net/cnxk: fix inline IPsec security error handling

[Nithin Dabilpuram]

Use raw mbuf free on inline security error to simulate
HW NPA free instead of doing rte_pktmbuf_free(). This
is needed as the callback will not be called from
DPDK lcore.

Fixes: 69daa9e5022b ("net/cnxk: support inline security setup for cn10k")
Cc: stable@dpdk.org

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/net/cnxk/cn10k_ethdev_sec.c | 37 ++++++++++++++++++++++++++++++++-----
 1 file changed, 32 insertions(+), 5 deletions(-)

diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c
index ac45056..044b20c 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -138,6 +138,20 @@ static const struct rte_security_capability cn10k_eth_sec_capabilities[] = {
 	}
 };
 
+static inline void
+cnxk_pktmbuf_free_no_cache(struct rte_mbuf *mbuf)
+{
+	struct rte_mbuf *next;
+
+	if (!mbuf)
+		return;
+	do {
+		next = mbuf->next;
+		roc_npa_aura_op_free(mbuf->pool->pool_id, 1, (rte_iova_t)mbuf);
+		mbuf = next;
+	} while (mbuf != NULL);
+}
+
 void
 cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args)
 {
@@ -148,6 +162,7 @@ cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args)
 	struct cpt_cn10k_res_s *res;
 	struct rte_eth_dev *eth_dev;
 	struct cnxk_eth_dev *dev;
+	static uint64_t warn_cnt;
 	uint16_t dlen_adj, rlen;
 	struct rte_mbuf *mbuf;
 	uintptr_t sa_base;
@@ -161,7 +176,7 @@ cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args)
 		/* Event from inbound inline dev due to IPSEC packet bad L4 */
 		mbuf = (struct rte_mbuf *)(gw[1] - sizeof(struct rte_mbuf));
 		plt_nix_dbg("Received mbuf %p from inline dev inbound", mbuf);
-		rte_pktmbuf_free(mbuf);
+		cnxk_pktmbuf_free_no_cache(mbuf);
 		return;
 	case RTE_EVENT_TYPE_CPU:
 		/* Check for subtype */
@@ -212,17 +227,29 @@ cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args)
 	case ROC_IE_OT_UCC_ERR_SA_OVERFLOW:
 		desc.subtype = RTE_ETH_EVENT_IPSEC_ESN_OVERFLOW;
 		break;
+	case ROC_IE_OT_UCC_ERR_PKT_IP:
+		warn_cnt++;
+		if (warn_cnt % 10000 == 0)
+			plt_warn("Outbound error, bad ip pkt, mbuf %p,"
+				 " sa_index %u (total warnings %" PRIu64 ")",
+				 mbuf, sess_priv.sa_idx, warn_cnt);
+		desc.subtype = RTE_ETH_EVENT_IPSEC_UNKNOWN;
+		break;
 	default:
-		plt_warn("Outbound error, mbuf %p, sa_index %u, "
-			 "compcode %x uc %x", mbuf, sess_priv.sa_idx,
-			 res->compcode, res->uc_compcode);
+		warn_cnt++;
+		if (warn_cnt % 10000 == 0)
+			plt_warn("Outbound error, mbuf %p, sa_index %u,"
+				 " compcode %x uc %x,"
+				 " (total warnings %" PRIu64 ")",
+				 mbuf, sess_priv.sa_idx, res->compcode,
+				 res->uc_compcode, warn_cnt);
 		desc.subtype = RTE_ETH_EVENT_IPSEC_UNKNOWN;
 		break;
 	}
 
 	desc.metadata = (uint64_t)priv->userdata;
 	rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_IPSEC, &desc);
-	rte_pktmbuf_free(mbuf);
+	cnxk_pktmbuf_free_no_cache(mbuf);
 }
 
 static int
-- 
2.8.4

[PATCH v2 16/21] net/cnxk: use NPA batch burst free for meta buffers

[Nithin Dabilpuram]

Currently meta buffers are freed in bursts of one LMT line
i.e 15 pointers. Instead free them in bursts of 16 LMTlines
which is 240 ptrs for better perf.

Also mark mempool objects as get and put in missing places.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/event/cnxk/cn10k_worker.h |  13 ++++-
 drivers/net/cnxk/cn10k_rx.h       | 112 +++++++++++++++++++++++++++++++-------
 2 files changed, 105 insertions(+), 20 deletions(-)

diff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h
index b9d8619..e8255ea 100644
--- a/drivers/event/cnxk/cn10k_worker.h
+++ b/drivers/event/cnxk/cn10k_worker.h
@@ -92,12 +92,16 @@ cn10k_sso_hws_forward_event(struct cn10k_sso_hws *ws,
 }
 
 static __rte_always_inline void
-cn10k_wqe_to_mbuf(uint64_t wqe, const uint64_t mbuf, uint8_t port_id,
+cn10k_wqe_to_mbuf(uint64_t wqe, const uint64_t __mbuf, uint8_t port_id,
 		  const uint32_t tag, const uint32_t flags,
 		  const void *const lookup_mem)
 {
 	const uint64_t mbuf_init = 0x100010000ULL | RTE_PKTMBUF_HEADROOM |
 				   (flags & NIX_RX_OFFLOAD_TSTAMP_F ? 8 : 0);
+	struct rte_mbuf *mbuf = (struct rte_mbuf *)__mbuf;
+
+	/* Mark mempool obj as "get" as it is alloc'ed by NIX */
+	RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
 
 	cn10k_nix_cqe_to_mbuf((struct nix_cqe_hdr_s *)wqe, tag,
 			      (struct rte_mbuf *)mbuf, lookup_mem,
@@ -159,6 +163,9 @@ cn10k_process_vwqe(uintptr_t vwqe, uint16_t port_id, const uint32_t flags,
 		mbuf = (struct rte_mbuf *)((char *)cqe -
 					   sizeof(struct rte_mbuf));
 
+		/* Mark mempool obj as "get" as it is alloc'ed by NIX */
+		RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
+
 		/* Translate meta to mbuf */
 		if (flags & NIX_RX_OFFLOAD_SECURITY_F) {
 			const uint64_t cq_w1 = *((const uint64_t *)cqe + 1);
@@ -278,6 +285,10 @@ cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev,
 			*(uint64_t *)gw.u64[1] = (uint64_t)vwqe_hdr;
 			cn10k_process_vwqe(gw.u64[1], port, flags, lookup_mem,
 					   ws->tstamp, ws->lmt_base);
+			/* Mark vector mempool object as get */
+			RTE_MEMPOOL_CHECK_COOKIES(
+				rte_mempool_from_obj((void *)gw.u64[1]),
+				(void **)&gw.u64[1], 1, 1);
 		}
 	}
 
diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h
index 0c9fe4a..2083c73 100644
--- a/drivers/net/cnxk/cn10k_rx.h
+++ b/drivers/net/cnxk/cn10k_rx.h
@@ -67,6 +67,24 @@ nix_get_mbuf_from_cqe(void *cq, const uint64_t data_off)
 }
 
 static __rte_always_inline void
+nix_sec_flush_meta_burst(uint16_t lmt_id, uint64_t data, uint16_t lnum,
+			 uintptr_t aura_handle)
+{
+	uint64_t pa;
+
+	/* Prepare PA and Data */
+	pa = roc_npa_aura_handle_to_base(aura_handle) + NPA_LF_AURA_BATCH_FREE0;
+	pa |= ((data & 0x7) << 4);
+
+	data >>= 3;
+	data <<= 19;
+	data |= (uint64_t)lmt_id;
+	data |= (uint64_t)(lnum - 1) << 12;
+
+	roc_lmt_submit_steorl(data, pa);
+}
+
+static __rte_always_inline void
 nix_sec_flush_meta(uintptr_t laddr, uint16_t lmt_id, uint8_t loff,
 		   uintptr_t aura_handle)
 {
@@ -82,7 +100,7 @@ nix_sec_flush_meta(uintptr_t laddr, uint16_t lmt_id, uint8_t loff,
 	*(uint64_t *)laddr = (((uint64_t)(loff & 0x1) << 32) |
 			      roc_npa_aura_handle_to_aura(aura_handle));
 
-	pa |= ((loff >> 1) << 4);
+	pa |= ((uint64_t)(loff >> 1) << 4);
 	roc_lmt_submit_steorl(lmt_id, pa);
 }
 
@@ -122,6 +140,12 @@ nix_sec_meta_to_mbuf_sc(uint64_t cq_w1, const uint64_t sa_base, uintptr_t laddr,
 		*(uint64_t *)(laddr + (*loff << 3)) = (uint64_t)mbuf;
 		*loff = *loff + 1;
 
+		/* Mark meta mbuf as put */
+		RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 0);
+
+		/* Mark inner mbuf as get */
+		RTE_MEMPOOL_CHECK_COOKIES(inner->pool, (void **)&inner, 1, 1);
+
 		return inner;
 	}
 	return mbuf;
@@ -181,6 +205,12 @@ nix_sec_meta_to_mbuf(uint64_t cq_w1, uintptr_t sa_base, uintptr_t laddr,
 		*(uint64_t *)(laddr + (*loff << 3)) = (uint64_t)mbuf;
 		*loff = *loff + 1;
 
+		/* Mark meta mbuf as put */
+		RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 0);
+
+		/* Mark inner mbuf as get */
+		RTE_MEMPOOL_CHECK_COOKIES(inner->pool, (void **)&inner, 1, 1);
+
 		/* Return inner mbuf */
 		return inner;
 	}
@@ -306,9 +336,6 @@ cn10k_nix_cqe_to_mbuf(const struct nix_cqe_hdr_s *cq, const uint32_t tag,
 	uint16_t len = rx->pkt_lenm1 + 1;
 	uint64_t ol_flags = 0;
 
-	/* Mark mempool obj as "get" as it is alloc'ed by NIX */
-	RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
-
 	if (flag & NIX_RX_OFFLOAD_PTYPE_F)
 		mbuf->packet_type = nix_ptype_get(lookup_mem, w1);
 	else
@@ -446,6 +473,9 @@ cn10k_nix_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t pkts,
 
 		mbuf = nix_get_mbuf_from_cqe(cq, data_off);
 
+		/* Mark mempool obj as "get" as it is alloc'ed by NIX */
+		RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1);
+
 		/* Translate meta to mbuf */
 		if (flags & NIX_RX_OFFLOAD_SECURITY_F) {
 			const uint64_t cq_w1 = *((const uint64_t *)cq + 1);
@@ -543,7 +573,7 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,
 	uint64x2_t rearm3 = vdupq_n_u64(mbuf_initializer);
 	struct rte_mbuf *mbuf0, *mbuf1, *mbuf2, *mbuf3;
 	uint64_t aura_handle, lbase, laddr;
-	uint8_t loff = 0, lnum = 0;
+	uint8_t loff = 0, lnum = 0, shft = 0;
 	uint8x16_t f0, f1, f2, f3;
 	uint16_t lmt_id, d_off;
 	uint16_t packets = 0;
@@ -714,6 +744,12 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,
 			ol_flags3 |= nix_rx_olflags_get(lookup_mem, cq3_w1);
 		}
 
+		/* Mark mempool obj as "get" as it is alloc'ed by NIX */
+		RTE_MEMPOOL_CHECK_COOKIES(mbuf0->pool, (void **)&mbuf0, 1, 1);
+		RTE_MEMPOOL_CHECK_COOKIES(mbuf1->pool, (void **)&mbuf1, 1, 1);
+		RTE_MEMPOOL_CHECK_COOKIES(mbuf2->pool, (void **)&mbuf2, 1, 1);
+		RTE_MEMPOOL_CHECK_COOKIES(mbuf3->pool, (void **)&mbuf3, 1, 1);
+
 		/* Translate meta to mbuf */
 		if (flags & NIX_RX_OFFLOAD_SECURITY_F) {
 			/* Checksum ol_flags will be cleared if mbuf is meta */
@@ -910,12 +946,6 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,
 		roc_prefetch_store_keep(mbuf2);
 		roc_prefetch_store_keep(mbuf3);
 
-		/* Mark mempool obj as "get" as it is alloc'ed by NIX */
-		RTE_MEMPOOL_CHECK_COOKIES(mbuf0->pool, (void **)&mbuf0, 1, 1);
-		RTE_MEMPOOL_CHECK_COOKIES(mbuf1->pool, (void **)&mbuf1, 1, 1);
-		RTE_MEMPOOL_CHECK_COOKIES(mbuf2->pool, (void **)&mbuf2, 1, 1);
-		RTE_MEMPOOL_CHECK_COOKIES(mbuf3->pool, (void **)&mbuf3, 1, 1);
-
 		packets += NIX_DESCS_PER_LOOP;
 
 		if (!(flags & NIX_RX_VWQE_F)) {
@@ -925,22 +955,66 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts,
 		}
 
 		if (flags & NIX_RX_OFFLOAD_SECURITY_F) {
-			/* Flush when we don't have space for 4 meta */
-			if ((15 - loff) < 4) {
-				nix_sec_flush_meta(laddr, lmt_id + lnum, loff,
-						   aura_handle);
+			/* Check if lmtline border is crossed and adjust lnum */
+			if (loff > 15) {
+				/* Update aura handle */
+				*(uint64_t *)(laddr - 8) =
+					(((uint64_t)(15 & 0x1) << 32) |
+				    roc_npa_aura_handle_to_aura(aura_handle));
+				loff = loff - 15;
+				shft += 3;
+
 				lnum++;
-				lnum &= BIT_ULL(ROC_LMT_LINES_PER_CORE_LOG2) -
-					1;
-				/* First pointer starts at 8B offset */
 				laddr = (uintptr_t)LMT_OFF(lbase, lnum, 8);
+				/* Pick the pointer from 16th index and put it
+				 * at end of this new line.
+				 */
+				*(uint64_t *)(laddr + (loff << 3) - 8) =
+					*(uint64_t *)(laddr - 8);
+			}
+
+			/* Flush it when we are in 16th line and might
+			 * overflow it
+			 */
+			if (lnum >= 15 && loff >= 12) {
+				/* 16 LMT Line size m1 */
+				uint64_t data = BIT_ULL(48) - 1;
+
+				/* Update aura handle */
+				*(uint64_t *)(laddr - 8) =
+					(((uint64_t)(loff & 0x1) << 32) |
+				    roc_npa_aura_handle_to_aura(aura_handle));
+
+				data = (data & ~(0x7UL << shft)) |
+				       (((uint64_t)loff >> 1) << shft);
+
+				/* Send up to 16 lmt lines of pointers */
+				nix_sec_flush_meta_burst(lmt_id, data, lnum + 1,
+							 aura_handle);
+				rte_io_wmb();
+				lnum = 0;
 				loff = 0;
+				shft = 0;
+				/* First pointer starts at 8B offset */
+				laddr = (uintptr_t)LMT_OFF(lbase, lnum, 8);
 			}
 		}
 	}
 
 	if (flags & NIX_RX_OFFLOAD_SECURITY_F && loff) {
-		nix_sec_flush_meta(laddr, lmt_id + lnum, loff, aura_handle);
+		/* 16 LMT Line size m1 */
+		uint64_t data = BIT_ULL(48) - 1;
+
+		/* Update aura handle */
+		*(uint64_t *)(laddr - 8) =
+			(((uint64_t)(loff & 0x1) << 32) |
+			 roc_npa_aura_handle_to_aura(aura_handle));
+
+		data = (data & ~(0x7UL << shft)) |
+		       (((uint64_t)loff >> 1) << shft);
+
+		/* Send up to 16 lmt lines of pointers */
+		nix_sec_flush_meta_burst(lmt_id, data, lnum + 1, aura_handle);
 		if (flags & NIX_RX_VWQE_F)
 			plt_io_wmb();
 	}
-- 
2.8.4

[PATCH v2 17/21] net/cnxk: enable packet pool tail drop

[Nithin Dabilpuram]

Enable packet pool tail drop on RQ when inbound security is not
enabled. This is only part of the config. It is a NOP if
tail drop is not enabled on NPA_AURA_CTX_S. And tail drop
on packet pool AURA is enabled only when that packet pool aura
is used by inline device RQ.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/net/cnxk/cnxk_ethdev.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index a6b6331..ad1e63d 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -574,6 +574,7 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,
 	rq->first_skip = first_skip;
 	rq->later_skip = sizeof(struct rte_mbuf);
 	rq->lpb_size = mp->elt_size;
+	rq->lpb_drop_ena = !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY);
 
 	/* Enable Inline IPSec on RQ, will not be used for Poll mode */
 	if (roc_nix_inl_inb_is_enabled(nix))
-- 
2.8.4

[PATCH v2 18/21] net/cnxk: enable flow control by default on device configure

[Nithin Dabilpuram]

Enable flow control by default on device configuration
instead of basing it on Kernel behaviour.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Harman Kalra <hkalra@marvell.com>
---
 drivers/net/cnxk/cnxk_ethdev.c | 24 +++++++++++-------------
 1 file changed, 11 insertions(+), 13 deletions(-)

diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index ad1e63d..9481af9 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -306,24 +306,22 @@ static int
 nix_init_flow_ctrl_config(struct rte_eth_dev *eth_dev)
 {
 	struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
+	enum roc_nix_fc_mode fc_mode = ROC_NIX_FC_FULL;
 	struct cnxk_fc_cfg *fc = &dev->fc_cfg;
-	struct rte_eth_fc_conf fc_conf = {0};
 	int rc;
 
-	/* Both Rx & Tx flow ctrl get enabled(RTE_ETH_FC_FULL) in HW
-	 * by AF driver, update those info in PMD structure.
-	 */
-	rc = cnxk_nix_flow_ctrl_get(eth_dev, &fc_conf);
+	/* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */
+	if (roc_model_is_cn96_ax() &&
+	    dev->npc.switch_header_type != ROC_PRIV_FLAGS_HIGIG)
+		fc_mode = ROC_NIX_FC_TX;
+
+	/* By default enable flow control */
+	rc = roc_nix_fc_mode_set(&dev->nix, fc_mode);
 	if (rc)
-		goto exit;
+		return rc;
 
-	fc->mode = fc_conf.mode;
-	fc->rx_pause = (fc_conf.mode == RTE_ETH_FC_FULL) ||
-			(fc_conf.mode == RTE_ETH_FC_RX_PAUSE);
-	fc->tx_pause = (fc_conf.mode == RTE_ETH_FC_FULL) ||
-			(fc_conf.mode == RTE_ETH_FC_TX_PAUSE);
-
-exit:
+	fc->mode = (fc_mode == ROC_NIX_FC_FULL) ? RTE_ETH_FC_FULL :
+						  RTE_ETH_FC_TX_PAUSE;
 	return rc;
 }
 
-- 
2.8.4

[PATCH v2 19/21] net/cnxk: add dev args for min-max spi

[Nithin Dabilpuram]

Add support for inline inbound SPI range via devargs
instead of just max SPI value and range being 0..max.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 doc/guides/nics/cnxk.rst               | 28 +++++++++++++-
 drivers/common/cnxk/roc_nix.h          |  5 ++-
 drivers/common/cnxk/roc_nix_inl.c      | 68 ++++++++++++++++++++--------------
 drivers/common/cnxk/roc_nix_inl.h      |  8 ++--
 drivers/common/cnxk/roc_nix_inl_dev.c  | 22 +++++++----
 drivers/common/cnxk/roc_nix_inl_priv.h |  4 +-
 drivers/common/cnxk/roc_nix_priv.h     |  1 +
 drivers/common/cnxk/version.map        |  2 +-
 drivers/net/cnxk/cn10k_ethdev_sec.c    | 13 +++++--
 drivers/net/cnxk/cn9k_ethdev_sec.c     | 10 +++--
 drivers/net/cnxk/cnxk_ethdev_devargs.c | 25 +++++++++----
 drivers/net/cnxk/cnxk_ethdev_sec.c     | 16 ++++++--
 drivers/net/cnxk/cnxk_lookup.c         |  3 +-
 13 files changed, 142 insertions(+), 63 deletions(-)

diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst
index 27a9420..e7c5ea5 100644
--- a/doc/guides/nics/cnxk.rst
+++ b/doc/guides/nics/cnxk.rst
@@ -214,6 +214,18 @@ Runtime Config Options
 
       -a 0002:02:00.0,tag_as_xor=1
 
+- ``Min SPI for inbound inline IPsec`` (default ``0``)
+
+   Min SPI supported for inbound inline IPsec processing can be specified by
+   ``ipsec_in_min_spi`` ``devargs`` parameter.
+
+   For example::
+
+      -a 0002:02:00.0,ipsec_in_min_spi=6
+
+   With the above configuration, application can enable inline IPsec processing
+   for inbound SA with min SPI of 6.
+
 - ``Max SPI for inbound inline IPsec`` (default ``255``)
 
    Max SPI supported for inbound inline IPsec processing can be specified by
@@ -224,7 +236,7 @@ Runtime Config Options
       -a 0002:02:00.0,ipsec_in_max_spi=128
 
    With the above configuration, application can enable inline IPsec processing
-   for 128 inbound SAs (SPI 0-127).
+   with max SPI of 128.
 
 - ``Max SA's for outbound inline IPsec`` (default ``4096``)
 
@@ -413,6 +425,18 @@ VF ``177D:A0F1``.
 Runtime Config Options for inline device
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
+- ``Min SPI for inbound inline IPsec`` (default ``0``)
+
+   Min SPI supported for inbound inline IPsec processing can be specified by
+   ``ipsec_in_min_spi`` ``devargs`` parameter.
+
+   For example::
+
+      -a 0002:1d:00.0,ipsec_in_min_spi=6
+
+   With the above configuration, application can enable inline IPsec processing
+   for inbound SA with min SPI of 6 for traffic aggregated on inline device.
+
 - ``Max SPI for inbound inline IPsec`` (default ``255``)
 
    Max SPI supported for inbound inline IPsec processing can be specified by
@@ -423,7 +447,7 @@ Runtime Config Options for inline device
       -a 0002:1d:00.0,ipsec_in_max_spi=128
 
    With the above configuration, application can enable inline IPsec processing
-   for 128 inbound SAs (SPI 0-127) for traffic aggregated on inline device.
+   for inbound SA with max SPI of 128 for traffic aggregated on inline device.
 
 
 Debugging Options
diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h
index 57a595f..ea58e06 100644
--- a/drivers/common/cnxk/roc_nix.h
+++ b/drivers/common/cnxk/roc_nix.h
@@ -384,8 +384,9 @@ struct roc_nix {
 	uint8_t lock_rx_ctx;
 	uint32_t outb_nb_desc;
 	uint16_t outb_nb_crypto_qs;
-	uint16_t ipsec_in_max_spi;
-	uint16_t ipsec_out_max_sa;
+	uint32_t ipsec_in_min_spi;
+	uint32_t ipsec_in_max_spi;
+	uint32_t ipsec_out_max_sa;
 	bool ipsec_out_sso_pffunc;
 	/* End of input parameters */
 	/* LMT line base for "Per Core Tx LMT line" mode*/
diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c
index 11a1691..7bf89a4 100644
--- a/drivers/common/cnxk/roc_nix_inl.c
+++ b/drivers/common/cnxk/roc_nix_inl.c
@@ -19,12 +19,16 @@ PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ ==
 static int
 nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
 {
-	uint16_t ipsec_in_max_spi = roc_nix->ipsec_in_max_spi;
+	uint32_t ipsec_in_min_spi = roc_nix->ipsec_in_min_spi;
+	uint32_t ipsec_in_max_spi = roc_nix->ipsec_in_max_spi;
 	struct nix *nix = roc_nix_to_nix_priv(roc_nix);
 	struct roc_nix_ipsec_cfg cfg;
+	uint64_t max_sa, i;
 	size_t inb_sa_sz;
-	int rc, i;
 	void *sa;
+	int rc;
+
+	max_sa = plt_align32pow2(ipsec_in_max_spi - ipsec_in_min_spi + 1);
 
 	/* CN9K SA size is different */
 	if (roc_model_is_cn9k())
@@ -34,14 +38,15 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
 
 	/* Alloc contiguous memory for Inbound SA's */
 	nix->inb_sa_sz = inb_sa_sz;
-	nix->inb_sa_base = plt_zmalloc(inb_sa_sz * ipsec_in_max_spi,
+	nix->inb_spi_mask = max_sa - 1;
+	nix->inb_sa_base = plt_zmalloc(inb_sa_sz * max_sa,
 				       ROC_NIX_INL_SA_BASE_ALIGN);
 	if (!nix->inb_sa_base) {
 		plt_err("Failed to allocate memory for Inbound SA");
 		return -ENOMEM;
 	}
 	if (roc_model_is_cn10k()) {
-		for (i = 0; i < ipsec_in_max_spi; i++) {
+		for (i = 0; i < max_sa; i++) {
 			sa = ((uint8_t *)nix->inb_sa_base) + (i * inb_sa_sz);
 			roc_ot_ipsec_inb_sa_init(sa, true);
 		}
@@ -50,7 +55,7 @@ nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)
 	memset(&cfg, 0, sizeof(cfg));
 	cfg.sa_size = inb_sa_sz;
 	cfg.iova = (uintptr_t)nix->inb_sa_base;
-	cfg.max_sa = ipsec_in_max_spi + 1;
+	cfg.max_sa = max_sa;
 	cfg.tt = SSO_TT_ORDERED;
 
 	/* Setup device specific inb SA table */
@@ -135,11 +140,13 @@ roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix, bool inb_inl_dev)
 }
 
 uint32_t
-roc_nix_inl_inb_sa_max_spi(struct roc_nix *roc_nix, bool inb_inl_dev)
+roc_nix_inl_inb_spi_range(struct roc_nix *roc_nix, bool inb_inl_dev,
+			  uint32_t *min_spi, uint32_t *max_spi)
 {
 	struct idev_cfg *idev = idev_get_cfg();
+	uint32_t min = 0, max = 0, mask = 0;
 	struct nix_inl_dev *inl_dev;
-	struct nix *nix;
+	struct nix *nix = NULL;
 
 	if (idev == NULL)
 		return 0;
@@ -147,20 +154,25 @@ roc_nix_inl_inb_sa_max_spi(struct roc_nix *roc_nix, bool inb_inl_dev)
 	if (!inb_inl_dev && roc_nix == NULL)
 		return -EINVAL;
 
-	if (roc_nix) {
+	inl_dev = idev->nix_inl_dev;
+	if (inb_inl_dev) {
+		min = inl_dev->ipsec_in_min_spi;
+		max = inl_dev->ipsec_in_max_spi;
+		mask = inl_dev->inb_spi_mask;
+	} else {
 		nix = roc_nix_to_nix_priv(roc_nix);
 		if (!nix->inl_inb_ena)
-			return 0;
+			goto exit;
+		min = roc_nix->ipsec_in_min_spi;
+		max = roc_nix->ipsec_in_max_spi;
+		mask = nix->inb_spi_mask;
 	}
-
-	if (inb_inl_dev) {
-		inl_dev = idev->nix_inl_dev;
-		if (inl_dev)
-			return inl_dev->ipsec_in_max_spi;
-		return 0;
-	}
-
-	return roc_nix->ipsec_in_max_spi;
+exit:
+	if (min_spi)
+		*min_spi = min;
+	if (max_spi)
+		*max_spi = max;
+	return mask;
 }
 
 uint32_t
@@ -194,8 +206,8 @@ roc_nix_inl_inb_sa_sz(struct roc_nix *roc_nix, bool inl_dev_sa)
 uintptr_t
 roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool inb_inl_dev, uint32_t spi)
 {
+	uint32_t max_spi, min_spi, mask;
 	uintptr_t sa_base;
-	uint32_t max_spi;
 	uint64_t sz;
 
 	sa_base = roc_nix_inl_inb_sa_base_get(roc_nix, inb_inl_dev);
@@ -204,11 +216,11 @@ roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool inb_inl_dev, uint32_t spi)
 		return 0;
 
 	/* Check if SPI is in range */
-	max_spi = roc_nix_inl_inb_sa_max_spi(roc_nix, inb_inl_dev);
-	if (spi > max_spi) {
-		plt_err("Inbound SA SPI %u exceeds max %u", spi, max_spi);
-		return 0;
-	}
+	mask = roc_nix_inl_inb_spi_range(roc_nix, inb_inl_dev, &min_spi,
+					 &max_spi);
+	if (spi > max_spi || spi < min_spi)
+		plt_warn("Inbound SA SPI %u not in range (%u..%u)", spi,
+			 min_spi, max_spi);
 
 	/* Get SA size */
 	sz = roc_nix_inl_inb_sa_sz(roc_nix, inb_inl_dev);
@@ -216,7 +228,7 @@ roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix, bool inb_inl_dev, uint32_t spi)
 		return 0;
 
 	/* Basic logic of SPI->SA for now */
-	return (sa_base + (spi * sz));
+	return (sa_base + ((spi & mask) * sz));
 }
 
 int
@@ -295,11 +307,11 @@ roc_nix_inl_outb_init(struct roc_nix *roc_nix)
 	struct nix_inl_dev *inl_dev;
 	uint16_t sso_pffunc;
 	uint8_t eng_grpmask;
-	uint64_t blkaddr;
+	uint64_t blkaddr, i;
 	uint16_t nb_lf;
 	void *sa_base;
 	size_t sa_sz;
-	int i, j, rc;
+	int j, rc;
 	void *sa;
 
 	if (idev == NULL)
@@ -775,7 +787,7 @@ roc_nix_inl_inb_tag_update(struct roc_nix *roc_nix, uint32_t tag_const,
 	memset(&cfg, 0, sizeof(cfg));
 	cfg.sa_size = nix->inb_sa_sz;
 	cfg.iova = (uintptr_t)nix->inb_sa_base;
-	cfg.max_sa = roc_nix->ipsec_in_max_spi + 1;
+	cfg.max_sa = nix->inb_spi_mask + 1;
 	cfg.tt = tt;
 	cfg.tag_const = tag_const;
 
diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h
index 728225b..5eb1a81 100644
--- a/drivers/common/cnxk/roc_nix_inl.h
+++ b/drivers/common/cnxk/roc_nix_inl.h
@@ -105,7 +105,8 @@ typedef void (*roc_nix_inl_sso_work_cb_t)(uint64_t *gw, void *args);
 struct roc_nix_inl_dev {
 	/* Input parameters */
 	struct plt_pci_device *pci_dev;
-	uint16_t ipsec_in_max_spi;
+	uint32_t ipsec_in_min_spi;
+	uint32_t ipsec_in_max_spi;
 	bool selftest;
 	bool is_multi_channel;
 	uint16_t channel;
@@ -136,8 +137,9 @@ int __roc_api roc_nix_inl_inb_fini(struct roc_nix *roc_nix);
 bool __roc_api roc_nix_inl_inb_is_enabled(struct roc_nix *roc_nix);
 uintptr_t __roc_api roc_nix_inl_inb_sa_base_get(struct roc_nix *roc_nix,
 						bool inl_dev_sa);
-uint32_t __roc_api roc_nix_inl_inb_sa_max_spi(struct roc_nix *roc_nix,
-					      bool inl_dev_sa);
+uint32_t __roc_api roc_nix_inl_inb_spi_range(struct roc_nix *roc_nix,
+					     bool inl_dev_sa, uint32_t *min,
+					     uint32_t *max);
 uint32_t __roc_api roc_nix_inl_inb_sa_sz(struct roc_nix *roc_nix,
 					 bool inl_dev_sa);
 uintptr_t __roc_api roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix,
diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c
index 4c1d85a..aeec406 100644
--- a/drivers/common/cnxk/roc_nix_inl_dev.c
+++ b/drivers/common/cnxk/roc_nix_inl_dev.c
@@ -120,6 +120,7 @@ nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool ena)
 {
 	struct nix_inline_ipsec_lf_cfg *lf_cfg;
 	struct mbox *mbox = (&inl_dev->dev)->mbox;
+	uint64_t max_sa;
 	uint32_t sa_w;
 
 	lf_cfg = mbox_alloc_msg_nix_inline_ipsec_lf_cfg(mbox);
@@ -127,8 +128,9 @@ nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool ena)
 		return -ENOSPC;
 
 	if (ena) {
-		sa_w = plt_align32pow2(inl_dev->ipsec_in_max_spi + 1);
-		sa_w = plt_log2_u32(sa_w);
+
+		max_sa = inl_dev->inb_spi_mask + 1;
+		sa_w = plt_log2_u32(max_sa);
 
 		lf_cfg->enable = 1;
 		lf_cfg->sa_base_addr = (uintptr_t)inl_dev->inb_sa_base;
@@ -138,7 +140,7 @@ nix_inl_nix_ipsec_cfg(struct nix_inl_dev *inl_dev, bool ena)
 			lf_cfg->ipsec_cfg0.lenm1_max = NIX_CN9K_MAX_HW_FRS - 1;
 		else
 			lf_cfg->ipsec_cfg0.lenm1_max = NIX_RPM_MAX_HW_FRS - 1;
-		lf_cfg->ipsec_cfg1.sa_idx_max = inl_dev->ipsec_in_max_spi;
+		lf_cfg->ipsec_cfg1.sa_idx_max = max_sa - 1;
 		lf_cfg->ipsec_cfg0.sa_pow2_size =
 			plt_log2_u32(inl_dev->inb_sa_sz);
 
@@ -319,16 +321,20 @@ nix_inl_sso_release(struct nix_inl_dev *inl_dev)
 static int
 nix_inl_nix_setup(struct nix_inl_dev *inl_dev)
 {
-	uint16_t ipsec_in_max_spi = inl_dev->ipsec_in_max_spi;
+	uint32_t ipsec_in_min_spi = inl_dev->ipsec_in_min_spi;
+	uint32_t ipsec_in_max_spi = inl_dev->ipsec_in_max_spi;
 	struct dev *dev = &inl_dev->dev;
 	struct mbox *mbox = dev->mbox;
 	struct nix_lf_alloc_rsp *rsp;
 	struct nix_lf_alloc_req *req;
 	struct nix_hw_info *hw_info;
+	uint64_t max_sa, i;
 	size_t inb_sa_sz;
-	int i, rc = -ENOSPC;
+	int rc = -ENOSPC;
 	void *sa;
 
+	max_sa = plt_align32pow2(ipsec_in_max_spi - ipsec_in_min_spi + 1);
+
 	/* Alloc NIX LF needed for single RQ */
 	req = mbox_alloc_msg_nix_lf_alloc(mbox);
 	if (req == NULL)
@@ -387,7 +393,8 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev)
 
 	/* Alloc contiguous memory for Inbound SA's */
 	inl_dev->inb_sa_sz = inb_sa_sz;
-	inl_dev->inb_sa_base = plt_zmalloc(inb_sa_sz * ipsec_in_max_spi,
+	inl_dev->inb_spi_mask = max_sa - 1;
+	inl_dev->inb_sa_base = plt_zmalloc(inb_sa_sz * max_sa,
 					   ROC_NIX_INL_SA_BASE_ALIGN);
 	if (!inl_dev->inb_sa_base) {
 		plt_err("Failed to allocate memory for Inbound SA");
@@ -396,7 +403,7 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev)
 	}
 
 	if (roc_model_is_cn10k()) {
-		for (i = 0; i < ipsec_in_max_spi; i++) {
+		for (i = 0; i < max_sa; i++) {
 			sa = ((uint8_t *)inl_dev->inb_sa_base) +
 			     (i * inb_sa_sz);
 			roc_ot_ipsec_inb_sa_init(sa, true);
@@ -657,6 +664,7 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)
 	memset(inl_dev, 0, sizeof(*inl_dev));
 
 	inl_dev->pci_dev = pci_dev;
+	inl_dev->ipsec_in_min_spi = roc_inl_dev->ipsec_in_min_spi;
 	inl_dev->ipsec_in_max_spi = roc_inl_dev->ipsec_in_max_spi;
 	inl_dev->selftest = roc_inl_dev->selftest;
 	inl_dev->is_multi_channel = roc_inl_dev->is_multi_channel;
diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h
index b6d8602..24dabbc 100644
--- a/drivers/common/cnxk/roc_nix_inl_priv.h
+++ b/drivers/common/cnxk/roc_nix_inl_priv.h
@@ -58,7 +58,9 @@ struct nix_inl_dev {
 	uint16_t channel;
 	uint16_t chan_mask;
 	bool is_multi_channel;
-	uint16_t ipsec_in_max_spi;
+	uint32_t ipsec_in_min_spi;
+	uint32_t ipsec_in_max_spi;
+	uint32_t inb_spi_mask;
 	bool attach_cptlf;
 	bool wqe_skip;
 };
diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h
index ec6f106..51b022e 100644
--- a/drivers/common/cnxk/roc_nix_priv.h
+++ b/drivers/common/cnxk/roc_nix_priv.h
@@ -174,6 +174,7 @@ struct nix {
 	bool inl_outb_ena;
 	void *inb_sa_base;
 	size_t inb_sa_sz;
+	uint32_t inb_spi_mask;
 	void *outb_sa_base;
 	size_t outb_sa_sz;
 	uint16_t outb_err_sso_pffunc;
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 704dea7..7f24bd6 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -143,7 +143,7 @@ INTERNAL {
 	roc_nix_inl_inb_init;
 	roc_nix_inl_inb_sa_base_get;
 	roc_nix_inl_inb_sa_get;
-	roc_nix_inl_inb_sa_max_spi;
+	roc_nix_inl_inb_spi_range;
 	roc_nix_inl_inb_sa_sz;
 	roc_nix_inl_inb_tag_update;
 	roc_nix_inl_inb_fini;
diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c
index 044b20c..a2a53c1 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -264,6 +264,7 @@ cn10k_eth_sec_session_create(void *device,
 	struct cn10k_sec_sess_priv sess_priv;
 	struct rte_crypto_sym_xform *crypto;
 	struct cnxk_eth_sec_sess *eth_sec;
+	struct roc_nix *nix = &dev->nix;
 	bool inbound, inl_dev;
 	rte_spinlock_t *lock;
 	char tbuf[128] = {0};
@@ -308,13 +309,16 @@ cn10k_eth_sec_session_create(void *device,
 	if (inbound) {
 		struct roc_ot_ipsec_inb_sa *inb_sa, *inb_sa_dptr;
 		struct cn10k_inb_priv_data *inb_priv;
+		uint32_t spi_mask;
 		uintptr_t sa;
 
 		PLT_STATIC_ASSERT(sizeof(struct cn10k_inb_priv_data) <
 				  ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD);
 
+		spi_mask = roc_nix_inl_inb_spi_range(nix, inl_dev, NULL, NULL);
+
 		/* Get Inbound SA from NIX_RX_IPSEC_SA_BASE */
-		sa = roc_nix_inl_inb_sa_get(&dev->nix, inl_dev, ipsec->spi);
+		sa = roc_nix_inl_inb_sa_get(nix, inl_dev, ipsec->spi);
 		if (!sa && dev->inb.inl_dev) {
 			snprintf(tbuf, sizeof(tbuf),
 				 "Failed to create ingress sa, inline dev "
@@ -358,16 +362,17 @@ cn10k_eth_sec_session_create(void *device,
 		inb_priv->userdata = conf->userdata;
 
 		/* Save SA index/SPI in cookie for now */
-		inb_sa_dptr->w1.s.cookie = rte_cpu_to_be_32(ipsec->spi);
+		inb_sa_dptr->w1.s.cookie =
+			rte_cpu_to_be_32(ipsec->spi & spi_mask);
 
 		/* Prepare session priv */
 		sess_priv.inb_sa = 1;
-		sess_priv.sa_idx = ipsec->spi;
+		sess_priv.sa_idx = ipsec->spi & spi_mask;
 
 		/* Pointer from eth_sec -> inb_sa */
 		eth_sec->sa = inb_sa;
 		eth_sec->sess = sess;
-		eth_sec->sa_idx = ipsec->spi;
+		eth_sec->sa_idx = ipsec->spi & spi_mask;
 		eth_sec->spi = ipsec->spi;
 		eth_sec->inl_dev = !!dev->inb.inl_dev;
 		eth_sec->inb = true;
diff --git a/drivers/net/cnxk/cn9k_ethdev_sec.c b/drivers/net/cnxk/cn9k_ethdev_sec.c
index 27930d1..fa72424 100644
--- a/drivers/net/cnxk/cn9k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn9k_ethdev_sec.c
@@ -146,6 +146,7 @@ cn9k_eth_sec_session_create(void *device,
 	struct cn9k_sec_sess_priv sess_priv;
 	struct rte_crypto_sym_xform *crypto;
 	struct cnxk_eth_sec_sess *eth_sec;
+	struct roc_nix *nix = &dev->nix;
 	rte_spinlock_t *lock;
 	char tbuf[128] = {0};
 	bool inbound;
@@ -185,15 +186,18 @@ cn9k_eth_sec_session_create(void *device,
 	if (inbound) {
 		struct cn9k_inb_priv_data *inb_priv;
 		struct roc_onf_ipsec_inb_sa *inb_sa;
+		uint32_t spi_mask;
 
 		PLT_STATIC_ASSERT(sizeof(struct cn9k_inb_priv_data) <
 				  ROC_NIX_INL_ONF_IPSEC_INB_SW_RSVD);
 
+		spi_mask = roc_nix_inl_inb_spi_range(nix, false, NULL, NULL);
+
 		/* Get Inbound SA from NIX_RX_IPSEC_SA_BASE. Assume no inline
 		 * device always for CN9K.
 		 */
 		inb_sa = (struct roc_onf_ipsec_inb_sa *)
-			 roc_nix_inl_inb_sa_get(&dev->nix, false, ipsec->spi);
+			 roc_nix_inl_inb_sa_get(nix, false, ipsec->spi);
 		if (!inb_sa) {
 			snprintf(tbuf, sizeof(tbuf),
 				 "Failed to create ingress sa");
@@ -236,12 +240,12 @@ cn9k_eth_sec_session_create(void *device,
 
 		/* Prepare session priv */
 		sess_priv.inb_sa = 1;
-		sess_priv.sa_idx = ipsec->spi;
+		sess_priv.sa_idx = ipsec->spi & spi_mask;
 
 		/* Pointer from eth_sec -> inb_sa */
 		eth_sec->sa = inb_sa;
 		eth_sec->sess = sess;
-		eth_sec->sa_idx = ipsec->spi;
+		eth_sec->sa_idx = ipsec->spi & spi_mask;
 		eth_sec->spi = ipsec->spi;
 		eth_sec->inb = true;
 
diff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c
index 157b27d..8a71644 100644
--- a/drivers/net/cnxk/cnxk_ethdev_devargs.c
+++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c
@@ -49,14 +49,17 @@ parse_outb_nb_crypto_qs(const char *key, const char *value, void *extra_args)
 }
 
 static int
-parse_ipsec_in_max_spi(const char *key, const char *value, void *extra_args)
+parse_ipsec_in_spi_range(const char *key, const char *value, void *extra_args)
 {
 	RTE_SET_USED(key);
 	uint32_t val;
 
-	val = atoi(value);
+	errno = 0;
+	val = strtoul(value, NULL, 0);
+	if (errno)
+		val = 0;
 
-	*(uint16_t *)extra_args = val;
+	*(uint32_t *)extra_args = val;
 
 	return 0;
 }
@@ -67,7 +70,10 @@ parse_ipsec_out_max_sa(const char *key, const char *value, void *extra_args)
 	RTE_SET_USED(key);
 	uint32_t val;
 
-	val = atoi(value);
+	errno = 0;
+	val = strtoul(value, NULL, 0);
+	if (errno)
+		val = 0;
 
 	*(uint16_t *)extra_args = val;
 
@@ -231,6 +237,7 @@ parse_sdp_channel_mask(const char *key, const char *value, void *extra_args)
 #define CNXK_SWITCH_HEADER_TYPE "switch_header"
 #define CNXK_RSS_TAG_AS_XOR	"tag_as_xor"
 #define CNXK_LOCK_RX_CTX	"lock_rx_ctx"
+#define CNXK_IPSEC_IN_MIN_SPI	"ipsec_in_min_spi"
 #define CNXK_IPSEC_IN_MAX_SPI	"ipsec_in_max_spi"
 #define CNXK_IPSEC_OUT_MAX_SA	"ipsec_out_max_sa"
 #define CNXK_OUTB_NB_DESC	"outb_nb_desc"
@@ -245,13 +252,14 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
 	uint16_t reta_sz = ROC_NIX_RSS_RETA_SZ_64;
 	uint16_t sqb_count = CNXK_NIX_TX_MAX_SQB;
 	struct flow_pre_l2_size_info pre_l2_info;
-	uint16_t ipsec_in_max_spi = BIT(8) - 1;
-	uint16_t ipsec_out_max_sa = BIT(12);
+	uint32_t ipsec_in_max_spi = BIT(8) - 1;
+	uint32_t ipsec_out_max_sa = BIT(12);
 	uint16_t flow_prealloc_size = 1;
 	uint16_t switch_header_type = 0;
 	uint16_t flow_max_priority = 3;
 	uint16_t force_inb_inl_dev = 0;
 	uint16_t outb_nb_crypto_qs = 1;
+	uint32_t ipsec_in_min_spi = 0;
 	uint16_t outb_nb_desc = 8200;
 	struct sdp_channel sdp_chan;
 	uint16_t rss_tag_as_xor = 0;
@@ -284,8 +292,10 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
 	rte_kvargs_process(kvlist, CNXK_RSS_TAG_AS_XOR, &parse_flag,
 			   &rss_tag_as_xor);
 	rte_kvargs_process(kvlist, CNXK_LOCK_RX_CTX, &parse_flag, &lock_rx_ctx);
+	rte_kvargs_process(kvlist, CNXK_IPSEC_IN_MIN_SPI,
+			   &parse_ipsec_in_spi_range, &ipsec_in_min_spi);
 	rte_kvargs_process(kvlist, CNXK_IPSEC_IN_MAX_SPI,
-			   &parse_ipsec_in_max_spi, &ipsec_in_max_spi);
+			   &parse_ipsec_in_spi_range, &ipsec_in_max_spi);
 	rte_kvargs_process(kvlist, CNXK_IPSEC_OUT_MAX_SA,
 			   &parse_ipsec_out_max_sa, &ipsec_out_max_sa);
 	rte_kvargs_process(kvlist, CNXK_OUTB_NB_DESC, &parse_outb_nb_desc,
@@ -307,6 +317,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
 	dev->outb.max_sa = ipsec_out_max_sa;
 	dev->outb.nb_desc = outb_nb_desc;
 	dev->outb.nb_crypto_qs = outb_nb_crypto_qs;
+	dev->nix.ipsec_in_min_spi = ipsec_in_min_spi;
 	dev->nix.ipsec_in_max_spi = ipsec_in_max_spi;
 	dev->nix.ipsec_out_max_sa = ipsec_out_max_sa;
 	dev->nix.rss_tag_as_xor = !!rss_tag_as_xor;
diff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c
index ea204ca..3831889 100644
--- a/drivers/net/cnxk/cnxk_ethdev_sec.c
+++ b/drivers/net/cnxk/cnxk_ethdev_sec.c
@@ -5,6 +5,7 @@
 #include <cnxk_ethdev.h>
 
 #define CNXK_NIX_INL_SELFTEST	      "selftest"
+#define CNXK_NIX_INL_IPSEC_IN_MIN_SPI "ipsec_in_min_spi"
 #define CNXK_NIX_INL_IPSEC_IN_MAX_SPI "ipsec_in_max_spi"
 #define CNXK_INL_CPT_CHANNEL	      "inl_cpt_channel"
 
@@ -119,14 +120,17 @@ struct rte_security_ops cnxk_eth_sec_ops = {
 };
 
 static int
-parse_ipsec_in_max_spi(const char *key, const char *value, void *extra_args)
+parse_ipsec_in_spi_range(const char *key, const char *value, void *extra_args)
 {
 	RTE_SET_USED(key);
 	uint32_t val;
 
-	val = atoi(value);
+	errno = 0;
+	val = strtoul(value, NULL, 0);
+	if (errno)
+		val = 0;
 
-	*(uint16_t *)extra_args = val;
+	*(uint32_t *)extra_args = val;
 
 	return 0;
 }
@@ -169,6 +173,7 @@ nix_inl_parse_devargs(struct rte_devargs *devargs,
 		      struct roc_nix_inl_dev *inl_dev)
 {
 	uint32_t ipsec_in_max_spi = BIT(8) - 1;
+	uint32_t ipsec_in_min_spi = 0;
 	struct inl_cpt_channel cpt_channel;
 	struct rte_kvargs *kvlist;
 	uint8_t selftest = 0;
@@ -184,13 +189,16 @@ nix_inl_parse_devargs(struct rte_devargs *devargs,
 
 	rte_kvargs_process(kvlist, CNXK_NIX_INL_SELFTEST, &parse_selftest,
 			   &selftest);
+	rte_kvargs_process(kvlist, CNXK_NIX_INL_IPSEC_IN_MIN_SPI,
+			   &parse_ipsec_in_spi_range, &ipsec_in_min_spi);
 	rte_kvargs_process(kvlist, CNXK_NIX_INL_IPSEC_IN_MAX_SPI,
-			   &parse_ipsec_in_max_spi, &ipsec_in_max_spi);
+			   &parse_ipsec_in_spi_range, &ipsec_in_max_spi);
 	rte_kvargs_process(kvlist, CNXK_INL_CPT_CHANNEL, &parse_inl_cpt_channel,
 			   &cpt_channel);
 	rte_kvargs_free(kvlist);
 
 null_devargs:
+	inl_dev->ipsec_in_min_spi = ipsec_in_min_spi;
 	inl_dev->ipsec_in_max_spi = ipsec_in_max_spi;
 	inl_dev->selftest = selftest;
 	inl_dev->channel = cpt_channel.channel;
diff --git a/drivers/net/cnxk/cnxk_lookup.c b/drivers/net/cnxk/cnxk_lookup.c
index 4eb1ecf..f36fb8f 100644
--- a/drivers/net/cnxk/cnxk_lookup.c
+++ b/drivers/net/cnxk/cnxk_lookup.c
@@ -337,7 +337,8 @@ cnxk_nix_lookup_mem_sa_base_set(struct cnxk_eth_dev *dev)
 	if (!sa_base)
 		return -ENOTSUP;
 
-	sa_w = plt_log2_u32(dev->nix.ipsec_in_max_spi + 1);
+	sa_w = plt_log2_u32(dev->nix.ipsec_in_max_spi + 1 -
+			    dev->nix.ipsec_in_min_spi);
 
 	/* Set SA Base in lookup mem */
 	sa_base_tbl = (uintptr_t)lookup_mem;
-- 
2.8.4

[PATCH v2 20/21] net/cnxk: add option to override outbound inline SA IV

[Nithin Dabilpuram]

Add option to override outbound inline SA IV for debug
purposes via environment variable. User can set env variable as:
export CN10K_ETH_SEC_IV_OVR="0x0, 0x0,..."

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 drivers/net/cnxk/cn10k_ethdev_sec.c | 62 +++++++++++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c
index a2a53c1..a514345 100644
--- a/drivers/net/cnxk/cn10k_ethdev_sec.c
+++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
@@ -252,6 +252,63 @@ cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args)
 	cnxk_pktmbuf_free_no_cache(mbuf);
 }
 
+static void
+outb_dbg_iv_update(struct roc_ot_ipsec_outb_sa *outb_sa, const char *__iv_str)
+{
+	uint8_t *iv_dbg = outb_sa->iv.iv_dbg;
+	char *iv_str = strdup(__iv_str);
+	char *iv_b = NULL, len = 16;
+	char *save;
+	int i;
+
+	if (!iv_str)
+		return;
+
+	if (outb_sa->w2.s.enc_type == ROC_IE_OT_SA_ENC_AES_GCM ||
+	    outb_sa->w2.s.enc_type == ROC_IE_OT_SA_ENC_AES_CTR ||
+	    outb_sa->w2.s.enc_type == ROC_IE_OT_SA_ENC_AES_CCM ||
+	    outb_sa->w2.s.auth_type == ROC_IE_OT_SA_AUTH_AES_GMAC) {
+		memset(outb_sa->iv.s.iv_dbg1, 0, sizeof(outb_sa->iv.s.iv_dbg1));
+		memset(outb_sa->iv.s.iv_dbg2, 0, sizeof(outb_sa->iv.s.iv_dbg2));
+
+		iv_dbg = outb_sa->iv.s.iv_dbg1;
+		for (i = 0; i < 4; i++) {
+			iv_b = strtok_r(i ? NULL : iv_str, ",", &save);
+			if (!iv_b)
+				break;
+			iv_dbg[i] = strtoul(iv_b, NULL, 0);
+		}
+		*(uint32_t *)iv_dbg = rte_be_to_cpu_32(*(uint32_t *)iv_dbg);
+
+		iv_dbg = outb_sa->iv.s.iv_dbg2;
+		for (i = 0; i < 4; i++) {
+			iv_b = strtok_r(NULL, ",", &save);
+			if (!iv_b)
+				break;
+			iv_dbg[i] = strtoul(iv_b, NULL, 0);
+		}
+		*(uint32_t *)iv_dbg = rte_be_to_cpu_32(*(uint32_t *)iv_dbg);
+
+	} else {
+		iv_dbg = outb_sa->iv.iv_dbg;
+		memset(iv_dbg, 0, sizeof(outb_sa->iv.iv_dbg));
+
+		for (i = 0; i < len; i++) {
+			iv_b = strtok_r(i ? NULL : iv_str, ",", &save);
+			if (!iv_b)
+				break;
+			iv_dbg[i] = strtoul(iv_b, NULL, 0);
+		}
+		*(uint64_t *)iv_dbg = rte_be_to_cpu_64(*(uint64_t *)iv_dbg);
+		*(uint64_t *)&iv_dbg[8] =
+			rte_be_to_cpu_64(*(uint64_t *)&iv_dbg[8]);
+	}
+
+	/* Update source of IV */
+	outb_sa->w2.s.iv_src = ROC_IE_OT_SA_IV_SRC_FROM_SA;
+	free(iv_str);
+}
+
 static int
 cn10k_eth_sec_session_create(void *device,
 			     struct rte_security_session_conf *conf,
@@ -390,6 +447,7 @@ cn10k_eth_sec_session_create(void *device,
 		struct cn10k_outb_priv_data *outb_priv;
 		struct cnxk_ipsec_outb_rlens *rlens;
 		uint64_t sa_base = dev->outb.sa_base;
+		const char *iv_str;
 		uint32_t sa_idx;
 
 		PLT_STATIC_ASSERT(sizeof(struct cn10k_outb_priv_data) <
@@ -416,6 +474,10 @@ cn10k_eth_sec_session_create(void *device,
 			goto mempool_put;
 		}
 
+		iv_str = getenv("CN10K_ETH_SEC_IV_OVR");
+		if (iv_str)
+			outb_dbg_iv_update(outb_sa_dptr, iv_str);
+
 		/* Save userdata */
 		outb_priv->userdata = conf->userdata;
 		outb_priv->sa_idx = sa_idx;
-- 
2.8.4

[PATCH v2 21/21] doc: add table for environment variables used by cnxk

[Nithin Dabilpuram]

Add table for environment variables used by cnxk drivers.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
---
 doc/guides/platform/cnxk.rst | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst
index 97e38c8..1cce2f9 100644
--- a/doc/guides/platform/cnxk.rst
+++ b/doc/guides/platform/cnxk.rst
@@ -606,3 +606,24 @@ CN10K:
    if Marvell toolchain is available then it can be used by overriding the
    c, cpp, ar, strip ``binaries`` attributes to respective Marvell
    toolchain binaries in ``config/arm/arm64_cn10k_linux_gcc`` file.
+
+Environment Variables
+~~~~~~~~~~~~~~~~~~~~~
+
+.. table:: cnxk environment variables
+
+   +---+-----------------------------+-----------------------------------------+
+   | # | Variable name               | Usage                                   |
+   +===+=============================+=========================================+
+   | 1 | BPHY_INTR_MLOCK_DISABLE     | When defined disables memory locking in |
+   |   |                             | BPHY environment.                       |
+   +---+-----------------------------+-----------------------------------------+
+   | 2 | ROC_CN10K_MBOX_TIMEOUT      | When set, overrides MBOX timeout by     |
+   |   | ROC_MBOX_TIMEOUT            | value in milli seconds.                 |
+   +---+-----------------------------+-----------------------------------------+
+   | 3 | CN10K_ETH_SEC_IV_OVR        | When set, overrides outbound inline SA  |
+   |   |                             | IV in CN10K. By default IV is generated |
+   |   |                             | by HW. Format of variable is string     |
+   |   |                             | of comma separated one byte values as   |
+   |   |                             | for ex: "0x0, 0x10, 0x20, ..."          |
+   +---+-----------------------------+-----------------------------------------+
-- 
2.8.4

Re: [PATCH v2 21/21] doc: add table for environment variables used by cnxk

[Thomas Monjalon]

22/02/2022 20:35, Nithin Dabilpuram:
> Add table for environment variables used by cnxk drivers.
> 
> Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
> ---
> +.. table:: cnxk environment variables
> +
> +   +---+-----------------------------+-----------------------------------------+
> +   | # | Variable name               | Usage                                   |
> +   +===+=============================+=========================================+
> +   | 1 | BPHY_INTR_MLOCK_DISABLE     | When defined disables memory locking in |
> +   |   |                             | BPHY environment.                       |
> +   +---+-----------------------------+-----------------------------------------+
> +   | 2 | ROC_CN10K_MBOX_TIMEOUT      | When set, overrides MBOX timeout by     |
> +   |   | ROC_MBOX_TIMEOUT            | value in milli seconds.                 |
> +   +---+-----------------------------+-----------------------------------------+
> +   | 3 | CN10K_ETH_SEC_IV_OVR        | When set, overrides outbound inline SA  |
> +   |   |                             | IV in CN10K. By default IV is generated |
> +   |   |                             | by HW. Format of variable is string     |
> +   |   |                             | of comma separated one byte values as   |
> +   |   |                             | for ex: "0x0, 0x10, 0x20, ..."          |
> +   +---+-----------------------------+-----------------------------------------+

Using tables for such list is a bad idea.
The source code is constrained in a small column,
and the HTML rendering is constrained by the page width.
I recommend switching to the definition list syntax
which has a nice rendering for such definitions.

Example:
``BPHY_INTR_MLOCK_DISABLE``
   Disable memory locking in BPHY environment.

See https://www.sphinx-doc.org/en/master/usage/restructuredtext/basics.html#lists-and-quote-like-blocks

Re: [PATCH v2 21/21] doc: add table for environment variables used by cnxk

[Jerin Jacob]

On Sat, Feb 26, 2022 at 2:52 PM Thomas Monjalon <thomas@monjalon.net> wrote:
>
> 22/02/2022 20:35, Nithin Dabilpuram:
> > Add table for environment variables used by cnxk drivers.
> >
> > Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
> > ---
> > +.. table:: cnxk environment variables
> > +
> > +   +---+-----------------------------+-----------------------------------------+
> > +   | # | Variable name               | Usage                                   |
> > +   +===+=============================+=========================================+
> > +   | 1 | BPHY_INTR_MLOCK_DISABLE     | When defined disables memory locking in |
> > +   |   |                             | BPHY environment.                       |
> > +   +---+-----------------------------+-----------------------------------------+
> > +   | 2 | ROC_CN10K_MBOX_TIMEOUT      | When set, overrides MBOX timeout by     |
> > +   |   | ROC_MBOX_TIMEOUT            | value in milli seconds.                 |
> > +   +---+-----------------------------+-----------------------------------------+
> > +   | 3 | CN10K_ETH_SEC_IV_OVR        | When set, overrides outbound inline SA  |
> > +   |   |                             | IV in CN10K. By default IV is generated |
> > +   |   |                             | by HW. Format of variable is string     |
> > +   |   |                             | of comma separated one byte values as   |
> > +   |   |                             | for ex: "0x0, 0x10, 0x20, ..."          |
> > +   +---+-----------------------------+-----------------------------------------+
>
> Using tables for such list is a bad idea.
> The source code is constrained in a small column,
> and the HTML rendering is constrained by the page width.
> I recommend switching to the definition list syntax
> which has a nice rendering for such definitions.
>
> Example:
> ``BPHY_INTR_MLOCK_DISABLE``
>    Disable memory locking in BPHY environment.

Sure, You can remove this doc update while merging to the main tree.
We will submit a separate patch for updating this document
based on your suggestion.

>
> See https://www.sphinx-doc.org/en/master/usage/restructuredtext/basics.html#lists-and-quote-like-blocks


>
>

Re: [PATCH v2 21/21] doc: add table for environment variables used by cnxk

[Thomas Monjalon]

26/02/2022 10:37, Jerin Jacob:
> On Sat, Feb 26, 2022 at 2:52 PM Thomas Monjalon <thomas@monjalon.net> wrote:
> >
> > 22/02/2022 20:35, Nithin Dabilpuram:
> > > Add table for environment variables used by cnxk drivers.
> > >
> > > Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
> > > ---
> > > +.. table:: cnxk environment variables
> > > +
> > > +   +---+-----------------------------+-----------------------------------------+
> > > +   | # | Variable name               | Usage                                   |
> > > +   +===+=============================+=========================================+
> > > +   | 1 | BPHY_INTR_MLOCK_DISABLE     | When defined disables memory locking in |
> > > +   |   |                             | BPHY environment.                       |
> > > +   +---+-----------------------------+-----------------------------------------+
> > > +   | 2 | ROC_CN10K_MBOX_TIMEOUT      | When set, overrides MBOX timeout by     |
> > > +   |   | ROC_MBOX_TIMEOUT            | value in milli seconds.                 |
> > > +   +---+-----------------------------+-----------------------------------------+
> > > +   | 3 | CN10K_ETH_SEC_IV_OVR        | When set, overrides outbound inline SA  |
> > > +   |   |                             | IV in CN10K. By default IV is generated |
> > > +   |   |                             | by HW. Format of variable is string     |
> > > +   |   |                             | of comma separated one byte values as   |
> > > +   |   |                             | for ex: "0x0, 0x10, 0x20, ..."          |
> > > +   +---+-----------------------------+-----------------------------------------+
> >
> > Using tables for such list is a bad idea.
> > The source code is constrained in a small column,
> > and the HTML rendering is constrained by the page width.
> > I recommend switching to the definition list syntax
> > which has a nice rendering for such definitions.
> >
> > Example:
> > ``BPHY_INTR_MLOCK_DISABLE``
> >    Disable memory locking in BPHY environment.
> 
> Sure, You can remove this doc update while merging to the main tree.
> We will submit a separate patch for updating this document
> based on your suggestion.

It has been squashed in a commit adding the third variable,
so yes it can be dropped and submitted again for the 3 variables.

Re: [PATCH v2 01/21] common/cnxk: increase SMQ resource count

[Jerin Jacob]

On Wed, Feb 23, 2022 at 1:05 AM Nithin Dabilpuram
<ndabilpuram@marvell.com> wrote:
>
> From: Satha Rao <skoteshwar@marvell.com>
>
> CN10K supports up to 832 resources at SMQ level, so increase
> bitmap count to 1024.
>
> Signed-off-by: Satha Rao <skoteshwar@marvell.com>
> ---
>
> v2:
> - Addressed comments from Jerin on patches 1/20, 3/20, 7/20,
>   8/20, 10/20, 11/20, 15/20 and 20/20.
> - Added another patch to update documentation on environment variables
> - Fixed functional issues with patch 18/20.

Squashed 21/21 patch into 20/21.

Series Acked-by: Jerin Jacob <jerinj@marvell.com>
Series applied to dpdk-next-net-mrvl/for-next-net. Thanks.

>
>  drivers/common/cnxk/roc_nix_priv.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h
> index deb2a6b..4d2a7d8 100644
> --- a/drivers/common/cnxk/roc_nix_priv.h
> +++ b/drivers/common/cnxk/roc_nix_priv.h
> @@ -31,7 +31,7 @@ struct nix_qint {
>  };
>
>  /* Traffic Manager */
> -#define NIX_TM_MAX_HW_TXSCHQ 512
> +#define NIX_TM_MAX_HW_TXSCHQ 1024
>  #define NIX_TM_HW_ID_INVALID UINT32_MAX
>
>  /* TM flags */
> --
> 2.8.4
>