From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8ED0BA034F; Mon, 7 Feb 2022 08:30:37 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B76DD41153; Mon, 7 Feb 2022 08:30:17 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 22B0F410FD for ; Mon, 7 Feb 2022 08:30:15 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 216LsOhG030467 for ; Sun, 6 Feb 2022 23:30:14 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=TYz3/d/oHTy99bOVXKaHoQ8nPS+wG+4f4HUoF2t6Hj0=; b=jQ3Z2NqYoBPP15KBneeVyImorbPa5kWRaXG7o3MhxVmfpOCtUFllYQTj53utOCJag0VG Ww597VBamSzlKKEtDbrREnDrQAUL9jAbx9c7XTQtisYAUjIlzTsRh2bCweOegxXGTQcy +3q/iS94B9wZvcmM7QRB7+sXS+Khhs6dzHBMrEK8wz9ztjqln+jqU6yNK/GCQkwH07dK y+iVyf54Ulkco9Tkr1XHD45/0UbIS87+wMtL3yy3/eS00wCQpasWH8jUT3GXFzHXQDIN oygnGPDI93EhhlmuUVvHJfHrtjW6welkexajGgBR06VD+bZoPwHfckxArfPxLLVr8hyT 6w== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3e1smr4p28-12 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sun, 06 Feb 2022 23:30:14 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sun, 6 Feb 2022 23:30:10 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Sun, 6 Feb 2022 23:30:10 -0800 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id B24DC3F7068; Sun, 6 Feb 2022 23:30:07 -0800 (PST) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: Subject: [PATCH 08/20] common/cnxk: use SSO time counter threshold for IRQ Date: Mon, 7 Feb 2022 12:59:20 +0530 Message-ID: <20220207072932.22409-8-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220207072932.22409-1-ndabilpuram@marvell.com> References: <20220207072932.22409-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: LSWiYU6N6IAM2twe6vTH0kjp7V0dP79y X-Proofpoint-ORIG-GUID: LSWiYU6N6IAM2twe6vTH0kjp7V0dP79y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-07_02,2022-02-03_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Enable time counter based threshold for raising SSO EXE_INT instead of IAQ threshold. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_nix_inl_dev_irq.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_inl_dev_irq.c b/drivers/common/cnxk/roc_nix_inl_dev_irq.c index d758e0c..8a0cb74 100644 --- a/drivers/common/cnxk/roc_nix_inl_dev_irq.c +++ b/drivers/common/cnxk/roc_nix_inl_dev_irq.c @@ -5,6 +5,8 @@ #include "roc_api.h" #include "roc_priv.h" +#define WORK_LIMIT 1000 + static void nix_inl_sso_work_cb(struct nix_inl_dev *inl_dev) { @@ -15,6 +17,7 @@ nix_inl_sso_work_cb(struct nix_inl_dev *inl_dev) __uint128_t get_work; uint64_t u64[2]; } gw; + uint16_t cnt = 0; uint64_t work; again: @@ -33,7 +36,9 @@ nix_inl_sso_work_cb(struct nix_inl_dev *inl_dev) else plt_warn("Undelivered inl dev work gw0: %p gw1: %p", (void *)gw.u64[0], (void *)gw.u64[1]); - goto again; + cnt++; + if (cnt < WORK_LIMIT) + goto again; } plt_atomic_thread_fence(__ATOMIC_ACQ_REL); @@ -138,8 +143,10 @@ nix_inl_sso_register_irqs(struct nix_inl_dev *inl_dev) /* Enable hw interrupt */ plt_write64(~0ull, sso_base + SSO_LF_GGRP_INT_ENA_W1S); - /* Setup threshold for work exec interrupt to 1 wqe in IAQ */ - plt_write64(0x1ull, sso_base + SSO_LF_GGRP_INT_THR); + /* Setup threshold for work exec interrupt to 100us timeout + * based on time counter. + */ + plt_write64(BIT_ULL(63) | 10ULL << 48, sso_base + SSO_LF_GGRP_INT_THR); return rc; } -- 2.8.4