From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 347C5A00BE; Thu, 10 Feb 2022 17:30:15 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D21344117E; Thu, 10 Feb 2022 17:29:59 +0100 (CET) Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2044.outbound.protection.outlook.com [40.107.237.44]) by mails.dpdk.org (Postfix) with ESMTP id C485641176 for ; Thu, 10 Feb 2022 17:29:56 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=B+R7MkEjVxOrAEgdVxIddBaTs/kWx5zt9c4COlROGLa65R2zE1zWLhbuVqOZ1lkMz82ntrJ4pdqcOHlZ/wKKDNHcvoHp0sTjJou950nvXkyOUkQ/V31KiJ1zd7K51jWUW8BWVJQjseBipmbDagrawx54WpnelbDEgyz8zeIady1Rb7JQs7qqV77VRfn6HgZkCwejqSOrmmlJCmsRX4Ih6QbeM/6cgE1QIgWZdR7KYjOzPNxFY2CktMjN2VjVeniy8k7ZrWsV+1eNjCQolmH4e+gB6Tt0U1CzLYDHpkLRa5r+dv+TJmBu2tLJ+wL5pWMbRwooZ1PMz4pZmK1lwQ4gSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=4KQbJWAdT70l2d94zQ9RC3Br6f5HBuEv8zojsfKKT4c=; b=CIJOks1M0LwSa1NX7RFq3KGjtJaurgt05p1i9hcr+5ZizVCI6cUptSDR/LrozBWZ3HB862vn2OWupsgfBxfc30/TGGCDXsAeABr7kdpruFN5mjSmG6ZF3xl02oYWZDN2Yo0cARidvmPTEcVsFMmBC446a74dx7BLM73+N39PQc0hXhwGbLWg6GkekobhrH/VOMkpXrZ+C4Mq5d15EgWtc89qrQhUDJBAgykg31T7E5jfugeeQmJs5NA4+ztLn51mQoIY1oNbjUGXK/f5INWZUdS0JXtk+lj1f3afCicSAPCxivB++mV8y/Cn1dO1rejh8ctuJYYZAtyQkNX3bJnYRg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.238) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=4KQbJWAdT70l2d94zQ9RC3Br6f5HBuEv8zojsfKKT4c=; b=WdD9xeGFPVc/A75wuSTupE5EX74tXwwsbdAGGkyZfmakEAXbmO/vD0JywHqhaWU+fJFhr7ireJmFc4NpkMxOV5+NXcjElEPX4vvYK/UVSOXMGZMwOLLX7Hey1/wMTADlL4ZQEgqU3nYaPbOEoZ+9WyLILiv9aXJEPzFAEWdnOouy+/gRfCyZcWj+ynrP9t24xWtZtBxb2MvnQCcToewCcohbneETNBQRmu+Bu4/RJYxcrnMLlVCSNOUt6apjwbyZp70bDPpicVJOTPxwXUUd4h0fvD3hOnC6kcKSIk7pbFGlyGFNnmWIFtsmfZoK9zU5/a4j816jleP1J8xm636lhA== Received: from DM6PR03CA0091.namprd03.prod.outlook.com (2603:10b6:5:333::24) by PH0PR12MB5420.namprd12.prod.outlook.com (2603:10b6:510:e8::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4951.14; Thu, 10 Feb 2022 16:29:55 +0000 Received: from DM6NAM11FT008.eop-nam11.prod.protection.outlook.com (2603:10b6:5:333:cafe::ce) by DM6PR03CA0091.outlook.office365.com (2603:10b6:5:333::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4975.11 via Frontend Transport; Thu, 10 Feb 2022 16:29:54 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.238) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.238 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.238; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.238) by DM6NAM11FT008.mail.protection.outlook.com (10.13.172.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4975.11 via Frontend Transport; Thu, 10 Feb 2022 16:29:54 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL105.nvidia.com (10.27.9.14) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 10 Feb 2022 16:29:53 +0000 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9; Thu, 10 Feb 2022 08:29:51 -0800 From: Suanming Mou To: , CC: , , Subject: [PATCH 04/13] net/mlx5: add pattern template management Date: Thu, 10 Feb 2022 18:29:17 +0200 Message-ID: <20220210162926.20436-5-suanmingm@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20220210162926.20436-1-suanmingm@nvidia.com> References: <20220210162926.20436-1-suanmingm@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e20e2963-cdf0-4c4b-4aa1-08d9ecb291d7 X-MS-TrafficTypeDiagnostic: PH0PR12MB5420:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:901; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: itvO0DMQ/8BrglrNCrjRoj50rr7bJALGGeZdFti6pRUC1dRzI7LDXxxHMhMw58S7WGScsnBbZdGruFqaMN4dfYtFXKaMlCQMEg3QEy0MciSmbgZ6DYZ/z3M4C+ihD97hqaCPUH5Xw1kFbrzCsghiGlXuLRWiW9SrlBYzR4GRHY0DA3hn3atY+AqvT6gkbqp5m6cTkDwwNQpMICx3tzWdQWZ5P2OJQH/FPFkmrbBp9l2HlYj/rX0PjWAxqnyYVT6K/tXmx/oGX9ErLttcEICNX2vBPD8faxtkTlL0VhbHXy7r81kxgRT3nnrR9TA4qUok/qAH87uVBDvhPW0RELtTeoeTN/q+cYuyIq+LykznGcSpgkjd8viPZvj1/NTZyLDzQwd7XohIoOjn7GKfVIchCAR+wYemetf1QWeIC3rCY8M13EDrD6MxpwlgpsMA/9bEvZlUAaxtpmxBZzaf8lRbwxZztriYrHa2SMIRlMHqauxJpCfEnyKV7eZqwX+MzixiRvyoNpiq7q4/W9yla9rLQ9cpCRuGBmVmlb6KmlKVjfHGmxh60IjhKg6GhQylP7U+V9iZpPvncz8OaxjUQiXEKvRznJ9h/MIOl68qHTcX4Gz06tBM+JLbOC6WKXOUW7v8UFpzSe3OPlZj3bbw9rqSI5+Wcpco/dCuJImPg8hQ9j5mGdmy4FZDOfOxSHxV3P7A+9Hob0c6mYYI+3gtttlpSQ== X-Forefront-Antispam-Report: CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(86362001)(316002)(8936002)(54906003)(2906002)(6636002)(8676002)(508600001)(82310400004)(2616005)(40460700003)(110136005)(356005)(6286002)(1076003)(26005)(186003)(336012)(426003)(16526019)(70586007)(5660300002)(47076005)(36860700001)(70206006)(55016003)(83380400001)(81166007)(6666004)(4326008)(7696005)(36756003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Feb 2022 16:29:54.3056 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e20e2963-cdf0-4c4b-4aa1-08d9ecb291d7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT008.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5420 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The pattern template defines flows that have the same matching fields but with different matching values. For example, matching on 5 tuple TCP flow, the template will be (eth(null) + IPv4(source + dest) + TCP(s_port + d_port) while the values for each rule will be different. Due to the pattern template can be used in different domains, the items will only be cached in pattern template create stage, while the template is binded to a dedicated table, the HW criteria will be created and saved to the table. And different tables may create the same criteria and will not shared between each other in order to have better performance. This commit adds pattern template management. Signed-off-by: Suanming Mou --- drivers/net/mlx5/mlx5.h | 2 + drivers/net/mlx5/mlx5_flow.c | 64 +++++++++++++++++++++++++ drivers/net/mlx5/mlx5_flow.h | 20 ++++++++ drivers/net/mlx5/mlx5_flow_hw.c | 82 +++++++++++++++++++++++++++++++++ 4 files changed, 168 insertions(+) diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 31a13ca69a..96048ad0ea 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1500,6 +1500,8 @@ struct mlx5_priv { struct mlx5_flex_item flex_item[MLX5_PORT_FLEX_ITEM_NUM]; /* Flex items have been created on the port. */ uint32_t flex_item_map; /* Map of allocated flex item elements. */ + /* Item template list. */ + LIST_HEAD(flow_hw_itt, rte_flow_pattern_template) flow_hw_itt; struct mlx5dr_context *dr_ctx; /**< HW steering DR context. */ uint32_t nb_queue; /* HW steering queue number. */ /* HW steering queue polling mechanism job descriptor LIFO. */ diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 5ff96642b4..27a40a9627 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -812,6 +812,17 @@ mlx5_flow_port_configure(struct rte_eth_dev *dev, const struct rte_flow_queue_attr *queue_attr[], struct rte_flow_error *err); +static struct rte_flow_pattern_template * +mlx5_flow_pattern_template_create(struct rte_eth_dev *dev, + const struct rte_flow_pattern_template_attr *attr, + const struct rte_flow_item items[], + struct rte_flow_error *error); + +static int +mlx5_flow_pattern_template_destroy(struct rte_eth_dev *dev, + struct rte_flow_pattern_template *template, + struct rte_flow_error *error); + static const struct rte_flow_ops mlx5_flow_ops = { .validate = mlx5_flow_validate, .create = mlx5_flow_create, @@ -833,6 +844,8 @@ static const struct rte_flow_ops mlx5_flow_ops = { .flex_item_create = mlx5_flow_flex_item_create, .flex_item_release = mlx5_flow_flex_item_release, .configure = mlx5_flow_port_configure, + .pattern_template_create = mlx5_flow_pattern_template_create, + .pattern_template_destroy = mlx5_flow_pattern_template_destroy, }; /* Tunnel information. */ @@ -7851,6 +7864,57 @@ mlx5_flow_port_configure(struct rte_eth_dev *dev, return fops->configure(dev, port_attr, nb_queue, queue_attr, err); } +/** + * Create flow item template. + * + * @param[in] dev + * Pointer to the rte_eth_dev structure. + * @param[in] attr + * Pointer to the item template attributes. + * @param[in] items + * The template item pattern. + * @param[out] error + * Pointer to error structure. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +static struct rte_flow_pattern_template * +mlx5_flow_pattern_template_create(struct rte_eth_dev *dev, + const struct rte_flow_pattern_template_attr *attr, + const struct rte_flow_item items[], + struct rte_flow_error *error) +{ + const struct mlx5_flow_driver_ops *fops = + flow_get_drv_ops(MLX5_FLOW_TYPE_HW); + + return fops->pattern_template_create(dev, attr, items, error); +} + +/** + * Destroy flow item template. + * + * @param[in] dev + * Pointer to the rte_eth_dev structure. + * @param[in] template + * Pointer to the item template to be destroyed. + * @param[out] error + * Pointer to error structure. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +static int +mlx5_flow_pattern_template_destroy(struct rte_eth_dev *dev, + struct rte_flow_pattern_template *template, + struct rte_flow_error *error) +{ + const struct mlx5_flow_driver_ops *fops = + flow_get_drv_ops(MLX5_FLOW_TYPE_HW); + + return fops->pattern_template_destroy(dev, template, error); +} + /** * Allocate a new memory for the counter values wrapped by all the needed * management. diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 731478ff05..88102f0991 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -1015,6 +1015,15 @@ struct rte_flow { uint32_t geneve_tlv_option; /**< Holds Geneve TLV option id. > */ } __rte_packed; +/* Flow item template struct. */ +struct rte_flow_pattern_template { + LIST_ENTRY(rte_flow_pattern_template) next; + /* Template attributes. */ + struct rte_flow_pattern_template_attr attr; + struct mlx5dr_match_template *mt; /* mlx5 match template. */ + uint32_t refcnt; /* Reference counter. */ +}; + /* * Define list of valid combinations of RX Hash fields * (see enum ibv_rx_hash_fields). @@ -1263,6 +1272,15 @@ typedef int (*mlx5_flow_port_configure_t) uint16_t nb_queue, const struct rte_flow_queue_attr *queue_attr[], struct rte_flow_error *err); +typedef struct rte_flow_pattern_template *(*mlx5_flow_pattern_template_create_t) + (struct rte_eth_dev *dev, + const struct rte_flow_pattern_template_attr *attr, + const struct rte_flow_item items[], + struct rte_flow_error *error); +typedef int (*mlx5_flow_pattern_template_destroy_t) + (struct rte_eth_dev *dev, + struct rte_flow_pattern_template *template, + struct rte_flow_error *error); struct mlx5_flow_driver_ops { mlx5_flow_validate_t validate; @@ -1302,6 +1320,8 @@ struct mlx5_flow_driver_ops { mlx5_flow_item_release_t item_release; mlx5_flow_item_update_t item_update; mlx5_flow_port_configure_t configure; + mlx5_flow_pattern_template_create_t pattern_template_create; + mlx5_flow_pattern_template_destroy_t pattern_template_destroy; }; /* mlx5_flow.c */ diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 4194f81ee9..c984e520cd 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -12,6 +12,81 @@ const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops; +/** + * Create flow item template. + * + * @param[in] dev + * Pointer to the rte_eth_dev structure. + * @param[in] attr + * Pointer to the item template attributes. + * @param[in] items + * The template item pattern. + * @param[out] error + * Pointer to error structure. + * + * @return + * Item template pointer on success, NULL otherwise and rte_errno is set. + */ +static struct rte_flow_pattern_template * +flow_hw_pattern_template_create(struct rte_eth_dev *dev, + const struct rte_flow_pattern_template_attr *attr, + const struct rte_flow_item items[], + struct rte_flow_error *error) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct rte_flow_pattern_template *it; + + it = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*it), 0, SOCKET_ID_ANY); + if (!it) { + rte_flow_error_set(error, ENOMEM, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "cannot allocate item template"); + return NULL; + } + it->attr = *attr; + it->mt = mlx5dr_match_template_create(items, attr->relaxed_matching); + if (!it->mt) { + mlx5_free(it); + return NULL; + } + __atomic_fetch_add(&it->refcnt, 1, __ATOMIC_RELAXED); + LIST_INSERT_HEAD(&priv->flow_hw_itt, it, next); + return it; +} + +/** + * Destroy flow item template. + * + * @param[in] dev + * Pointer to the rte_eth_dev structure. + * @param[in] template + * Pointer to the item template to be destroyed. + * @param[out] error + * Pointer to error structure. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +static int +flow_hw_pattern_template_destroy(struct rte_eth_dev *dev __rte_unused, + struct rte_flow_pattern_template *template, + struct rte_flow_error *error __rte_unused) +{ + if (__atomic_load_n(&template->refcnt, __ATOMIC_RELAXED) > 1) { + DRV_LOG(WARNING, "Item template %p is still in use.", + (void *)template); + return rte_flow_error_set(error, EBUSY, + RTE_FLOW_ERROR_TYPE_UNSPECIFIED, + NULL, + "item template in using"); + } + LIST_REMOVE(template, next); + claim_zero(mlx5dr_match_template_destroy(template->mt)); + mlx5_free(template); + return 0; +} + /** * Configure port HWS resources. * @@ -128,9 +203,14 @@ void flow_hw_resource_release(struct rte_eth_dev *dev) { struct mlx5_priv *priv = dev->data->dev_private; + struct rte_flow_pattern_template *it; if (!priv->dr_ctx) return; + while (!LIST_EMPTY(&priv->flow_hw_itt)) { + it = LIST_FIRST(&priv->flow_hw_itt); + flow_hw_pattern_template_destroy(dev, it, NULL); + } mlx5_free(priv->hw_q); priv->hw_q = NULL; claim_zero(mlx5dr_context_close(priv->dr_ctx)); @@ -140,6 +220,8 @@ flow_hw_resource_release(struct rte_eth_dev *dev) const struct mlx5_flow_driver_ops mlx5_flow_hw_drv_ops = { .configure = flow_hw_configure, + .pattern_template_create = flow_hw_pattern_template_create, + .pattern_template_destroy = flow_hw_pattern_template_destroy, }; #endif -- 2.25.1