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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.236 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.236; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.236) by BN8NAM11FT020.mail.protection.outlook.com (10.13.176.223) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4975.11 via Frontend Transport; Thu, 10 Feb 2022 16:30:02 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL109.nvidia.com (10.27.9.19) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 10 Feb 2022 16:30:01 +0000 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9; Thu, 10 Feb 2022 08:29:59 -0800 From: Suanming Mou To: , CC: , , Subject: [PATCH 08/13] net/mlx5: add flow flush function Date: Thu, 10 Feb 2022 18:29:21 +0200 Message-ID: <20220210162926.20436-9-suanmingm@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20220210162926.20436-1-suanmingm@nvidia.com> References: <20220210162926.20436-1-suanmingm@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c562f3a3-835f-4065-954b-08d9ecb296ae X-MS-TrafficTypeDiagnostic: BN6PR1201MB0036:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:186; 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SFS:(13230001)(4636009)(40470700004)(36840700001)(46966006)(110136005)(6636002)(4326008)(54906003)(8676002)(356005)(70586007)(316002)(81166007)(5660300002)(82310400004)(2906002)(86362001)(70206006)(8936002)(55016003)(7696005)(6666004)(47076005)(508600001)(2616005)(16526019)(186003)(6286002)(83380400001)(26005)(40460700003)(336012)(426003)(36860700001)(1076003)(36756003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Feb 2022 16:30:02.4274 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c562f3a3-835f-4065-954b-08d9ecb296ae X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR1201MB0036 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org In case port restarting, all created flows should be flushed. This commit adds the flow flush helper function. Signed-off-by: Suanming Mou --- drivers/net/mlx5/mlx5_flow.c | 8 +++ drivers/net/mlx5/mlx5_flow_hw.c | 117 ++++++++++++++++++++++++++++++++ 2 files changed, 125 insertions(+) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index b48a3af0fb..9ac96ac979 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -6991,6 +6991,14 @@ mlx5_flow_list_flush(struct rte_eth_dev *dev, enum mlx5_flow_type type, uint32_t num_flushed = 0, fidx = 1; struct rte_flow *flow; +#ifdef HAVE_IBV_FLOW_DV_SUPPORT + if (priv->config.dv_flow_en == 2 && + type == MLX5_FLOW_TYPE_GEN) { + flow_hw_q_flow_flush(dev, NULL); + return; + } +#endif + MLX5_IPOOL_FOREACH(priv->flows[type], fidx, flow) { flow_list_destroy(dev, type, fidx); num_flushed++; diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index a74825312f..dcf72ab89f 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -377,6 +377,123 @@ flow_hw_q_push(struct rte_eth_dev *dev, MLX5DR_SEND_QUEUE_ACTION_DRAIN); } +/** + * Drain the enqueued flows' completion. + * + * @param[in] dev + * Pointer to the rte_eth_dev structure. + * @param[in] queue + * The queue to pull the flow. + * @param[in] pending_rules + * The pending flow number. + * @param[out] error + * Pointer to error structure. + * + * @return + * 0 on success, negative value otherwise and rte_errno is set. + */ +static int +__flow_hw_pull_comp(struct rte_eth_dev *dev, + uint32_t queue, + uint32_t pending_rules, + struct rte_flow_error *error) +{ +#define BURST_THR 32u + struct rte_flow_q_op_res comp[BURST_THR]; + int ret, i, empty_loop = 0; + + flow_hw_q_push(dev, queue, error); + while (pending_rules) { + ret = flow_hw_q_pull(dev, 0, comp, BURST_THR, error); + if (ret < 0) + return -1; + if (!ret) { + usleep(200); + if (++empty_loop > 5) { + DRV_LOG(WARNING, "No available dequeue, quit."); + break; + } + continue; + } + for (i = 0; i < ret; i++) { + if (comp[i].status == RTE_FLOW_Q_OP_ERROR) + DRV_LOG(WARNING, "Flow flush get error CQE."); + } + if ((uint32_t)ret > pending_rules) { + DRV_LOG(WARNING, "Flow flush get extra CQE."); + return -1; + } + pending_rules -= ret; + empty_loop = 0; + } + return 0; +} + +/** + * Flush created flows. + * + * @param[in] dev + * Pointer to the rte_eth_dev structure. + * @param[out] error + * Pointer to error structure. + * + * @return + * 0 on success, negative value otherwise and rte_errno is set. + */ +int +flow_hw_q_flow_flush(struct rte_eth_dev *dev, + struct rte_flow_error *error) +{ +#define DEFAULT_QUEUE 0 + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_hw_q *hw_q; + struct rte_flow_template_table *tbl; + struct rte_flow_hw *flow; + struct rte_flow_q_ops_attr attr = { + .postpone = 0, + }; + uint32_t pending_rules = 0; + uint32_t queue; + uint32_t fidx; + + /* + * Ensure to push and dequeue all the enqueued flows in case user + * forgot to dequeue. Or the enqueued created flows will be leaked. + * The forgot dequeue will also cause flow flush get extra CQEs as + * expected and pending_rules be minus value. + */ + for (queue = 0; queue < priv->nb_queue; queue++) { + hw_q = &priv->hw_q[queue]; + if (__flow_hw_pull_comp(dev, queue, hw_q->size - hw_q->job_idx, + error)) + return -1; + } + /* Flush flow per-table from DEFAULT_QUEUE. */ + hw_q = &priv->hw_q[DEFAULT_QUEUE]; + LIST_FOREACH(tbl, &priv->flow_hw_tbl, next) { + MLX5_IPOOL_FOREACH(tbl->flow, fidx, flow) { + if (flow_hw_q_flow_destroy(dev, DEFAULT_QUEUE, &attr, + (struct rte_flow *)flow, + error)) + return -1; + pending_rules++; + /* Drain completion with queue size. */ + if (pending_rules >= hw_q->size) { + if (__flow_hw_pull_comp(dev, DEFAULT_QUEUE, + pending_rules, error)) + return -1; + pending_rules = 0; + } + } + } + /* Drain left completion. */ + if (pending_rules && + __flow_hw_pull_comp(dev, DEFAULT_QUEUE, pending_rules, + error)) + return -1; + return 0; +} + /** * Create flow table. * -- 2.25.1