From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DDD9DA00C4; Mon, 14 Feb 2022 05:30:04 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 74D6F40C35; Mon, 14 Feb 2022 05:30:04 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 93B554068C for ; Mon, 14 Feb 2022 05:30:02 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 21DLsDBG008905; Sun, 13 Feb 2022 20:29:59 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=ZtEmtQDcO3zLvuTA6cmZQ0myR8IZpssNH7PfnA3yE6k=; b=eUy+RYZcZOBhq9t9leOT8LATTZgp1M9Z0Ab94dns/2QNhfGjfVXxifbbfgCuPpf5NhG7 24wM4N09PjzgSrXcs5XJ2x/5XyXX6jZbn3+Gpv/6sNP+uWi7PzhHMMzLPlFZKeB/Oj+O wX8Gh2mVJ7Xa7HHOJSXQ6aT7zJ5/117W1RCVdBa6fxovtYHWb3nR7ARU3yNv5HquvXzM vQWFL3Zf9oI5J/8DLedU5u3TzrqQrFkdX/EohlG/fZ6//oW6CgeL9MBjOR1fUN/uALpu M63d97zAwClxfGaeiqane6eaCcIl+2/Cx97MumsizRB+oXgo8krH5y+4wlHVs7J4zctn sA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3e6d9qvnqb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 13 Feb 2022 20:29:58 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 13 Feb 2022 20:29:56 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 13 Feb 2022 20:29:56 -0800 Received: from localhost.localdomain (unknown [10.28.34.33]) by maili.marvell.com (Postfix) with ESMTP id 9CFCD3F7095; Sun, 13 Feb 2022 20:29:54 -0800 (PST) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: , Satheesh Paul Subject: [dpdk-dev] [PATCH v2] drivers: enable keep flow rule device capability for cnxk Date: Mon, 14 Feb 2022 09:59:46 +0530 Message-ID: <20220214042946.1511548-1-psatheesh@marvell.com> X-Mailer: git-send-email 2.25.4 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: 2mtFAv0xO5sropAzoU5P25Wy8yvm5js7 X-Proofpoint-ORIG-GUID: 2mtFAv0xO5sropAzoU5P25Wy8yvm5js7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-14_01,2022-02-11_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Kiran Kumar K Adding changes to enable keep flow rule device capability. With this change, flow rules will be kept across device restart. Signed-off-by: Kiran Kumar K Reviewed-by: Satheesh Paul --- v2: * Allow creating flow rule before device start. drivers/common/cnxk/roc_npc.c | 8 ++++++++ drivers/common/cnxk/roc_npc.h | 2 ++ drivers/common/cnxk/roc_npc_mcam.c | 20 ++++++++++++++++++++ drivers/common/cnxk/roc_npc_priv.h | 1 + drivers/common/cnxk/version.map | 1 + drivers/net/cnxk/cnxk_ethdev.c | 15 +++++++++++++-- drivers/net/cnxk/cnxk_ethdev_ops.c | 4 ++-- 7 files changed, 47 insertions(+), 4 deletions(-) diff --git a/drivers/common/cnxk/roc_npc.c b/drivers/common/cnxk/roc_npc.c index e3961bfbc6..d470f53788 100644 --- a/drivers/common/cnxk/roc_npc.c +++ b/drivers/common/cnxk/roc_npc.c @@ -74,6 +74,14 @@ roc_npc_mcam_alloc_entries(struct roc_npc *roc_npc, int ref_entry, priority, resp_count); } +int +roc_npc_mcam_enable_all_entries(struct roc_npc *roc_npc, bool enable) +{ + struct npc *npc = roc_npc_to_npc_priv(roc_npc); + + return npc_flow_enable_all_entries(npc, enable); +} + int roc_npc_mcam_alloc_entry(struct roc_npc *roc_npc, struct roc_npc_flow *mcam, struct roc_npc_flow *ref_mcam, int prio, diff --git a/drivers/common/cnxk/roc_npc.h b/drivers/common/cnxk/roc_npc.h index b836e264c6..f9e5028cab 100644 --- a/drivers/common/cnxk/roc_npc.h +++ b/drivers/common/cnxk/roc_npc.h @@ -309,6 +309,8 @@ roc_npc_flow_create(struct roc_npc *roc_npc, const struct roc_npc_attr *attr, int __roc_api roc_npc_flow_destroy(struct roc_npc *roc_npc, struct roc_npc_flow *flow); int __roc_api roc_npc_mcam_free_entry(struct roc_npc *roc_npc, uint32_t entry); +int __roc_api roc_npc_mcam_enable_all_entries(struct roc_npc *roc_npc, + bool enable); int __roc_api roc_npc_mcam_alloc_entry(struct roc_npc *roc_npc, struct roc_npc_flow *mcam, struct roc_npc_flow *ref_mcam, int prio, diff --git a/drivers/common/cnxk/roc_npc_mcam.c b/drivers/common/cnxk/roc_npc_mcam.c index b251f643bc..30eceeb883 100644 --- a/drivers/common/cnxk/roc_npc_mcam.c +++ b/drivers/common/cnxk/roc_npc_mcam.c @@ -780,6 +780,26 @@ npc_program_mcam(struct npc *npc, struct npc_parse_state *pst, bool mcam_alloc) return 0; } +int +npc_flow_enable_all_entries(struct npc *npc, bool enable) +{ + struct npc_flow_list *list; + struct roc_npc_flow *flow; + int rc = 0, idx; + + /* Free any MCAM counters and delete flow list */ + for (idx = 0; idx < npc->flow_max_priority; idx++) { + list = &npc->flow_list[idx]; + TAILQ_FOREACH(flow, list, next) { + flow->enable = enable; + rc = npc_mcam_write_entry(npc, flow); + if (rc) + return rc; + } + } + return rc; +} + int npc_flow_free_all_resources(struct npc *npc) { diff --git a/drivers/common/cnxk/roc_npc_priv.h b/drivers/common/cnxk/roc_npc_priv.h index afd11add9a..23e8675253 100644 --- a/drivers/common/cnxk/roc_npc_priv.h +++ b/drivers/common/cnxk/roc_npc_priv.h @@ -413,6 +413,7 @@ int npc_mcam_alloc_entries(struct npc *npc, int ref_mcam, int *alloc_entry, int npc_mcam_ena_dis_entry(struct npc *npc, struct roc_npc_flow *mcam, bool enable); int npc_mcam_write_entry(struct npc *npc, struct roc_npc_flow *mcam); +int npc_flow_enable_all_entries(struct npc *npc, bool enable); int npc_update_parse_state(struct npc_parse_state *pst, struct npc_parse_item_info *info, int lid, int lt, uint8_t flags); diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index ad1b5e8476..75a260f11e 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -312,6 +312,7 @@ INTERNAL { roc_npc_mcam_alloc_entries; roc_npc_mcam_alloc_entry; roc_npc_mcam_clear_counter; + roc_npc_mcam_enable_all_entries; roc_npc_mcam_ena_dis_entry; roc_npc_mcam_free_all_resources; roc_npc_mcam_free_counter; diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 53dfb5eae8..304272acab 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -1407,8 +1407,10 @@ cnxk_nix_dev_stop(struct rte_eth_dev *eth_dev) int count, i, j, rc; void *rxq; - /* Disable switch hdr pkind */ - roc_nix_switch_hdr_set(&dev->nix, 0, 0, 0, 0); + /* Disable all the NPC entries */ + rc = roc_npc_mcam_enable_all_entries(&dev->npc, 0); + if (rc) + return rc; /* Stop link change events */ if (!roc_nix_is_vf_or_sdp(&dev->nix)) @@ -1483,6 +1485,12 @@ cnxk_nix_dev_start(struct rte_eth_dev *eth_dev) return rc; } + rc = roc_npc_mcam_enable_all_entries(&dev->npc, 1); + if (rc) { + plt_err("Failed to enable NPC entries %d", rc); + return rc; + } + cnxk_nix_toggle_flag_link_cfg(dev, true); /* Start link change events */ @@ -1733,6 +1741,9 @@ cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool reset) struct roc_nix *nix = &dev->nix; int rc, i; + /* Disable switch hdr pkind */ + roc_nix_switch_hdr_set(&dev->nix, 0, 0, 0, 0); + plt_free(eth_dev->security_ctx); eth_dev->security_ctx = NULL; diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c index f20f201db2..1ae90092d6 100644 --- a/drivers/net/cnxk/cnxk_ethdev_ops.c +++ b/drivers/net/cnxk/cnxk_ethdev_ops.c @@ -67,8 +67,8 @@ cnxk_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo) devinfo->speed_capa = dev->speed_capa; devinfo->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | - RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; - devinfo->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; + RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP | + RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; return 0; } -- 2.25.4