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Mon, 14 Feb 2022 01:35:25 -0800 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Subject: [PATCH v2 02/20] net/mlx5: fix ineffective metadata argument adjustment Date: Mon, 14 Feb 2022 11:34:53 +0200 Message-ID: <20220214093511.1592698-3-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220214093511.1592698-1-michaelba@nvidia.com> References: <20220127153950.812953-1-michaelba@nvidia.com> <20220214093511.1592698-1-michaelba@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 79a44887-8be3-445c-1ada-08d9ef9d5613 X-MS-TrafficTypeDiagnostic: BY5PR12MB4835:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 916Pt+razBeJiJyd3v465Xzugu6NqYeUsL5n4cLKqjMnLdpswy2RsbymkqPH8zKDE2IC76lREfn1Gf0LZxOtmoyCN4KyIVtQtfblbKTH5Puf213/vXMZp4fVHzPJjhNbYK4GoFlbSgxQEsygoLYWshKlElyop33bG008tqLBceLBz8K9PwoyBKV/ahYevgD0Ociqkg4gJdsw3m2y9OlvAYu3cGf3FLZcVtS/jgEWVxIYwGfBEFszsqY+CaCHDh2lIMtGaeb4jE++TTkT5dZT53jf/xsHQTiP5a0mzB8RFZRaWVQWvRjrpL+Dlw9YkS/jMQWrIGOyY4aABIKaUkIwOMD9T9UUsLjNTg4r5JE/DAU9x/Aqk0EkV3YqVRLAtr3l9LoBJQR6eVI59Tw+8vsgEigPlT2Y2L4fTWUkdrEiSjLwkk8LvhrDn9AO840/YnInPlHDICtAIsjcbqKMrtZFk557aEpUAoHQZdmi7EoHxOFtQKdpPiRAlMi+l0v8AtDOsQiqzdhGfP4ALFoRD8h5SQHZRj5+V2inY/I3zHVIe7A1QFfCsskCTwV5mtE8CJLUdrY/XuKwaHU0Nk5Otnx7m5emDKQJYIv16ieLjt6EfB2qcYDy/+hqy+iA+z1tjHOa929RUzTCCCDEeH8era+V6ZMPsNc+kvXS2x9BzZVEW+ghRVSEb42hVZ2pHLlqOxM+GXTV8iZMoapmsx2vxHWapQ== X-Forefront-Antispam-Report: CIP:12.22.5.234; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(40460700003)(36860700001)(86362001)(47076005)(356005)(81166007)(316002)(82310400004)(54906003)(6916009)(8936002)(8676002)(70586007)(70206006)(2906002)(5660300002)(450100002)(4326008)(55016003)(2616005)(83380400001)(336012)(426003)(36756003)(1076003)(6666004)(186003)(26005)(6286002)(508600001)(7696005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2022 09:35:28.1538 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 79a44887-8be3-445c-1ada-08d9ef9d5613 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4835 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org In "dv_xmeta_en" devarg there is an option of dv_xmeta_en=3 which engages tunnel offload mode. In E-Switch configuration, that mode implicitly activates dv_xmeta_en=1. The update according to E-switch support is done immediately after the first parsing of the devargs, but there is another adjustment later. This patch moves the adjustment after the second parsing. Fixes: 4ec6360de37d ("net/mlx5: implement tunnel offload") Cc: stable@dpdk.org Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/net/mlx5/linux/mlx5_os.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index e157795b63..69d3e1e3ad 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -977,10 +977,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, strerror(rte_errno)); goto error; } - if (config->dv_miss_info) { - if (switch_info->master || switch_info->representor) - config->dv_xmeta_en = MLX5_XMETA_MODE_META16; - } sh = mlx5_alloc_shared_dev_ctx(spawn, config); if (!sh) return NULL; @@ -1242,6 +1238,10 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, /* Override some values set by hardware configuration. */ mlx5_args(config, dpdk_dev->devargs); /* Update final values for devargs before check sibling config. */ + if (config->dv_miss_info) { + if (switch_info->master || switch_info->representor) + config->dv_xmeta_en = MLX5_XMETA_MODE_META16; + } #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) if (config->dv_flow_en) { DRV_LOG(WARNING, "DV flow is not supported."); -- 2.25.1