From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: <dev-bounces@dpdk.org> Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8D32CA00BE; Thu, 17 Feb 2022 12:09:33 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 775B941151; Thu, 17 Feb 2022 12:09:33 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 1E9DE41150 for <dev@dpdk.org>; Thu, 17 Feb 2022 12:09:31 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 21HAe5PP017579; Thu, 17 Feb 2022 03:09:30 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=kfGVfr5iKwvfV00HnJzzaDv9tlv4zGYE0i4+rtEJUq4=; b=RU9rDNFxHJWYefrOmtvShN/xWbM3gbSDgoXCWC7erqH8VrCMN1/cwT/ifXGt7uLsnnzS gOPGQ2wIpc7YuiTrKinL0CHu/0JyOQC1C84AuycVKfMxpMRvjgdOT0tWeC54bQ641sKk P4WXWwLvdeOWyR3hM93qEyWeSRDsYpTpOi3arsjbe1+DN/bjoRRrwVCxMhtHz2SRYaHe CRDA00OFKV1lTkyaYp88N+9/pK3sghi5X6emiHgblaVIokFM9hZcavDAGeCUoIlJBoqc cBee++APP8ZrO6IWMqGl8I9ZYfzOm14P5IZY4tXCyBPRMZyugN9hm/U0Hl4BRxWtNAkW qA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3e9mt9r2xg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 17 Feb 2022 03:09:29 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 17 Feb 2022 03:09:28 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 17 Feb 2022 03:09:28 -0800 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id CF4FB3F705A; Thu, 17 Feb 2022 03:09:26 -0800 (PST) From: Tomasz Duszynski <tduszynski@marvell.com> To: <dev@dpdk.org> CC: <jerinj@marvell.com>, <thomas@monjalon.net>, Tomasz Duszynski <tduszynski@marvell.com> Subject: [PATCH v6 00/11] Add cnxk_gpio Date: Thu, 17 Feb 2022 12:09:13 +0100 Message-ID: <20220217110924.419024-1-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220118132424.2573372-1-tduszynski@marvell.com> References: <20220118132424.2573372-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: td-vSJHC9ry_Twx_6ggHBCmWXOFjPMaa X-Proofpoint-ORIG-GUID: td-vSJHC9ry_Twx_6ggHBCmWXOFjPMaa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-17_04,2022-02-17_01,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org This series introduces a new rawdevice PMD which allows to manage userspace GPIOs and install custom GPIO interrupt handlers which bypass kernel. This is especially useful for applications that, besides providing standard dataplane functionality, want to have fast and low latency access to GPIO pin state. It'd be great to have that merged during 22.03 merge window. v6: - update MAINTAINERS v5: - added close callback to make sure PMD resources are freed properly - updated selftest to return early on error - doc fixes v4: - free kvargs after parsing arguments - add support for allowing only subset of available GPIOs v3: - fix meson formatting - fix cnxk_gpio_process_buf() return value v2: - do not trigger irq by writing to /dev/mem, use ioctl() instead Tomasz Duszynski (11): raw/cnxk_gpio: add GPIO driver skeleton raw/cnxk_gpio: support reading default queue conf raw/cnxk_gpio: support reading queue count raw/cnxk_gpio: support queue setup raw/cnxk_gpio: support queue release raw/cnxk_gpio: support enqueuing buffers raw/cnxk_gpio: support dequeuing buffers raw/cnxk_gpio: support standard GPIO operations raw/cnxk_gpio: support custom irq handlers raw/cnxk_gpio: support selftest raw/cnxk_gpio: add option to allow using subset of GPIOs MAINTAINERS | 6 + doc/guides/platform/cnxk.rst | 2 + doc/guides/rawdevs/cnxk_gpio.rst | 200 ++++++ doc/guides/rawdevs/index.rst | 1 + doc/guides/rel_notes/release_22_03.rst | 10 + drivers/raw/cnxk_gpio/cnxk_gpio.c | 763 +++++++++++++++++++++ drivers/raw/cnxk_gpio/cnxk_gpio.h | 35 + drivers/raw/cnxk_gpio/cnxk_gpio_irq.c | 216 ++++++ drivers/raw/cnxk_gpio/cnxk_gpio_selftest.c | 393 +++++++++++ drivers/raw/cnxk_gpio/meson.build | 11 + drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h | 437 ++++++++++++ drivers/raw/cnxk_gpio/version.map | 3 + drivers/raw/meson.build | 1 + 13 files changed, 2078 insertions(+) create mode 100644 doc/guides/rawdevs/cnxk_gpio.rst create mode 100644 drivers/raw/cnxk_gpio/cnxk_gpio.c create mode 100644 drivers/raw/cnxk_gpio/cnxk_gpio.h create mode 100644 drivers/raw/cnxk_gpio/cnxk_gpio_irq.c create mode 100644 drivers/raw/cnxk_gpio/cnxk_gpio_selftest.c create mode 100644 drivers/raw/cnxk_gpio/meson.build create mode 100644 drivers/raw/cnxk_gpio/rte_pmd_cnxk_gpio.h create mode 100644 drivers/raw/cnxk_gpio/version.map -- 2.25.1