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SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(26005)(426003)(82310400004)(2906002)(186003)(5660300002)(7696005)(6666004)(1076003)(6286002)(2616005)(16526019)(8936002)(55016003)(356005)(81166007)(336012)(47076005)(40460700003)(86362001)(83380400001)(36860700001)(110136005)(4326008)(8676002)(316002)(36756003)(70206006)(70586007)(6636002)(508600001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Feb 2022 07:18:58.1333 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 39804d31-d560-4040-271d-08d9f2aeee18 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT032.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5735 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org One of the E-Switch vports plays the special role - it is assigned as "E-Switch manager" and has some special exclusive rights and duties - it maintains all the representors, manages FDB domain flows, etc. By default, the E-Switch vport index was supposed to be zero on standalone NICs (regular ConnectX) and 0xFFFE SmartNIC (BlueField), but that was not always correct - this index can be assigned with any value by kernel/hypervisor. To handle this, this uses the DevX API to query E-Switch manager vport ID directly from firmware during initialization. Fixes: a564038699f9 ("net/mlx5: support E-Switch manager egress traffic match") Cc: stable@dpdk.org Signed-off-by: Shun Hao --- drivers/common/mlx5/mlx5_devx_cmds.c | 12 ++++++++++++ drivers/common/mlx5/mlx5_devx_cmds.h | 2 ++ drivers/common/mlx5/mlx5_prm.h | 12 ++++++++++++ 3 files changed, 26 insertions(+) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 2e807a0829..6d632b97ed 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -1130,6 +1130,18 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, goto error; } } + if (attr->eswitch_manager) { + hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, + MLX5_SET_HCA_CAP_OP_MOD_ESW | + MLX5_HCA_CAP_OPMOD_GET_CUR); + if (!hcattr) + return rc; + attr->esw_mgr_vport_id_valid = + MLX5_GET(esw_cap, hcattr, + esw_manager_vport_number_valid); + attr->esw_mgr_vport_id = + MLX5_GET(esw_cap, hcattr, esw_manager_vport_number); + } return 0; error: rc = (rc > 0) ? -rc : rc; diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 37821b493e..4373761c29 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -252,6 +252,8 @@ struct mlx5_hca_attr { uint32_t umr_modify_entity_size_disabled:1; uint32_t umr_indirect_mkey_disabled:1; uint32_t log_min_stride_wqe_sz:5; + uint32_t esw_mgr_vport_id_valid:1; /* E-Switch Mgr vport ID is valid. */ + uint16_t esw_mgr_vport_id; /* E-Switch Mgr vport ID . */ uint16_t max_wqe_sz_sq; }; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 495b63191a..b9e39aa717 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1264,6 +1264,7 @@ enum { MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1, MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1, MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1, + MLX5_SET_HCA_CAP_OP_MOD_ESW = 0x9 << 1, MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1, MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP = 0x1C << 1, MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1, @@ -1926,6 +1927,16 @@ struct mlx5_ifc_cmd_hca_cap_2_bits { u8 reserved_at_100[0x700]; }; +struct mlx5_ifc_esw_cap_bits { + u8 reserved_at_0[0x60]; + + u8 esw_manager_vport_number_valid[0x1]; + u8 reserved_at_61[0xf]; + u8 esw_manager_vport_number[0x10]; + + u8 reserved_at_80[0x780]; +}; + union mlx5_ifc_hca_cap_union_bits { struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; @@ -1934,6 +1945,7 @@ union mlx5_ifc_hca_cap_union_bits { struct mlx5_ifc_qos_cap_bits qos_cap; struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps; struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; + struct mlx5_ifc_esw_cap_bits esw_cap; struct mlx5_ifc_roce_caps_bits roce_caps; u8 reserved_at_0[0x8000]; }; -- 2.20.0