From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 61EA8A034E; Tue, 22 Feb 2022 11:27:24 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7F9CA41152; Tue, 22 Feb 2022 11:27:16 +0100 (CET) Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2058.outbound.protection.outlook.com [40.107.220.58]) by mails.dpdk.org (Postfix) with ESMTP id C355941151 for ; Tue, 22 Feb 2022 11:27:15 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ER+Wm4TW1vUR8IEqWznreYhf2c/+Ie/IrJtJMWS+bw364Q3/OcjPM0VVcSL+wPnl/h19GbdkjQPpzUvkvxFzQ1Vzilxqdv+AlkXhTzp3G/oESzXgJevm5620w7BOuWh/8DhSOPKCHWgGs/+tv9rqhBGmAlG9EZbldNF8Iwiq+Xz4CF5sucsnx6c8HU0t3wxFvZTsf55QuxPuy8ZdxY/u7M5ZM0JwaKyRXvJe92A1bPeerulgX7kKjsEn1MVxPlnP5AVSCqRc9JnqdRU87f73/yGee4AV+a9MXWBoMYHNl9As3Q9wZNmUW8lX2D35fV5PZmfR7DVKpE0sGCJ5LYfDyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=p7Yf/G/mctjjWQO0ayuom5lH7ePPJSVhQuOkZzaHtG0=; b=cHGiWwyxQj/L9dI8aq9v9jJg1N4X+qKkYmPuUzVFB/wmkt8dGK8WqEiBXqEj/O0fSfmiT407L6nVbCAzyRu38leg0DEOR9QH+MQ61Tgr30BcRmSmK3tPAox2gXbirx/aX+uKm37cqw151ssrvOfrZdHoJmq468rpSszGzQjX3hKo5PCFs8XhWiq4uuQYH8Z4MhISvvUK+FqfyQBsS84Qe9wGxK5CtPzLCm+a3zs4bFQHh8I3g/LxrmKBgsMuP8qljODcbAsF7l8sZSlAPVemry+eEbms6dBRrzHEjnh5cME//O7AHpLRrClSegIIi+nSIewngq83a7GX0sVBizFW3Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.234) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=p7Yf/G/mctjjWQO0ayuom5lH7ePPJSVhQuOkZzaHtG0=; b=neyXnLlBcIIfHvvJ96v0ouI4ObTdKpmTV2UcZyLiKMKC7HIXBoLPiSHC6/uEXgfD9N1B0MNAQaKusvGttMCOH4FcKIhW5dX901AFerYBgkz+0o9FmyaBIpeXDMFC9LUR9McGDWu6W1NdWTgSusYMwZB4AzeX4yxdzg8MejIlgNQxlW4Zrul17AzufzMZ9acY/3CCJlNEj8irqIP4/d9m25UEtvi4X1DaE7MYB7ADNnayeRzBH4u+HSUs+V1EkGhAxskuX0tWtQBQ9LSe6wbg8qzcqn7Z0cpG9Cgmei/FLh4Nq6Tq5gpV31Ebn4diivg0EMlAwbsZBVpls/UkmiCkJg== Received: from DM5PR17CA0052.namprd17.prod.outlook.com (2603:10b6:3:13f::14) by BL0PR12MB4916.namprd12.prod.outlook.com (2603:10b6:208:1ce::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5017.21; Tue, 22 Feb 2022 10:27:12 +0000 Received: from DM6NAM11FT017.eop-nam11.prod.protection.outlook.com (2603:10b6:3:13f:cafe::c0) by DM5PR17CA0052.outlook.office365.com (2603:10b6:3:13f::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4995.24 via Frontend Transport; Tue, 22 Feb 2022 10:27:12 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.234) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.234) by DM6NAM11FT017.mail.protection.outlook.com (10.13.172.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4995.15 via Frontend Transport; Tue, 22 Feb 2022 10:27:12 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 22 Feb 2022 10:27:11 +0000 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9; Tue, 22 Feb 2022 02:27:09 -0800 From: Viacheslav Ovsiienko To: CC: , Subject: [PATCH v2 2/4] net/mlx5: configure Tx queue with send on time offload Date: Tue, 22 Feb 2022 12:26:46 +0200 Message-ID: <20220222102648.4662-3-viacheslavo@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20220222102648.4662-1-viacheslavo@nvidia.com> References: <20220214085655.22648-2-viacheslavo@nvidia.com> <20220222102648.4662-1-viacheslavo@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b8448cdf-0185-4484-a05f-08d9f5ede37b X-MS-TrafficTypeDiagnostic: BL0PR12MB4916:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: VVOJsmYQyxVXY3kBxLCC61vfDs00ubXi8rb/0ZjB7d32jD+WT53Aj6fOMt7uZag6ItkG7e2/W/pobLSVLumDfEGwLd9SKW2d+tuaq1NJXnSbgZUZ6O6MswrmGV6zbNpvf5EurgaFs12bRLKy5+Za84pPzqACIMoUaUEhvfaD9KA9ieLjYJt+V/LQySG52H43XhyG05HQqdI0XgDmpEzgyZaB0Fcpsfzhg7+Kw6v5ARXkowAoz0QmZopAeR3DnnFCAwN3aKCBRqI8CnkTIW2K01BhY71UTz45Zcah5Wiq7dR37XRF1rpjYhcfF8+iuDeLDwnyXxV0oTDdA6E4SBxH8KmYWOh41qpaM9xRNTwzV00gYkJrmb5hQQ0kt9Fr97XJSiGNzUcersBYSEnLHiFgPhBxAS82tc/Ipq9lNKJVvseX8MvqznWFAHRa2rd9VDvvjmiHCDq15BpOs6SiegiAbDhSapdVdclTDwIOQYGOH2CnC98e/P9JrZ7o6QeQ+r38Q4Xzow4s1HhGwHR80kXOyNvHus9QmQ+CxUHUQnB9PIAesKx5qvgqM8ckB+0E27Hh+l4gt+KY9iqFsQnqc+tr8FmwF2/5FlUkr8avMe10FF5TR7MpuDhZghkX0SYhDBUIscWARXkoGLwfBHjRCVpIB+HsgoUkdhgruBkz2gXA4PFYql+huzgcsEZMcAcSMtZlk8qRpk3ye2p1nWDheZGA+g== X-Forefront-Antispam-Report: CIP:12.22.5.234; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(316002)(4326008)(7696005)(55016003)(6916009)(54906003)(508600001)(8676002)(6666004)(70206006)(70586007)(107886003)(2616005)(336012)(426003)(40460700003)(36756003)(16526019)(83380400001)(1076003)(186003)(26005)(6286002)(8936002)(36860700001)(5660300002)(47076005)(86362001)(2906002)(81166007)(356005)(82310400004)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Feb 2022 10:27:12.0970 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b8448cdf-0185-4484-a05f-08d9f5ede37b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT017.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4916 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The wait on time configuration flag is copied to the Tx queue structure due to performance considerations. Timestamp mask is preparted and stored in queue structure as well. Signed-off-by: Viacheslav Ovsiienko --- drivers/net/mlx5/linux/mlx5_verbs.c | 4 ++++ drivers/net/mlx5/mlx5.h | 3 +++ drivers/net/mlx5/mlx5_devx.c | 2 ++ drivers/net/mlx5/mlx5_tx.h | 3 +++ drivers/net/mlx5/mlx5_txq.c | 18 ++++++++++++++++-- 5 files changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_verbs.c b/drivers/net/mlx5/linux/mlx5_verbs.c index 73c44138de..331c61d3c5 100644 --- a/drivers/net/mlx5/linux/mlx5_verbs.c +++ b/drivers/net/mlx5/linux/mlx5_verbs.c @@ -1035,6 +1035,10 @@ mlx5_txq_ibv_obj_new(struct rte_eth_dev *dev, uint16_t idx) txq_data->wqe_pi = 0; txq_data->wqe_comp = 0; txq_data->wqe_thres = txq_data->wqe_s / MLX5_TX_COMP_THRESH_INLINE_DIV; + txq_data->wait_on_time = !!(!priv->sh->config.tx_pp && + priv->sh->cdev->config.hca_attr.wait_on_time && + txq_data->offloads & + RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP); #ifdef HAVE_IBV_FLOW_DV_SUPPORT /* * If using DevX need to query and store TIS transport domain value. diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 35ea3fb47c..4db94bb6e2 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -337,6 +337,9 @@ struct mlx5_lb_ctx { #define MLX5_CNT_ARRAY_IDX(pool, cnt) \ ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \ MLX5_CNT_LEN(pool))) +#define MLX5_TS_MASK_SECS 8ull +/* timestamp wrapping in seconds, must be power of 2. */ + /* * The pool index and offset of counter in the pool array makes up the * counter index. In case the counter is from pool 0 and offset 0, it diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index e57787cfec..e178b799fa 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -1328,6 +1328,8 @@ mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx) txq_data->qp_num_8s = txq_obj->sq_obj.sq->id << 8; txq_data->db_heu = sh->cdev->config.dbnc == MLX5_TXDB_HEURISTIC; txq_data->db_nc = sh->tx_uar.dbnc; + txq_data->wait_on_time = !!(!sh->config.tx_pp && + sh->cdev->config.hca_attr.wait_on_time); /* Change Send Queue state to Ready-to-Send. */ ret = mlx5_txq_devx_modify(txq_obj, MLX5_TXQ_MOD_RST2RDY, 0); if (ret) { diff --git a/drivers/net/mlx5/mlx5_tx.h b/drivers/net/mlx5/mlx5_tx.h index c4b8271f6f..b50deb8b67 100644 --- a/drivers/net/mlx5/mlx5_tx.h +++ b/drivers/net/mlx5/mlx5_tx.h @@ -138,6 +138,8 @@ struct mlx5_txq_data { uint16_t vlan_en:1; /* VLAN insertion in WQE is supported. */ uint16_t db_nc:1; /* Doorbell mapped to non-cached region. */ uint16_t db_heu:1; /* Doorbell heuristic write barrier. */ + uint16_t rt_timestamp:1; /* Realtime timestamp format. */ + uint16_t wait_on_time:1; /* WQE with timestamp is supported. */ uint16_t fast_free:1; /* mbuf fast free on Tx is enabled. */ uint16_t inlen_send; /* Ordinary send data inline size. */ uint16_t inlen_empw; /* eMPW max packet size to inline. */ @@ -157,6 +159,7 @@ struct mlx5_txq_data { volatile uint32_t *cq_db; /* Completion queue doorbell. */ uint16_t port_id; /* Port ID of device. */ uint16_t idx; /* Queue index. */ + uint64_t rt_timemask; /* Scheduling timestamp mask. */ uint64_t ts_mask; /* Timestamp flag dynamic mask. */ int32_t ts_offset; /* Timestamp field dynamic offset. */ struct mlx5_dev_ctx_shared *sh; /* Shared context. */ diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c index edbaa50692..f128c3d1a5 100644 --- a/drivers/net/mlx5/mlx5_txq.c +++ b/drivers/net/mlx5/mlx5_txq.c @@ -109,7 +109,8 @@ mlx5_get_tx_port_offloads(struct rte_eth_dev *dev) RTE_ETH_TX_OFFLOAD_TCP_CKSUM); if (dev_cap->tso) offloads |= RTE_ETH_TX_OFFLOAD_TCP_TSO; - if (priv->sh->config.tx_pp) + if (priv->sh->config.tx_pp || + priv->sh->cdev->config.hca_attr.wait_on_time) offloads |= RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP; if (dev_cap->swp) { if (dev_cap->swp & MLX5_SW_PARSING_CSUM_CAP) @@ -1288,12 +1289,21 @@ mlx5_txq_dynf_timestamp_set(struct rte_eth_dev *dev) int off, nbit; unsigned int i; uint64_t mask = 0; + uint64_t ts_mask; + if (sh->dev_cap.rt_timestamp || + !sh->cdev->config.hca_attr.dev_freq_khz) + ts_mask = MLX5_TS_MASK_SECS << 32; + else + ts_mask = rte_align64pow2(MLX5_TS_MASK_SECS * 1000ull * + sh->cdev->config.hca_attr.dev_freq_khz); + ts_mask = rte_cpu_to_be_64(ts_mask - 1ull); nbit = rte_mbuf_dynflag_lookup (RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL); off = rte_mbuf_dynfield_lookup (RTE_MBUF_DYNFIELD_TIMESTAMP_NAME, NULL); - if (nbit >= 0 && off >= 0 && sh->txpp.refcnt) + if (nbit >= 0 && off >= 0 && + (sh->txpp.refcnt || priv->sh->cdev->config.hca_attr.wait_on_time)) mask = 1ULL << nbit; for (i = 0; i != priv->txqs_n; ++i) { data = (*priv->txqs)[i]; @@ -1302,5 +1312,9 @@ mlx5_txq_dynf_timestamp_set(struct rte_eth_dev *dev) data->sh = sh; data->ts_mask = mask; data->ts_offset = off; + data->rt_timestamp = sh->dev_cap.rt_timestamp; + data->rt_timemask = (data->offloads & + RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP) ? + ts_mask : 0; } } -- 2.18.1