From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F3D98A034C; Tue, 22 Feb 2022 20:37:14 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3EFF2411EE; Tue, 22 Feb 2022 20:36:19 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id ECCA7411E1 for ; Tue, 22 Feb 2022 20:36:16 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 21MItcEU019938 for ; Tue, 22 Feb 2022 11:36:16 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=uc4wiWUV/JEOVxMpcmZ4qOyJniB5qqn0LMQnS0ZpO9I=; b=YgaRsGSo92ijx4SRD3B0thZJgr2Epjqdp+/kMl/8VPtNfmNzp1xI4zAWx9hXYzv0OBti JihfXwrzL41LRnLM8MvA5TEMJjVysnEGGDQBm/r25sULajLf8j7LFyN+QxHokbDtkGrt XtL7R+UQf1NXQIE3/J8CrvAiBN8CYt+WzDct3WB4MhZXCQsQr+fy7LakyEF3iGB2f7Ms AIHjk3/lSqvV3ZHXUzgPqnsL+aktYilJTHcVO+dxvdd78JS8rPCP4TQfaShaTyZV1yEE S6BebLYbIuQbSiUChbEKYlKwFAhlsHX/GlKIZIMkhg+JTo5csOtl8AGp8NpJhMg3Ze/k 7g== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3ecwaxar5x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 22 Feb 2022 11:36:16 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 22 Feb 2022 11:36:14 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 22 Feb 2022 11:36:14 -0800 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id B0B993F7092; Tue, 22 Feb 2022 11:36:12 -0800 (PST) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: Subject: [PATCH v2 20/21] net/cnxk: add option to override outbound inline SA IV Date: Wed, 23 Feb 2022 01:05:11 +0530 Message-ID: <20220222193512.19292-20-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220222193512.19292-1-ndabilpuram@marvell.com> References: <20220207072932.22409-1-ndabilpuram@marvell.com> <20220222193512.19292-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: yn027HTr6Tky9w3hLqK4YELBBS7XJtBd X-Proofpoint-ORIG-GUID: yn027HTr6Tky9w3hLqK4YELBBS7XJtBd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-22_06,2022-02-21_02,2021-12-02_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add option to override outbound inline SA IV for debug purposes via environment variable. User can set env variable as: export CN10K_ETH_SEC_IV_OVR="0x0, 0x0,..." Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cn10k_ethdev_sec.c | 62 +++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c index a2a53c1..a514345 100644 --- a/drivers/net/cnxk/cn10k_ethdev_sec.c +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c @@ -252,6 +252,63 @@ cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args) cnxk_pktmbuf_free_no_cache(mbuf); } +static void +outb_dbg_iv_update(struct roc_ot_ipsec_outb_sa *outb_sa, const char *__iv_str) +{ + uint8_t *iv_dbg = outb_sa->iv.iv_dbg; + char *iv_str = strdup(__iv_str); + char *iv_b = NULL, len = 16; + char *save; + int i; + + if (!iv_str) + return; + + if (outb_sa->w2.s.enc_type == ROC_IE_OT_SA_ENC_AES_GCM || + outb_sa->w2.s.enc_type == ROC_IE_OT_SA_ENC_AES_CTR || + outb_sa->w2.s.enc_type == ROC_IE_OT_SA_ENC_AES_CCM || + outb_sa->w2.s.auth_type == ROC_IE_OT_SA_AUTH_AES_GMAC) { + memset(outb_sa->iv.s.iv_dbg1, 0, sizeof(outb_sa->iv.s.iv_dbg1)); + memset(outb_sa->iv.s.iv_dbg2, 0, sizeof(outb_sa->iv.s.iv_dbg2)); + + iv_dbg = outb_sa->iv.s.iv_dbg1; + for (i = 0; i < 4; i++) { + iv_b = strtok_r(i ? NULL : iv_str, ",", &save); + if (!iv_b) + break; + iv_dbg[i] = strtoul(iv_b, NULL, 0); + } + *(uint32_t *)iv_dbg = rte_be_to_cpu_32(*(uint32_t *)iv_dbg); + + iv_dbg = outb_sa->iv.s.iv_dbg2; + for (i = 0; i < 4; i++) { + iv_b = strtok_r(NULL, ",", &save); + if (!iv_b) + break; + iv_dbg[i] = strtoul(iv_b, NULL, 0); + } + *(uint32_t *)iv_dbg = rte_be_to_cpu_32(*(uint32_t *)iv_dbg); + + } else { + iv_dbg = outb_sa->iv.iv_dbg; + memset(iv_dbg, 0, sizeof(outb_sa->iv.iv_dbg)); + + for (i = 0; i < len; i++) { + iv_b = strtok_r(i ? NULL : iv_str, ",", &save); + if (!iv_b) + break; + iv_dbg[i] = strtoul(iv_b, NULL, 0); + } + *(uint64_t *)iv_dbg = rte_be_to_cpu_64(*(uint64_t *)iv_dbg); + *(uint64_t *)&iv_dbg[8] = + rte_be_to_cpu_64(*(uint64_t *)&iv_dbg[8]); + } + + /* Update source of IV */ + outb_sa->w2.s.iv_src = ROC_IE_OT_SA_IV_SRC_FROM_SA; + free(iv_str); +} + static int cn10k_eth_sec_session_create(void *device, struct rte_security_session_conf *conf, @@ -390,6 +447,7 @@ cn10k_eth_sec_session_create(void *device, struct cn10k_outb_priv_data *outb_priv; struct cnxk_ipsec_outb_rlens *rlens; uint64_t sa_base = dev->outb.sa_base; + const char *iv_str; uint32_t sa_idx; PLT_STATIC_ASSERT(sizeof(struct cn10k_outb_priv_data) < @@ -416,6 +474,10 @@ cn10k_eth_sec_session_create(void *device, goto mempool_put; } + iv_str = getenv("CN10K_ETH_SEC_IV_OVR"); + if (iv_str) + outb_dbg_iv_update(outb_sa_dptr, iv_str); + /* Save userdata */ outb_priv->userdata = conf->userdata; outb_priv->sa_idx = sa_idx; -- 2.8.4