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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.235 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.235; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.235) by DM6NAM11FT066.mail.protection.outlook.com (10.13.173.179) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5017.22 via Frontend Transport; Thu, 24 Feb 2022 03:11:16 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 24 Feb 2022 03:10:45 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9; Wed, 23 Feb 2022 19:10:43 -0800 From: Suanming Mou To: , CC: , , Subject: [PATCH v3 00/14] net/mlx5: add hardware steering Date: Thu, 24 Feb 2022 05:10:15 +0200 Message-ID: <20220224031029.14049-1-suanmingm@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20220210162926.20436-1-suanmingm@nvidia.com> References: <20220210162926.20436-1-suanmingm@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a4bed7eb-be7d-4234-3cdb-08d9f7435232 X-MS-TrafficTypeDiagnostic: BL0PR12MB2466:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Feb 2022 03:11:16.2279 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a4bed7eb-be7d-4234-3cdb-08d9f7435232 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT066.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB2466 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The Connect-X steering is a lookup hardware mechanism that accesses flow tables, matches packets to the rules, and performs specified actions. Historically, mlx5 PMD implements several software engines to manage steering hardware facility: - FW Steering - Verbs/Direct Verbs, uses FW calls to manage flows - SW Steering - DevX/mlx5dv, uses WQEs to access table memory directly However, there are still some disadvantages: - performance is limited, we should invoke firmware either to manage the entire flow, or to handle some internal steering objects - organizing and preparing flow infrastructure (actions, matchers, groups, etc.) on the flow inserting is sure to cause slow flow insertion - security, exposing the low-level steering entries directly to the userspace may cause security risks A new hardware WQE based steering operation with codename "HW Steering" is going to be introduced to get rid of the security risks. And it will take advantage of the recently new introduced async queue-based rte_flow APIs to prepare everything in advance to achieve high insertion rate. In this new HW steering engine, the original SW steering rte_flow API will not be supported in the first implementation, only the new async queue-based flow operations is going to be supported. A new steering mode parameter for dv_flow_en will be introduced and user will be able to engage the new steering engine. *** THIS PATCH SET DEPENDS ON THE NEW RTE_FLOW ASYNC API *** --- v3: - rebase to the latest version. v2: - New HW steering low-level abstract code added. - commit message improvement. - add protection for rte_flow and rte_flow_async callbacks. - rebase to rte_flow_async v9. - fix some rte_flow error not filled bugs. Suanming Mou (14): net/mlx5: introduce hardware steering operation net/mlx5: add HW steering low-level abstract code net/mlx5: introduce hardware steering enable routine net/mlx5: add port flow configuration net/mlx5: add pattern template management net/mlx5: add action template management net/mlx5: add table management net/mlx5: add basic flow queue operation net/mlx5: add flow flush function net/mlx5: add flow jump action net/mlx5: add queue and RSS action net/mlx5: add mark action net/mlx5: add indirect action net/mlx5: add header reformat action doc/guides/nics/mlx5.rst | 19 +- doc/guides/rel_notes/release_22_03.rst | 6 + drivers/net/mlx5/linux/mlx5_flow_os.h | 1 + drivers/net/mlx5/linux/mlx5_os.c | 22 +- drivers/net/mlx5/meson.build | 2 + drivers/net/mlx5/mlx5.c | 55 +- drivers/net/mlx5/mlx5.h | 66 +- drivers/net/mlx5/mlx5_devx.c | 10 + drivers/net/mlx5/mlx5_dr.c | 383 ++++ drivers/net/mlx5/mlx5_dr.h | 456 +++++ drivers/net/mlx5/mlx5_flow.c | 721 ++++++- drivers/net/mlx5/mlx5_flow.h | 287 +++ drivers/net/mlx5/mlx5_flow_dv.c | 186 +- drivers/net/mlx5/mlx5_flow_hw.c | 2335 +++++++++++++++++++++++ drivers/net/mlx5/mlx5_flow_verbs.c | 7 +- drivers/net/mlx5/mlx5_rx.h | 9 +- drivers/net/mlx5/mlx5_rxq.c | 85 +- drivers/net/mlx5/windows/mlx5_flow_os.h | 1 + 18 files changed, 4471 insertions(+), 180 deletions(-) create mode 100644 drivers/net/mlx5/mlx5_dr.c create mode 100644 drivers/net/mlx5/mlx5_dr.h create mode 100644 drivers/net/mlx5/mlx5_flow_hw.c -- 2.25.1