From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C064EA0353; Thu, 24 Feb 2022 11:43:04 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 55B4441155; Thu, 24 Feb 2022 11:43:04 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 32BE84114D for ; Thu, 24 Feb 2022 11:43:02 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 21O7D06H024405; Thu, 24 Feb 2022 02:43:01 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=KRTdZ6/yjPem3sgdS6bY9ij1N+SpJXOMKP06sTEcHKY=; b=XLlc47dcLCN/PUzwQStHb5Mf/vnS37E2v6dHSPQSM6qjkPzajgonj5lBPB7etlNq3iVP Q0eLVsqXSwlUP181NGM3FAe3h3f36FzTTZ4tMllNRLH+V3NQZzsi8RK76E00zDktQLTD Yz/cXcaQFGog1HtN2R5TLgaafZOLYo557SmNM0d97htP0epUU+qesnG11yDe/cxciAR2 L87QiFU3KfTTEKO5pI8u6rDMU+nfD9lMAKJlwlgdR5BGiulXGocTveZF57MxfL8zAPOC VmLAHR/r3QM2XUToOe438KR0A/aYiJhG0xyj7WktgVL2YELgZznH3gNp1pMwKnzPQagW CA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3edjerp3hf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 24 Feb 2022 02:43:01 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 24 Feb 2022 02:42:59 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 24 Feb 2022 02:42:59 -0800 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id 13B253F7066; Thu, 24 Feb 2022 02:42:56 -0800 (PST) From: Tomasz Duszynski To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Tomasz Duszynski Subject: [PATCH] common/cnxk: support B0 variant Date: Thu, 24 Feb 2022 11:42:36 +0100 Message-ID: <20220224104236.1425812-1-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: pjgoG4A_TrjgnOAucM6YUZ-NTd1U2M6j X-Proofpoint-GUID: pjgoG4A_TrjgnOAucM6YUZ-NTd1U2M6j X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-02-24_01,2022-02-24_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add B0 variant to the list of supported models. Signed-off-by: Tomasz Duszynski Reviewed-by: Jerin Jacob Kollanukkaran --- drivers/common/cnxk/roc_model.c | 1 + drivers/common/cnxk/roc_model.h | 6 ++++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c index 49617c02b7..4120029541 100644 --- a/drivers/common/cnxk/roc_model.c +++ b/drivers/common/cnxk/roc_model.c @@ -56,6 +56,7 @@ static const struct model_db { {VENDOR_CAVIUM, PART_95xx, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"}, {VENDOR_CAVIUM, PART_95xxN, 0, 0, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a0"}, {VENDOR_CAVIUM, PART_95xxN, 0, 1, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a1"}, + {VENDOR_CAVIUM, PART_95xxN, 1, 0, ROC_MODEL_CNF95xxN_B0, "cnf95xxn_b0"}, {VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95xxO_A0, "cnf95O_a0"}, {VENDOR_CAVIUM, PART_95xxMM, 0, 0, ROC_MODEL_CNF95xxMM_A0, "cnf95xxmm_a0"}}; diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h index cee06779bc..4567566169 100644 --- a/drivers/common/cnxk/roc_model.h +++ b/drivers/common/cnxk/roc_model.h @@ -19,6 +19,7 @@ struct roc_model { #define ROC_MODEL_CNF95xxN_A0 BIT_ULL(12) #define ROC_MODEL_CNF95xxO_A0 BIT_ULL(13) #define ROC_MODEL_CNF95xxN_A1 BIT_ULL(14) +#define ROC_MODEL_CNF95xxN_B0 BIT_ULL(15) #define ROC_MODEL_CN98xx_A0 BIT_ULL(16) #define ROC_MODEL_CN106xx_A0 BIT_ULL(20) #define ROC_MODEL_CNF105xx_A0 BIT_ULL(21) @@ -39,11 +40,12 @@ struct roc_model { (ROC_MODEL_CN96xx_Ax | ROC_MODEL_CN96xx_C0 | ROC_MODEL_CNF95xx_A0 | \ ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95xxMM_A0 | \ ROC_MODEL_CNF95xxO_A0 | ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CN98xx_A0 | \ - ROC_MODEL_CNF95xxN_A1) + ROC_MODEL_CNF95xxN_A1 | ROC_MODEL_CNF95xxN_B0) #define ROC_MODEL_CNF9K \ (ROC_MODEL_CNF95xx_A0 | ROC_MODEL_CNF95xx_B0 | \ ROC_MODEL_CNF95xxMM_A0 | ROC_MODEL_CNF95xxO_A0 | \ - ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CNF95xxN_A1) + ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CNF95xxN_A1 | \ + ROC_MODEL_CNF95xxN_B0) #define ROC_MODEL_CN106xx (ROC_MODEL_CN106xx_A0) #define ROC_MODEL_CNF105xx (ROC_MODEL_CNF105xx_A0) -- 2.25.1