From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C5F41A034C; Fri, 25 Feb 2022 11:34:29 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 632E34115C; Fri, 25 Feb 2022 11:34:29 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 9719C4068B for ; Fri, 25 Feb 2022 11:34:27 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 21PA1gBk010805; Fri, 25 Feb 2022 02:34:26 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=4xET0/mrwl8Qkz3SamLFu34urPjbbzdA/tZYELOVFuQ=; b=Mv6GFgMWloQmEUVSGcFRhdq/MT6yky4UM/HEtu9ToYYgCf6WA1IXi4RFYHSa5O48Zfpx QT12LCMLqqQC/Q0aDuzWZrcbCm/nx+/WnztWE4Fj1n5JYRozhL/w8boaj1cy6OCX4LbK a45Rn7adKMvQOmmUEWs+JmzfHj4l0gFwg9P+jbd0k7v2ZJQLxyGEvkXdEnnjBWsaZJyz N32zOBUTEcCxcCShvMcb+ALYU+w6DwY3DfW/H1fRnuh9tp0CkcEE5Uxt38A8h0K27jxf nbXLx9xdFvSSf078Cwdwm1kb1mhzdCOhT/w4w3ewNcyMrkxRs0eWPf+Hhguxhn/NmWi3 2g== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3eekfwagkq-7 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 25 Feb 2022 02:34:26 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 25 Feb 2022 02:34:18 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 25 Feb 2022 02:34:18 -0800 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id C409F3F70B8; Fri, 25 Feb 2022 02:34:14 -0800 (PST) From: Tomasz Duszynski To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Tomasz Duszynski , "Jerin Jacob" Subject: [dpdk-dev] [PATCH v2] common/cnxk: support CNF95xx B0 variant Date: Fri, 25 Feb 2022 11:34:10 +0100 Message-ID: <20220225103411.1633560-1-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220224104236.1425812-1-tduszynski@marvell.com> References: <20220224104236.1425812-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: 4t16ydIs7XaDO1Pt17ZUAaWnWizHtlRj X-Proofpoint-ORIG-GUID: 4t16ydIs7XaDO1Pt17ZUAaWnWizHtlRj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-02-25_06,2022-02-25_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add CNF95xx B0 variant to the list of supported models. Signed-off-by: Tomasz Duszynski Reviewed-by: Jerin Jacob --- v2: - Update release notes for new device support (Ferruh) doc/guides/rel_notes/release_22_03.rst | 1 + drivers/common/cnxk/roc_model.c | 1 + drivers/common/cnxk/roc_model.h | 6 ++++-- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/doc/guides/rel_notes/release_22_03.rst b/doc/guides/rel_notes/release_22_03.rst index 54563106d1..43c4db65c3 100644 --- a/doc/guides/rel_notes/release_22_03.rst +++ b/doc/guides/rel_notes/release_22_03.rst @@ -135,6 +135,7 @@ New Features * Added queue based priority flow control support for CN9K & CN10K. * Added support for IP reassembly for inline inbound IPsec packets. * Added support for packet marking in traffic manager. + * Added support for CNF95xx B0 variant SoC. * **Added an API for private user data in asymmetric crypto session.** diff --git a/drivers/common/cnxk/roc_model.c b/drivers/common/cnxk/roc_model.c index 49617c02b7..4120029541 100644 --- a/drivers/common/cnxk/roc_model.c +++ b/drivers/common/cnxk/roc_model.c @@ -56,6 +56,7 @@ static const struct model_db { {VENDOR_CAVIUM, PART_95xx, 1, 0, ROC_MODEL_CNF95xx_B0, "cnf95xx_b0"}, {VENDOR_CAVIUM, PART_95xxN, 0, 0, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a0"}, {VENDOR_CAVIUM, PART_95xxN, 0, 1, ROC_MODEL_CNF95xxN_A0, "cnf95xxn_a1"}, + {VENDOR_CAVIUM, PART_95xxN, 1, 0, ROC_MODEL_CNF95xxN_B0, "cnf95xxn_b0"}, {VENDOR_CAVIUM, PART_95O, 0, 0, ROC_MODEL_CNF95xxO_A0, "cnf95O_a0"}, {VENDOR_CAVIUM, PART_95xxMM, 0, 0, ROC_MODEL_CNF95xxMM_A0, "cnf95xxmm_a0"}}; diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h index cee06779bc..4567566169 100644 --- a/drivers/common/cnxk/roc_model.h +++ b/drivers/common/cnxk/roc_model.h @@ -19,6 +19,7 @@ struct roc_model { #define ROC_MODEL_CNF95xxN_A0 BIT_ULL(12) #define ROC_MODEL_CNF95xxO_A0 BIT_ULL(13) #define ROC_MODEL_CNF95xxN_A1 BIT_ULL(14) +#define ROC_MODEL_CNF95xxN_B0 BIT_ULL(15) #define ROC_MODEL_CN98xx_A0 BIT_ULL(16) #define ROC_MODEL_CN106xx_A0 BIT_ULL(20) #define ROC_MODEL_CNF105xx_A0 BIT_ULL(21) @@ -39,11 +40,12 @@ struct roc_model { (ROC_MODEL_CN96xx_Ax | ROC_MODEL_CN96xx_C0 | ROC_MODEL_CNF95xx_A0 | \ ROC_MODEL_CNF95xx_B0 | ROC_MODEL_CNF95xxMM_A0 | \ ROC_MODEL_CNF95xxO_A0 | ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CN98xx_A0 | \ - ROC_MODEL_CNF95xxN_A1) + ROC_MODEL_CNF95xxN_A1 | ROC_MODEL_CNF95xxN_B0) #define ROC_MODEL_CNF9K \ (ROC_MODEL_CNF95xx_A0 | ROC_MODEL_CNF95xx_B0 | \ ROC_MODEL_CNF95xxMM_A0 | ROC_MODEL_CNF95xxO_A0 | \ - ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CNF95xxN_A1) + ROC_MODEL_CNF95xxN_A0 | ROC_MODEL_CNF95xxN_A1 | \ + ROC_MODEL_CNF95xxN_B0) #define ROC_MODEL_CN106xx (ROC_MODEL_CN106xx_A0) #define ROC_MODEL_CNF105xx (ROC_MODEL_CNF105xx_A0) -- 2.35.1