From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7958BA0350; Mon, 28 Feb 2022 18:36:47 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 474B54068C; Mon, 28 Feb 2022 18:36:47 +0100 (CET) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 0EB2D40140 for ; Mon, 28 Feb 2022 18:36:44 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646069805; x=1677605805; h=from:to:cc:subject:date:message-id; bh=3h/bxeHIT7mY7fu0IEHpKknp61g7DthJV/kAVe8NbcI=; b=AAen7vxJOAg+lH84e0OYc9C+4Sl05cnxXx5ty+0e4WlYRILgEVF0jwBN 9+sDAuIUijtgCzUMQmsc1vH7J1AWl7UJZHwkkBhwI33WB74Pq8v1jqDnX a4rQ4KQD2McdoMqMwTCYC2q2tl1paIqZdCUdf/WLq0S3gVvh+MvrlQB/i Fy4sB2mXqU5hVkWmIe6xL0NRRebUcSpLIYV7GAarJ4wDIaF/duSFZBlj4 PQZl2Tvdcgubv7+jlxKzQyFnZ7ZcmR4JfJlsMPo5c47jvQj97pay4/ETP QXIpl0if225aVOn40ecYevvb06gPiyALe1rFUUpqeoKsjY7HfRjOtGYhx Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10272"; a="233560347" X-IronPort-AV: E=Sophos;i="5.90,144,1643702400"; d="scan'208";a="233560347" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2022 09:36:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,144,1643702400"; d="scan'208";a="534538481" Received: from silpixa00400465.ir.intel.com ([10.55.128.22]) by orsmga007.jf.intel.com with ESMTP; 28 Feb 2022 09:36:42 -0800 From: Kai Ji To: dev@dpdk.org Cc: roy.fan.zhang@intel.com, gakhil@marvell.com, Kai Ji Subject: [dpdk-dev] crypto/qat: fix process type handling Date: Tue, 1 Mar 2022 01:36:39 +0800 Message-Id: <20220228173639.51393-1-kai.ji@intel.com> X-Mailer: git-send-email 2.17.1 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch fix the process type handling in QAT PMDs where only primary and secondary process are supported in qat build request Signed-off-by: Kai Ji --- drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 3 +++ drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 3 +++ drivers/crypto/qat/dev/qat_sym_pmd_gen1.c | 3 +++ drivers/crypto/qat/qat_sym.c | 8 ++++---- 4 files changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c index 5084a5fcd1..739404b1d4 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c @@ -358,6 +358,9 @@ qat_sym_crypto_set_session_gen3(void *cdev __rte_unused, void *session) enum rte_proc_type_t proc_type = rte_eal_process_type(); int ret; + if (proc_type < 0 || proc_type == RTE_PROC_INVALID) + return -EINVAL; + ret = qat_sym_crypto_set_session_gen1(cdev, session); /* special single pass build request for GEN3 */ if (ctx->is_single_pass) diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c index bd7f3785df..586f3d0344 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c @@ -189,6 +189,9 @@ qat_sym_crypto_set_session_gen4(void *cdev, void *session) enum rte_proc_type_t proc_type = rte_eal_process_type(); int ret; + if (proc_type < 0 || proc_type == RTE_PROC_INVALID) + return -EINVAL; + ret = qat_sym_crypto_set_session_gen1(cdev, session); /* special single pass build request for GEN4 */ if (ctx->is_single_pass && ctx->is_ucs) diff --git a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c index 3bcb53cf9f..857b5747db 100644 --- a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c +++ b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c @@ -1149,6 +1149,9 @@ qat_sym_crypto_set_session_gen1(void *cryptodev __rte_unused, void *session) enum rte_proc_type_t proc_type = rte_eal_process_type(); int handle_mixed = 0; + if (proc_type < 0 || proc_type == RTE_PROC_INVALID) + return -EINVAL; + if ((ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER || ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) && !ctx->is_gmac) { diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c index 1ccffad5ab..d846cc9ac4 100644 --- a/drivers/crypto/qat/qat_sym.c +++ b/drivers/crypto/qat/qat_sym.c @@ -60,6 +60,10 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg, uintptr_t build_request_p = (uintptr_t)opaque[1]; qat_sym_build_request_t build_request = (void *)build_request_p; struct qat_sym_session *ctx = NULL; + enum rte_proc_type_t proc_type = rte_eal_process_type(); + + if (proc_type < 0 || proc_type == RTE_PROC_INVALID) + return -EINVAL; if (likely(op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)) { ctx = get_sym_session_private_data(op->sym->session, @@ -71,11 +75,9 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg, if (sess != (uintptr_t)ctx) { struct rte_cryptodev *cdev; struct qat_cryptodev_private *internals; - enum rte_proc_type_t proc_type; cdev = rte_cryptodev_pmd_get_dev(ctx->dev_id); internals = cdev->data->dev_private; - proc_type = rte_eal_process_type(); if (internals->qat_dev->qat_dev_gen != dev_gen) { op->status = @@ -105,7 +107,6 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg, if ((void *)sess != (void *)op->sym->sec_session) { struct rte_cryptodev *cdev; struct qat_cryptodev_private *internals; - enum rte_proc_type_t proc_type; ctx = get_sec_session_private_data( op->sym->sec_session); @@ -130,7 +131,6 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg, } cdev = rte_cryptodev_pmd_get_dev(ctx->dev_id); internals = cdev->data->dev_private; - proc_type = rte_eal_process_type(); if (internals->qat_dev->qat_dev_gen != dev_gen) { op->status = -- 2.30.2