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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Mar 2022 10:58:19.0215 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 833477f5-3fef-48c2-7cee-08d9fb72652f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1826 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Elena Agostini Memory allocated for CPU mapping the status flag in the communication list should be aligned to the GPU page size. Signed-off-by: Elena Agostini --- lib/gpudev/gpudev.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/lib/gpudev/gpudev.c b/lib/gpudev/gpudev.c index fb1bee344c..56033f4a5f 100644 --- a/lib/gpudev/gpudev.c +++ b/lib/gpudev/gpudev.c @@ -820,6 +820,7 @@ rte_gpu_comm_create_list(uint16_t dev_id, uint32_t idx_l; int ret; struct rte_gpu *dev; + struct rte_gpu_info info; if (num_comm_items == 0) { rte_errno = EINVAL; @@ -833,6 +834,12 @@ rte_gpu_comm_create_list(uint16_t dev_id, return NULL; } + ret = rte_gpu_info_get(dev_id, &info); + if (ret < 0) { + rte_errno = ENODEV; + return NULL; + } + comm_list = rte_zmalloc(NULL, sizeof(struct rte_gpu_comm_list) * num_comm_items, 0); if (comm_list == NULL) { @@ -855,7 +862,7 @@ rte_gpu_comm_create_list(uint16_t dev_id, */ comm_list[0].status_d = rte_gpu_mem_alloc(dev_id, sizeof(enum rte_gpu_comm_list_status) * num_comm_items, - rte_mem_page_size()); + info.page_size); if (ret < 0) { rte_errno = ENOMEM; return NULL; -- 2.17.1