From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B7E7EA0351; Fri, 4 Mar 2022 08:35:31 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7DE0740150; Fri, 4 Mar 2022 08:35:31 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id 880624013F for ; Fri, 4 Mar 2022 08:35:30 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F07C81396; Thu, 3 Mar 2022 23:35:29 -0800 (PST) Received: from net-arm-n1amp-02.shanghai.arm.com (net-arm-n1amp-02.shanghai.arm.com [10.169.210.142]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 26DA33F73D; Thu, 3 Mar 2022 23:35:27 -0800 (PST) From: Joyce Kong To: Ruifeng Wang , Beilei Xing , Joyce Kong Cc: dev@dpdk.org, nd@arm.com Subject: [PATCH v1] net/i40e: fix build issue with 16B descriptor on Arm Date: Fri, 4 Mar 2022 07:35:17 +0000 Message-Id: <20220304073517.2000817-1-joyce.kong@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org For NEON vector path, there is an issue when building with 16B descriptor: incompatible types when assigning to type ‘uint64x2_t’ from type ‘uint32x4_t’ 180 | descs[3] = vbslq_u32(v_desc3_mask, v_zeros, vreinterpretq_u32_u64(descs[3])); | ^~~~~~~~~ The fix is to add interpretation between type 'uint64x2_t' and type 'uint32x4_t'. Fixes: dba9e3bcd9bb ("net/i40e: add flow mark capability to NEON Rx") Signed-off-by: Joyce Kong Reviewed-by: Ruifeng Wang --- drivers/net/i40e/i40e_rxtx_vec_neon.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/net/i40e/i40e_rxtx_vec_neon.c b/drivers/net/i40e/i40e_rxtx_vec_neon.c index 6433f9d051..fa9e6582c5 100644 --- a/drivers/net/i40e/i40e_rxtx_vec_neon.c +++ b/drivers/net/i40e/i40e_rxtx_vec_neon.c @@ -177,19 +177,23 @@ descs_to_fdir_16b(uint32x4_t fltstat, uint64x2_t descs[4], struct rte_mbuf **rx_ uint32x4_t v_zeros = {0, 0, 0, 0}; uint32x4_t v_desc3_shift = vextq_u32(v_fdir_id_mask, v_zeros, 2); uint32x4_t v_desc3_mask = vandq_u32(v_desc_fdir_mask, v_desc3_shift); - descs[3] = vbslq_u32(v_desc3_mask, v_zeros, vreinterpretq_u32_u64(descs[3])); + descs[3] = vreinterpretq_u64_u32(vbslq_u32(v_desc3_mask, v_zeros, + vreinterpretq_u32_u64(descs[3]))); uint32x4_t v_desc2_shift = vextq_u32(v_fdir_id_mask, v_zeros, 1); uint32x4_t v_desc2_mask = vandq_u32(v_desc_fdir_mask, v_desc2_shift); - descs[2] = vbslq_u32(v_desc2_mask, v_zeros, vreinterpretq_u32_u64(descs[2])); + descs[2] = vreinterpretq_u64_u32(vbslq_u32(v_desc2_mask, v_zeros, + vreinterpretq_u32_u64(descs[2]))); uint32x4_t v_desc1_shift = v_fdir_id_mask; uint32x4_t v_desc1_mask = vandq_u32(v_desc_fdir_mask, v_desc1_shift); - descs[1] = vbslq_u32(v_desc1_mask, v_zeros, vreinterpretq_u32_u64(descs[1])); + descs[1] = vreinterpretq_u64_u32(vbslq_u32(v_desc1_mask, v_zeros, + vreinterpretq_u32_u64(descs[1]))); uint32x4_t v_desc0_shift = vextq_u32(v_zeros, v_fdir_id_mask, 3); uint32x4_t v_desc0_mask = vandq_u32(v_desc_fdir_mask, v_desc0_shift); - descs[0] = vbslq_u32(v_desc0_mask, v_zeros, vreinterpretq_u32_u64(descs[0])); + descs[0] = vreinterpretq_u64_u32(vbslq_u32(v_desc0_mask, v_zeros, + vreinterpretq_u32_u64(descs[0]))); /* Shift to 1 or 0 bit per u32 lane, then to RTE_MBUF_F_RX_FDIR_ID offset */ RTE_BUILD_BUG_ON(RTE_MBUF_F_RX_FDIR_ID != (1 << 13)); -- 2.25.1