From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BF858A0351; Fri, 4 Mar 2022 13:08:54 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4BB54427A9; Fri, 4 Mar 2022 13:08:54 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 6C6C64013F; Fri, 4 Mar 2022 13:08:52 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 2247N6E7002105; Fri, 4 Mar 2022 04:08:51 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=pfpt0220; bh=FzbVRAmzq8dsurdFXpfJCGruNA8u9frz3Ozh/CjQwrc=; b=boWNOvDQ3XeU45YUM2d5zfFDStObVNuMZaj+L69L5lYV1pfDVH2b6yt1w91eMB8bKckY P7brnEK0J8suau/5wUfp08vpWwq2iCadB701Dif1oPbtwb4NrUIpvOKsbXiE0H0DAHY5 r2yUHc6eGEcPDp3+OXlcXEz3IDcnSRD4lJ0104mDlLZgHszomjmv+Mys2KFnJRyoFl7f B2YBqBZkrSfIW1r8fNOEL3MXBc3gxoLJYb27H/C9ClYwSC/Wa67V8jPM4fhUp1JoqkCs HJNzYMQdDkqfXiPlQiY0q5NuLAxz0phpTnjPpaDpdqAlc2wduBqHmF0SzkEd3ExSdos8 Zw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3ek4j63c2a-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 04 Mar 2022 04:08:51 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 4 Mar 2022 04:08:49 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Fri, 4 Mar 2022 04:08:49 -0800 Received: from localhost.marvell.com (unknown [10.30.47.116]) by maili.marvell.com (Postfix) with ESMTP id 0359E3F7083; Fri, 4 Mar 2022 04:08:46 -0800 (PST) From: Devendra Singh Rawat To: , , , , CC: , Devendra Singh Rawat , Subject: [PATCH 1/3] net/qede: fix Tx callback completion routine Date: Fri, 4 Mar 2022 17:38:31 +0530 Message-ID: <20220304120833.312776-1-dsinghrawat@marvell.com> X-Mailer: git-send-email 2.18.2 MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: M5iUtdFMYt0qOJYsoHU5Sr2NVidaFo2w X-Proofpoint-ORIG-GUID: M5iUtdFMYt0qOJYsoHU5Sr2NVidaFo2w X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-04_02,2022-03-04_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Tx completion routine was first incrementing no. of free slots in Tx ring and then freeing corresponding mbufs in bulk. In some situations no. of mbufs freed were less than no. of Tx ring slots freed. This caused TX ring to get into an inconsistent state and ultimately application fails to transmit further traffic. The fix first updates Tx ring SW consumer index, then increments Tx ring free slot no. and finally frees the mbuf, this is done in a single iteration of loop. Fixes: 2c41740bf19e ("net/qede: get consumer index once") Fixes: 4996b959cde6 ("net/qede: free packets in bulk") Cc: stable@dpdk.org Signed-off-by: Devendra Singh Rawat Signed-off-by: Rasesh Mody --- drivers/net/qede/qede_rxtx.c | 79 +++++++++++++++--------------------- 1 file changed, 33 insertions(+), 46 deletions(-) diff --git a/drivers/net/qede/qede_rxtx.c b/drivers/net/qede/qede_rxtx.c index 911bb1a260..0c52568180 100644 --- a/drivers/net/qede/qede_rxtx.c +++ b/drivers/net/qede/qede_rxtx.c @@ -885,68 +885,55 @@ qede_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) } static inline void -qede_process_tx_compl(__rte_unused struct ecore_dev *edev, - struct qede_tx_queue *txq) +qede_free_tx_pkt(struct qede_tx_queue *txq) { - uint16_t hw_bd_cons; - uint16_t sw_tx_cons; - uint16_t remaining; - uint16_t mask; struct rte_mbuf *mbuf; uint16_t nb_segs; uint16_t idx; - uint16_t first_idx; - - rte_compiler_barrier(); - rte_prefetch0(txq->hw_cons_ptr); - sw_tx_cons = ecore_chain_get_cons_idx(&txq->tx_pbl); - hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr); -#ifdef RTE_LIBRTE_QEDE_DEBUG_TX - PMD_TX_LOG(DEBUG, txq, "Tx Completions = %u\n", - abs(hw_bd_cons - sw_tx_cons)); -#endif - - mask = NUM_TX_BDS(txq); - idx = txq->sw_tx_cons & mask; - remaining = hw_bd_cons - sw_tx_cons; - txq->nb_tx_avail += remaining; - first_idx = idx; - - while (remaining) { - mbuf = txq->sw_tx_ring[idx]; - RTE_ASSERT(mbuf); + idx = TX_CONS(txq); + mbuf = txq->sw_tx_ring[idx]; + if (mbuf) { nb_segs = mbuf->nb_segs; - remaining -= nb_segs; - - /* Prefetch the next mbuf. Note that at least the last 4 mbufs - * that are prefetched will not be used in the current call. - */ - rte_mbuf_prefetch_part1(txq->sw_tx_ring[(idx + 4) & mask]); - rte_mbuf_prefetch_part2(txq->sw_tx_ring[(idx + 4) & mask]); - PMD_TX_LOG(DEBUG, txq, "nb_segs to free %u\n", nb_segs); - while (nb_segs) { + /* It's like consuming rxbuf in recv() */ ecore_chain_consume(&txq->tx_pbl); + txq->nb_tx_avail++; nb_segs--; } - - idx = (idx + 1) & mask; + rte_pktmbuf_free(mbuf); + txq->sw_tx_ring[idx] = NULL; + txq->sw_tx_cons++; PMD_TX_LOG(DEBUG, txq, "Freed tx packet\n"); - } - txq->sw_tx_cons = idx; - - if (first_idx > idx) { - rte_pktmbuf_free_bulk(&txq->sw_tx_ring[first_idx], - mask - first_idx + 1); - rte_pktmbuf_free_bulk(&txq->sw_tx_ring[0], idx); } else { - rte_pktmbuf_free_bulk(&txq->sw_tx_ring[first_idx], - idx - first_idx); + ecore_chain_consume(&txq->tx_pbl); + txq->nb_tx_avail++; } } +static inline void +qede_process_tx_compl(__rte_unused struct ecore_dev *edev, + struct qede_tx_queue *txq) +{ + uint16_t hw_bd_cons; +#ifdef RTE_LIBRTE_QEDE_DEBUG_TX + uint16_t sw_tx_cons; +#endif + + hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr); + /* read barrier prevents speculative execution on stale data */ + rte_rmb(); + +#ifdef RTE_LIBRTE_QEDE_DEBUG_TX + sw_tx_cons = ecore_chain_get_cons_idx(&txq->tx_pbl); + PMD_TX_LOG(DEBUG, txq, "Tx Completions = %u\n", + abs(hw_bd_cons - sw_tx_cons)); +#endif + while (hw_bd_cons != ecore_chain_get_cons_idx(&txq->tx_pbl)) + qede_free_tx_pkt(txq); +} + static int qede_drain_txq(struct qede_dev *qdev, struct qede_tx_queue *txq, bool allow_drain) { -- 2.18.2