From: Wenjun Wu <wenjun1.wu@intel.com>
To: dev@dpdk.org, qiming.yang@intel.com, qi.z.zhang@intel.com
Cc: Wenjun Wu <wenjun1.wu@intel.com>
Subject: [PATCH v1] net/ice: support 256 queues
Date: Thu, 24 Mar 2022 13:12:32 +0800 [thread overview]
Message-ID: <20220324051232.170169-1-wenjun1.wu@intel.com> (raw)
256 queues can be allowed now. This patch improves the code
to support 256 queues for per PF.
Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>
---
drivers/net/ice/ice_ethdev.c | 8 ++++----
drivers/net/ice/ice_ethdev.h | 4 ++--
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c
index 13adcf90ed..73e550f5fb 100644
--- a/drivers/net/ice/ice_ethdev.c
+++ b/drivers/net/ice/ice_ethdev.c
@@ -808,7 +808,7 @@ ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
struct ice_aqc_vsi_props *info,
uint8_t enabled_tcmap)
{
- uint16_t bsf, qp_idx;
+ uint16_t fls, qp_idx;
/* default tc 0 now. Multi-TC supporting need to be done later.
* Configure TC and queue mapping parameters, for enabled TC,
@@ -820,15 +820,15 @@ ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
}
vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
- bsf = rte_bsf32(vsi->nb_qps);
+ fls = (vsi->nb_qps == 0) ? 0 : rte_fls_u32(vsi->nb_qps) - 1;
/* Adjust the queue number to actual queues that can be applied */
- vsi->nb_qps = 0x1 << bsf;
+ vsi->nb_qps = (vsi->nb_qps == 0) ? 0 : 0x1 << fls;
qp_idx = 0;
/* Set tc and queue mapping with VSI */
info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
ICE_AQ_VSI_TC_Q_OFFSET_S) |
- (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
+ (fls << ICE_AQ_VSI_TC_Q_NUM_S));
/* Associate queue number with VSI */
info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
diff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h
index 3ed580d438..09cfb60b0f 100644
--- a/drivers/net/ice/ice_ethdev.h
+++ b/drivers/net/ice/ice_ethdev.h
@@ -21,8 +21,8 @@
#define ICE_ADMINQ_BUF_SZ 4096
#define ICE_SBIOQ_BUF_SZ 4096
#define ICE_MAILBOXQ_BUF_SZ 4096
-/* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
-#define ICE_MAX_Q_PER_TC 64
+/* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64, 128, 256 */
+#define ICE_MAX_Q_PER_TC 256
#define ICE_NUM_DESC_DEFAULT 512
#define ICE_BUF_SIZE_MIN 1024
#define ICE_FRAME_SIZE_MAX 9728
--
2.25.1
next reply other threads:[~2022-03-24 5:34 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-24 5:12 Wenjun Wu [this message]
2022-03-24 8:28 ` Zhang, Qi Z
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