From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7EB17A00C3; Fri, 25 Mar 2022 11:59:56 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1F9CC40687; Fri, 25 Mar 2022 11:59:56 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 02D1240140; Fri, 25 Mar 2022 11:59:54 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 22P5xHF4022917; Fri, 25 Mar 2022 03:59:54 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=P9fLK8OCVfLcLW2tlPqvRlhxZYRsj/lapQIF4KlP8jw=; b=b/N2BlzkZJgq5ZMsuTeBg2uWUghWJ4yfIPY58XIObRvfZrNB423NtNUbg+0s52rFCmX9 nLf66DJkOeYhuwKwRF1XG2Va116COOw9V26P7B/1WslSqgoeaR7XXVN1G5RqZ7+hUTx6 RwxVY1bUWAoFfo6lybbdR38eY/0malEm53tkY8zzGX5GW1930T/ridylZZGip6vThVSa eQqGnuM2fP2tUJXWdrKNBU6MsZBpt5PgnSCbXmZj/X+cvAET1NtL7It9TW8I/cuw13Gk 9DIRSEnCfzUR0Ss/vI+AfcbHnuCBqhrEA3qkd73a5v8rw7ntL8B/KVUveGa3c3rtMJYV xQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3f0mn6x44r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 25 Mar 2022 03:59:54 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 25 Mar 2022 03:59:52 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 25 Mar 2022 03:59:52 -0700 Received: from localhost.localdomain (unknown [10.28.34.39]) by maili.marvell.com (Postfix) with ESMTP id 024C33F704C; Fri, 25 Mar 2022 03:59:49 -0700 (PDT) From: Volodymyr Fialko To: , Ankur Dwivedi , Anoob Joseph , Tejasree Kondoj , "Pavan Nikhilesh" , Shijith Thotton CC: , Volodymyr Fialko , Subject: [PATCH] event/cnxk: fix base pointer for SSO head wait Date: Fri, 25 Mar 2022 11:59:39 +0100 Message-ID: <20220325105939.1117634-1-vfialko@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: KX_LL-p8bCXY_ZfEze8HWtcxjOd5PptF X-Proofpoint-ORIG-GUID: KX_LL-p8bCXY_ZfEze8HWtcxjOd5PptF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.850,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-25_02,2022-03-24_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Function roc_sso_hws_head_wait() expects a base as input pointer, and it will itself get tag_op from the base. By passing tag_op instead of base pointer to this function will add SSOW_LF_GWS_TAG register offset twice, which will lead to accessing wrong register. Fixes: 1f5b3d55c041 ("event/cnxk: store and reuse workslot status") Cc: stable@dpdk.org Signed-off-by: Volodymyr Fialko --- drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 4 ++-- drivers/crypto/cnxk/cn10k_cryptodev_ops.h | 2 +- drivers/crypto/cnxk/cn9k_cryptodev_ops.c | 4 ++-- drivers/crypto/cnxk/cn9k_cryptodev_ops.h | 2 +- drivers/event/cnxk/cn10k_worker.c | 3 +-- drivers/event/cnxk/cn9k_worker.c | 7 +++---- 6 files changed, 10 insertions(+), 12 deletions(-) diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c index d217bbf383..1b08c67fea 100644 --- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c @@ -265,7 +265,7 @@ cn10k_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops) } uint16_t -cn10k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, struct rte_crypto_op *op) +cn10k_cpt_crypto_adapter_enqueue(uintptr_t base, struct rte_crypto_op *op) { union rte_event_crypto_metadata *ec_mdata; struct cpt_inflight_req *infl_req; @@ -328,7 +328,7 @@ cn10k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, struct rte_crypto_op *op) } if (!rsp_info->sched_type) - roc_sso_hws_head_wait(tag_op); + roc_sso_hws_head_wait(base); lmt_arg = ROC_CN10K_CPT_LMT_ARG | (uint64_t)lmt_id; roc_lmt_submit_steorl(lmt_arg, qp->lmtline.io_addr); diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.h b/drivers/crypto/cnxk/cn10k_cryptodev_ops.h index d7e9f87396..1ad4c16873 100644 --- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.h +++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.h @@ -13,7 +13,7 @@ extern struct rte_cryptodev_ops cn10k_cpt_ops; void cn10k_cpt_set_enqdeq_fns(struct rte_cryptodev *dev); __rte_internal -uint16_t cn10k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, +uint16_t cn10k_cpt_crypto_adapter_enqueue(uintptr_t base, struct rte_crypto_op *op); __rte_internal uintptr_t cn10k_cpt_crypto_adapter_dequeue(uintptr_t get_work1); diff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c index ddba9d5dd0..d3858149c7 100644 --- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c @@ -317,7 +317,7 @@ cn9k_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops) } uint16_t -cn9k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, struct rte_crypto_op *op) +cn9k_cpt_crypto_adapter_enqueue(uintptr_t base, struct rte_crypto_op *op) { union rte_event_crypto_metadata *ec_mdata; struct cpt_inflight_req *infl_req; @@ -374,7 +374,7 @@ cn9k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, struct rte_crypto_op *op) } if (!rsp_info->sched_type) - roc_sso_hws_head_wait(tag_op); + roc_sso_hws_head_wait(base); cn9k_cpt_inst_submit(&inst, qp->lmtline.lmt_base, qp->lmtline.io_addr); diff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.h b/drivers/crypto/cnxk/cn9k_cryptodev_ops.h index 309f507346..9f6dc24603 100644 --- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.h +++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.h @@ -12,7 +12,7 @@ extern struct rte_cryptodev_ops cn9k_cpt_ops; void cn9k_cpt_set_enqdeq_fns(struct rte_cryptodev *dev); __rte_internal -uint16_t cn9k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, +uint16_t cn9k_cpt_crypto_adapter_enqueue(uintptr_t base, struct rte_crypto_op *op); __rte_internal uintptr_t cn9k_cpt_crypto_adapter_dequeue(uintptr_t get_work1); diff --git a/drivers/event/cnxk/cn10k_worker.c b/drivers/event/cnxk/cn10k_worker.c index 975a22336a..1ffd48a5ab 100644 --- a/drivers/event/cnxk/cn10k_worker.c +++ b/drivers/event/cnxk/cn10k_worker.c @@ -68,6 +68,5 @@ cn10k_sso_hws_ca_enq(void *port, struct rte_event ev[], uint16_t nb_events) RTE_SET_USED(nb_events); - return cn10k_cpt_crypto_adapter_enqueue(ws->base + SSOW_LF_GWS_TAG, - ev->event_ptr); + return cn10k_cpt_crypto_adapter_enqueue(ws->base, ev->event_ptr); } diff --git a/drivers/event/cnxk/cn9k_worker.c b/drivers/event/cnxk/cn9k_worker.c index a981bc986f..fca1f0dffa 100644 --- a/drivers/event/cnxk/cn9k_worker.c +++ b/drivers/event/cnxk/cn9k_worker.c @@ -128,8 +128,7 @@ cn9k_sso_hws_ca_enq(void *port, struct rte_event ev[], uint16_t nb_events) RTE_SET_USED(nb_events); - return cn9k_cpt_crypto_adapter_enqueue(ws->base + SSOW_LF_GWS_TAG, - ev->event_ptr); + return cn9k_cpt_crypto_adapter_enqueue(ws->base, ev->event_ptr); } uint16_t __rte_hot @@ -139,6 +138,6 @@ cn9k_sso_hws_dual_ca_enq(void *port, struct rte_event ev[], uint16_t nb_events) RTE_SET_USED(nb_events); - return cn9k_cpt_crypto_adapter_enqueue( - dws->base[!dws->vws] + SSOW_LF_GWS_TAG, ev->event_ptr); + return cn9k_cpt_crypto_adapter_enqueue(dws->base[!dws->vws], + ev->event_ptr); } -- 2.25.1