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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.234) by DM6NAM11FT061.mail.protection.outlook.com (10.13.173.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5123.19 via Frontend Transport; Fri, 1 Apr 2022 03:22:58 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Fri, 1 Apr 2022 03:22:58 +0000 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 31 Mar 2022 20:22:55 -0700 From: Spike Du To: , , , CC: , Subject: [RFC 1/6] net/mlx5: add LWM support for Rxq Date: Fri, 1 Apr 2022 06:22:27 +0300 Message-ID: <20220401032232.1267376-2-spiked@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220401032232.1267376-1-spiked@nvidia.com> References: <20220401032232.1267376-1-spiked@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 49bbf954-b03f-4802-347e-08da138eebca X-MS-TrafficTypeDiagnostic: MW2PR12MB2410:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Apr 2022 03:22:58.7277 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 49bbf954-b03f-4802-347e-08da138eebca X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT061.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW2PR12MB2410 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add lwm(Limit WaterMark) field to Rxq object which indicates the percentage of RX queue size used by HW to raise LWM event to the user. Allow LWM setting in modify_rq command. Allow the LWM configuration dynamically by adding RDY2RDY state change. Signed-off-by: Spike Du --- drivers/net/mlx5/mlx5.h | 1 + drivers/net/mlx5/mlx5_devx.c | 10 +++++++++- drivers/net/mlx5/mlx5_devx.h | 1 + drivers/net/mlx5/mlx5_rx.h | 1 + 4 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 23a28f6..f3e6682 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1391,6 +1391,7 @@ enum mlx5_rxq_modify_type { MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */ MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */ MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */ + MLX5_RXQ_MOD_RDY2RDY, /* modify state from ready to ready. */ }; enum mlx5_txq_modify_type { diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index af106bd..d6de882 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -62,7 +62,7 @@ * @return * 0 on success, a negative errno value otherwise and rte_errno is set. */ -static int +int mlx5_devx_modify_rq(struct mlx5_rxq_priv *rxq, uint8_t type) { struct mlx5_devx_modify_rq_attr rq_attr; @@ -76,6 +76,8 @@ case MLX5_RXQ_MOD_RST2RDY: rq_attr.rq_state = MLX5_RQC_STATE_RST; rq_attr.state = MLX5_RQC_STATE_RDY; + rq_attr.modify_bitmask |= MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM; + rq_attr.lwm = rxq->lwm; break; case MLX5_RXQ_MOD_RDY2ERR: rq_attr.rq_state = MLX5_RQC_STATE_RDY; @@ -85,6 +87,12 @@ rq_attr.rq_state = MLX5_RQC_STATE_RDY; rq_attr.state = MLX5_RQC_STATE_RST; break; + case MLX5_RXQ_MOD_RDY2RDY: + rq_attr.rq_state = MLX5_RQC_STATE_RDY; + rq_attr.state = MLX5_RQC_STATE_RDY; + rq_attr.modify_bitmask |= MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM; + rq_attr.lwm = rxq->lwm; + break; default: break; } diff --git a/drivers/net/mlx5/mlx5_devx.h b/drivers/net/mlx5/mlx5_devx.h index a95207a..ebd1da4 100644 --- a/drivers/net/mlx5/mlx5_devx.h +++ b/drivers/net/mlx5/mlx5_devx.h @@ -11,6 +11,7 @@ int mlx5_txq_devx_modify(struct mlx5_txq_obj *obj, enum mlx5_txq_modify_type type, uint8_t dev_port); void mlx5_txq_devx_obj_release(struct mlx5_txq_obj *txq_obj); +int mlx5_devx_modify_rq(struct mlx5_rxq_priv *rxq, uint8_t type); extern struct mlx5_obj_ops devx_obj_ops; diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h index acebe33..98d7cae 100644 --- a/drivers/net/mlx5/mlx5_rx.h +++ b/drivers/net/mlx5/mlx5_rx.h @@ -174,6 +174,7 @@ struct mlx5_rxq_priv { struct mlx5_devx_rq devx_rq; struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */ uint32_t hairpin_status; /* Hairpin binding status. */ + uint32_t lwm:16; }; /* External RX queue descriptor. */ -- 1.8.3.1