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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.236 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.236; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.236) by DM6NAM11FT055.mail.protection.outlook.com (10.13.173.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5144.20 via Frontend Transport; Sun, 10 Apr 2022 18:26:40 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL109.nvidia.com (10.27.9.19) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Sun, 10 Apr 2022 18:26:39 +0000 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sun, 10 Apr 2022 11:26:38 -0700 From: Raja Zidane To: CC: Subject: [RFC] compress/mlx5: add support for LZ4 decompress Date: Sun, 10 Apr 2022 21:26:22 +0300 Message-ID: <20220410182622.8828-1-rzidane@nvidia.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 071283ff-3532-45f9-586d-08da1b1fa7f6 X-MS-TrafficTypeDiagnostic: CH2PR12MB5514:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2022 18:26:40.1128 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 071283ff-3532-45f9-586d-08da1b1fa7f6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB5514 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org LZ4 decompress will be supported starting from BlueField3. Add LZ4 params struct to RTE XFORM struct. Add case to check for LZ4 algo, and pass params from RTE XFORM. Signed-off-by: Raja Zidane --- drivers/common/mlx5/mlx5_prm.h | 6 +++++ drivers/compress/mlx5/mlx5_compress.c | 29 +++++++++++++++++++++++ lib/compressdev/rte_comp.h | 34 +++++++++++++++++++++++---- 3 files changed, 64 insertions(+), 5 deletions(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 2ded67e85e..b89bf922b8 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -548,9 +548,15 @@ struct mlx5_rdma_write_wqe { #define MLX5_OPC_MOD_MMO_DECOMP 0x3u #define MLX5_OPC_MOD_MMO_DMA 0x1u +#define WQE_GGA_DECOMP_DEFLATE 0x0u +#define WQE_GGA_DECOMP_SNAPPY 0x1u +#define WQE_GGA_DECOMP_LZ4 0x2u + #define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u #define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u #define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u +#define WQE_GGA_DECOMP_PARAMS_OFFSET 20u +#define WQE_GGA_DECOMP_TYPE_OFFSET 8u #define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u #define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS) #define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index 82b871bd86..4994e38ab6 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -298,6 +298,10 @@ mlx5_compress_xform_create(struct rte_compressdev *dev, DRV_LOG(ERR, "Not enough capabilities to support compress operation, maybe old FW/OFED version?"); return -ENOTSUP; } + if (xform->compress.algo == RTE_COMP_ALGO_LZ4) { + DRV_LOG(ERR, "LZ4 compression is not supported."); + return -ENOTSUP; + } if (xform->compress.level == RTE_COMP_LEVEL_NONE) { DRV_LOG(ERR, "Non-compressed block is not supported."); return -ENOTSUP; @@ -371,6 +375,31 @@ mlx5_compress_xform_create(struct rte_compressdev *dev, case RTE_COMP_ALGO_DEFLATE: xfrm->opcode += MLX5_OPC_MOD_MMO_DECOMP << WQE_CSEG_OPC_MOD_OFFSET; + xfrm->gga_ctrl1 += WQE_GGA_DECOMP_DEFLATE << + WQE_GGA_DECOMP_TYPE_OFFSET; + break; + case RTE_COMP_ALGO_LZ4: + xfrm->opcode += MLX5_OPC_MOD_MMO_DECOMP << + WQE_CSEG_OPC_MOD_OFFSET; + xfrm->gga_ctrl1 += WQE_GGA_DECOMP_LZ4 << + WQE_GGA_DECOMP_TYPE_OFFSET; + switch (xform->decompress.lz4.lz4) { + case RTE_COMP_LZ4_DATA_ONLY: + xfrm->gga_ctrl1 += 0u << + WQE_GGA_DECOMP_PARAMS_OFFSET; + break; + case RTE_COMP_LZ4_BLOCK_WITHOUT_CHECKSUM: + xfrm->gga_ctrl1 += 1u << + WQE_GGA_DECOMP_PARAMS_OFFSET; + break; + case RTE_COMP_LZ4_BLOCK_WITH_CHECKSUM: + xfrm->gga_ctrl1 += 2u << + WQE_GGA_DECOMP_PARAMS_OFFSET; + break; + default: + xfrm->gga_ctrl1 += 0u << + WQE_GGA_DECOMP_PARAMS_OFFSET; + } break; default: goto err; diff --git a/lib/compressdev/rte_comp.h b/lib/compressdev/rte_comp.h index 95306c5d03..2a0cd79873 100644 --- a/lib/compressdev/rte_comp.h +++ b/lib/compressdev/rte_comp.h @@ -109,6 +109,10 @@ enum rte_comp_algorithm { /**< LZS compression algorithm * https://tools.ietf.org/html/rfc2395 */ + RTE_COMP_ALGO_LZ4, + /**< LZ4 compression algorithm + * + */ RTE_COMP_ALGO_LIST_END }; @@ -162,6 +166,14 @@ enum rte_comp_huffman { /**< Use Dynamic Huffman codes */ }; +enum rte_comp_lz4 { + RTE_COMP_LZ4_DEFAULT, + /**< PMD may choose which LZ4 codes to use */ + RTE_COMP_LZ4_DATA_ONLY, + RTE_COMP_LZ4_BLOCK_WITHOUT_CHECKSUM, + RTE_COMP_LZ4_BLOCK_WITH_CHECKSUM, +}; + /** Compression flush flags */ enum rte_comp_flush_flag { RTE_COMP_FLUSH_NONE, @@ -215,6 +227,12 @@ struct rte_comp_deflate_params { /**< Compression huffman encoding type */ }; +/** Parameters specific to the lz4 algorithm */ +struct rte_comp_lz4_params { + enum rte_comp_lz4 lz4; + /**< Compression LZ4 encoding type */ +}; + /** Setup Data for compression */ struct rte_comp_compress_xform { enum rte_comp_algorithm algo; @@ -222,6 +240,8 @@ struct rte_comp_compress_xform { union { struct rte_comp_deflate_params deflate; /**< Parameters specific to the deflate algorithm */ + struct rte_comp_lz4_params lz4; + /**< Parameters specific to the lz4 algorithm */ }; /**< Algorithm specific parameters */ int level; /**< Compression level */ @@ -246,11 +266,15 @@ struct rte_comp_decompress_xform { /**< Algorithm to use for decompression */ enum rte_comp_checksum_type chksum; /**< Type of checksum to generate on the decompressed data */ - uint8_t window_size; - /**< Base two log value of sliding window which was used to generate - * compressed data. If window size can't be supported by the PMD then - * setup of stream or private_xform should fail. - */ + union { + uint8_t window_size; + /**< Base two log value of sliding window which was used to generate + * compressed data. If window size can't be supported by the PMD then + * setup of stream or private_xform should fail. + */ + struct rte_comp_lz4_params lz4; + /**< Parameters specific to the lz4 algorithm */ + }; enum rte_comp_hash_algorithm hash_algo; /**< Hash algorithm to be used with decompress operation. Hash is always * done on plaintext. -- 2.21.0