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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.236 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.236; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.236) by BN8NAM11FT022.mail.protection.outlook.com (10.13.176.112) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5186.14 via Frontend Transport; Wed, 20 Apr 2022 15:32:34 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL109.nvidia.com (10.27.9.19) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Wed, 20 Apr 2022 15:32:33 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 20 Apr 2022 08:32:31 -0700 From: Raja Zidane To: CC: , , Subject: [PATCH] net/mlx5: fix rxq/txq stats memory access sync Date: Wed, 20 Apr 2022 18:32:17 +0300 Message-ID: <20220420153217.10723-1-rzidane@nvidia.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 94c4e7ce-2053-4970-c187-08da22e2fdc4 X-MS-TrafficTypeDiagnostic: BYAPR12MB2790:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2022 15:32:34.0111 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 94c4e7ce-2053-4970-c187-08da22e2fdc4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB2790 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Queue statistics are being continuously updated in Rx/Tx burst routines while handling traffic. In addition to that, statistics can be reset (written with zeroes) on statistics reset in other threads, causing a race condition, which in turn could result in wrong stats. The patch provides an approach with reference values, allowing the actual counters to be writable within Rx/Tx burst threads only, and updating reference values on stats reset. Fixes: 87011737b715 ("mlx5: add software counters") Cc: stable@dpdk.org Signed-off-by: Raja Zidane Acked-by: Slava Ovsiienko --- drivers/net/mlx5/mlx5_rx.h | 1 + drivers/net/mlx5/mlx5_stats.c | 40 +++++++++++++++++++++-------------- drivers/net/mlx5/mlx5_tx.h | 1 + 3 files changed, 26 insertions(+), 16 deletions(-) diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h index 5bf88b6181..e715ed6b62 100644 --- a/drivers/net/mlx5/mlx5_rx.h +++ b/drivers/net/mlx5/mlx5_rx.h @@ -126,6 +126,7 @@ struct mlx5_rxq_data { struct mlx5_dev_ctx_shared *sh; /* Shared context. */ uint16_t idx; /* Queue index. */ struct mlx5_rxq_stats stats; + struct mlx5_rxq_stats stats_reset; /* stats on last reset. */ rte_xmm_t mbuf_initializer; /* Default rearm/flags for vectorized Rx. */ struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */ struct mlx5_uar_data uar_data; /* CQ doorbell. */ diff --git a/drivers/net/mlx5/mlx5_stats.c b/drivers/net/mlx5/mlx5_stats.c index 732775954a..f64fa3587b 100644 --- a/drivers/net/mlx5/mlx5_stats.c +++ b/drivers/net/mlx5/mlx5_stats.c @@ -114,18 +114,23 @@ mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) idx = rxq->idx; if (idx < RTE_ETHDEV_QUEUE_STAT_CNTRS) { #ifdef MLX5_PMD_SOFT_COUNTERS - tmp.q_ipackets[idx] += rxq->stats.ipackets; - tmp.q_ibytes[idx] += rxq->stats.ibytes; + tmp.q_ipackets[idx] += rxq->stats.ipackets - + rxq->stats_reset.ipackets; + tmp.q_ibytes[idx] += rxq->stats.ibytes - + rxq->stats_reset.ibytes; #endif tmp.q_errors[idx] += (rxq->stats.idropped + - rxq->stats.rx_nombuf); + rxq->stats.rx_nombuf) - + (rxq->stats_reset.idropped + + rxq->stats_reset.rx_nombuf); } #ifdef MLX5_PMD_SOFT_COUNTERS - tmp.ipackets += rxq->stats.ipackets; - tmp.ibytes += rxq->stats.ibytes; + tmp.ipackets += rxq->stats.ipackets - rxq->stats_reset.ipackets; + tmp.ibytes += rxq->stats.ibytes - rxq->stats_reset.ibytes; #endif - tmp.ierrors += rxq->stats.idropped; - tmp.rx_nombuf += rxq->stats.rx_nombuf; + tmp.ierrors += rxq->stats.idropped - rxq->stats_reset.idropped; + tmp.rx_nombuf += rxq->stats.rx_nombuf - + rxq->stats_reset.rx_nombuf; } for (i = 0; (i != priv->txqs_n); ++i) { struct mlx5_txq_data *txq = (*priv->txqs)[i]; @@ -135,15 +140,17 @@ mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) idx = txq->idx; if (idx < RTE_ETHDEV_QUEUE_STAT_CNTRS) { #ifdef MLX5_PMD_SOFT_COUNTERS - tmp.q_opackets[idx] += txq->stats.opackets; - tmp.q_obytes[idx] += txq->stats.obytes; + tmp.q_opackets[idx] += txq->stats.opackets - + txq->stats_reset.opackets; + tmp.q_obytes[idx] += txq->stats.obytes - + txq->stats_reset.obytes; #endif } #ifdef MLX5_PMD_SOFT_COUNTERS - tmp.opackets += txq->stats.opackets; - tmp.obytes += txq->stats.obytes; + tmp.opackets += txq->stats.opackets - txq->stats_reset.opackets; + tmp.obytes += txq->stats.obytes - txq->stats_reset.obytes; #endif - tmp.oerrors += txq->stats.oerrors; + tmp.oerrors += txq->stats.oerrors - txq->stats_reset.oerrors; } ret = mlx5_os_read_dev_stat(priv, "out_of_buffer", &tmp.imissed); if (ret == 0) { @@ -185,13 +192,14 @@ mlx5_stats_reset(struct rte_eth_dev *dev) if (rxq_data == NULL) continue; - memset(&rxq_data->stats, 0, sizeof(struct mlx5_rxq_stats)); + rxq_data->stats_reset = rxq_data->stats; } for (i = 0; (i != priv->txqs_n); ++i) { - if ((*priv->txqs)[i] == NULL) + struct mlx5_txq_data *txq_data = (*priv->txqs)[i]; + + if (txq_data == NULL) continue; - memset(&(*priv->txqs)[i]->stats, 0, - sizeof(struct mlx5_txq_stats)); + txq_data->stats_reset = txq_data->stats; } mlx5_os_read_dev_stat(priv, "out_of_buffer", &stats_ctrl->imissed_base); stats_ctrl->imissed = 0; diff --git a/drivers/net/mlx5/mlx5_tx.h b/drivers/net/mlx5/mlx5_tx.h index dfa04612ff..20776919c2 100644 --- a/drivers/net/mlx5/mlx5_tx.h +++ b/drivers/net/mlx5/mlx5_tx.h @@ -164,6 +164,7 @@ struct mlx5_txq_data { int32_t ts_offset; /* Timestamp field dynamic offset. */ struct mlx5_dev_ctx_shared *sh; /* Shared context. */ struct mlx5_txq_stats stats; /* TX queue counters. */ + struct mlx5_txq_stats stats_reset; /* stats on last reset. */ struct mlx5_uar_data uar_data; struct rte_mbuf *elts[0]; /* Storage for queued packets, must be the last field. */ -- 2.21.0