From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 39E3AA00BE; Fri, 22 Apr 2022 12:48:30 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0DD32427FB; Fri, 22 Apr 2022 12:47:54 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 759A7427EB for ; Fri, 22 Apr 2022 12:47:52 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 23M0bigT003185 for ; Fri, 22 Apr 2022 03:47:51 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=3hfSLoLJa01oxMl0BXgQasi/inHcb323KecGr9c0ffU=; b=IR6+9GqTkzXIsXYW8vJDWGdxKs0kAo5Pg1hcafD0xVLCz6qkDl1FnjuxY09e0tM7TxAj J61wgt4V116SPIOLAWqFANZLCYAh0nMnCoramh1o32fffiYzkx1t6Yc+xfRt+WwpkrWE 7HpoaKVnm5r/Ez3zU7e1aQ6VFzItpowrZxuGyyypvBwuc6S6L42TMCViPfADg3m0lxxW WILPBajDmzs0hPrWPUxogS+E3xMhTZ6u5ToO1jkDzMIrwT+p3kwHwR9VZu/B31WZVNTc EwpHtLPhVZbM7nZYFtn6j/XPQT8ZCaz1rHhDaw6eMvLp+Iqbqa4sHPrWCOkjYZarua1o tQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3fk7mk44bd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 22 Apr 2022 03:47:51 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 22 Apr 2022 03:47:50 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 22 Apr 2022 03:47:50 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 0D7163F707F; Fri, 22 Apr 2022 03:47:47 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: Subject: [PATCH v2 13/28] net/cnxk: disable default inner chksum for outb inline Date: Fri, 22 Apr 2022 16:16:54 +0530 Message-ID: <20220422104709.20722-13-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220422104709.20722-1-ndabilpuram@marvell.com> References: <20220422104709.20722-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: -YAZYWFMTiZj5dt6ftzj8X4TdUvv1DB- X-Proofpoint-GUID: -YAZYWFMTiZj5dt6ftzj8X4TdUvv1DB- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-04-22_02,2022-04-22_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Disable default inner L3/L4 checksum generation for outbound inline path and enable based on SA options or RTE_MBUF flags as per the spec. Though the checksum generation is not impacting much performance, it is overwriting zero checksum for UDP packets which is not always good. Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cn10k_ethdev.h | 4 +++- drivers/net/cnxk/cn10k_ethdev_sec.c | 3 +++ drivers/net/cnxk/cn10k_tx.h | 44 ++++++++++++++++++++++++++++++------- 3 files changed, 42 insertions(+), 9 deletions(-) diff --git a/drivers/net/cnxk/cn10k_ethdev.h b/drivers/net/cnxk/cn10k_ethdev.h index 1e49d65..9642d6a 100644 --- a/drivers/net/cnxk/cn10k_ethdev.h +++ b/drivers/net/cnxk/cn10k_ethdev.h @@ -71,7 +71,9 @@ struct cn10k_sec_sess_priv { uint8_t mode : 1; uint8_t roundup_byte : 5; uint8_t roundup_len; - uint16_t partial_len; + uint16_t partial_len : 10; + uint16_t chksum : 2; + uint16_t rsvd : 4; }; uint64_t u64; diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c index 87bb691..b307215 100644 --- a/drivers/net/cnxk/cn10k_ethdev_sec.c +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c @@ -552,6 +552,9 @@ cn10k_eth_sec_session_create(void *device, sess_priv.partial_len = rlens->partial_len; sess_priv.mode = outb_sa_dptr->w2.s.ipsec_mode; sess_priv.outer_ip_ver = outb_sa_dptr->w2.s.outer_ip_ver; + /* Propagate inner checksum enable from SA to fast path */ + sess_priv.chksum = (!ipsec->options.ip_csum_enable << 1 | + !ipsec->options.l4_csum_enable); /* Pointer from eth_sec -> outb_sa */ eth_sec->sa = outb_sa; diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h index de88a21..981bc9b 100644 --- a/drivers/net/cnxk/cn10k_tx.h +++ b/drivers/net/cnxk/cn10k_tx.h @@ -246,6 +246,7 @@ cn10k_nix_prep_sec_vec(struct rte_mbuf *m, uint64x2_t *cmd0, uint64x2_t *cmd1, { struct cn10k_sec_sess_priv sess_priv; uint32_t pkt_len, dlen_adj, rlen; + uint8_t l3l4type, chksum; uint64x2_t cmd01, cmd23; uintptr_t dptr, nixtx; uint64_t ucode_cmd[4]; @@ -256,10 +257,23 @@ cn10k_nix_prep_sec_vec(struct rte_mbuf *m, uint64x2_t *cmd0, uint64x2_t *cmd1, sess_priv.u64 = *rte_security_dynfield(m); - if (flags & NIX_TX_NEED_SEND_HDR_W1) + if (flags & NIX_TX_NEED_SEND_HDR_W1) { l2_len = vgetq_lane_u8(*cmd0, 8); - else + /* Extract l3l4type either from il3il4type or ol3ol4type */ + if (flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F && + flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F) + l3l4type = vgetq_lane_u8(*cmd0, 13); + else + l3l4type = vgetq_lane_u8(*cmd0, 12); + + chksum = (l3l4type & 0x1) << 1 | !!(l3l4type & 0x30); + chksum = ~chksum; + sess_priv.chksum = sess_priv.chksum & chksum; + /* Clear SEND header flags */ + *cmd0 = vsetq_lane_u16(0, *cmd0, 6); + } else { l2_len = m->l2_len; + } /* Retrieve DPTR */ dptr = vgetq_lane_u64(*cmd1, 1); @@ -291,8 +305,8 @@ cn10k_nix_prep_sec_vec(struct rte_mbuf *m, uint64x2_t *cmd0, uint64x2_t *cmd1, sa_base &= ~0xFFFFUL; sa = (uintptr_t)roc_nix_inl_ot_ipsec_outb_sa(sa_base, sess_priv.sa_idx); ucode_cmd[3] = (ROC_CPT_DFLT_ENG_GRP_SE_IE << 61 | 1UL << 60 | sa); - ucode_cmd[0] = - (ROC_IE_OT_MAJOR_OP_PROCESS_OUTBOUND_IPSEC << 48 | pkt_len); + ucode_cmd[0] = (ROC_IE_OT_MAJOR_OP_PROCESS_OUTBOUND_IPSEC << 48 | + ((uint64_t)sess_priv.chksum) << 32 | pkt_len); /* CPT Word 0 and Word 1 */ cmd01 = vdupq_n_u64((nixtx + 16) | (cn10k_nix_tx_ext_subs(flags) + 1)); @@ -343,6 +357,7 @@ cn10k_nix_prep_sec(struct rte_mbuf *m, uint64_t *cmd, uintptr_t *nixtx_addr, struct cn10k_sec_sess_priv sess_priv; uint32_t pkt_len, dlen_adj, rlen; struct nix_send_hdr_s *send_hdr; + uint8_t l3l4type, chksum; uint64x2_t cmd01, cmd23; union nix_send_sg_s *sg; uintptr_t dptr, nixtx; @@ -360,10 +375,23 @@ cn10k_nix_prep_sec(struct rte_mbuf *m, uint64_t *cmd, uintptr_t *nixtx_addr, else sg = (union nix_send_sg_s *)&cmd[2]; - if (flags & NIX_TX_NEED_SEND_HDR_W1) + if (flags & NIX_TX_NEED_SEND_HDR_W1) { l2_len = cmd[1] & 0xFF; - else + /* Extract l3l4type either from il3il4type or ol3ol4type */ + if (flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F && + flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F) + l3l4type = (cmd[1] >> 40) & 0xFF; + else + l3l4type = (cmd[1] >> 32) & 0xFF; + + chksum = (l3l4type & 0x1) << 1 | !!(l3l4type & 0x30); + chksum = ~chksum; + sess_priv.chksum = sess_priv.chksum & chksum; + /* Clear SEND header flags */ + cmd[1] &= ~(0xFFFFUL << 32); + } else { l2_len = m->l2_len; + } /* Retrieve DPTR */ dptr = *(uint64_t *)(sg + 1); @@ -395,8 +423,8 @@ cn10k_nix_prep_sec(struct rte_mbuf *m, uint64_t *cmd, uintptr_t *nixtx_addr, sa_base &= ~0xFFFFUL; sa = (uintptr_t)roc_nix_inl_ot_ipsec_outb_sa(sa_base, sess_priv.sa_idx); ucode_cmd[3] = (ROC_CPT_DFLT_ENG_GRP_SE_IE << 61 | 1UL << 60 | sa); - ucode_cmd[0] = - (ROC_IE_OT_MAJOR_OP_PROCESS_OUTBOUND_IPSEC << 48 | pkt_len); + ucode_cmd[0] = (ROC_IE_OT_MAJOR_OP_PROCESS_OUTBOUND_IPSEC << 48 | + ((uint64_t)sess_priv.chksum) << 32 | pkt_len); /* CPT Word 0 and Word 1. Assume no multi-seg support */ cmd01 = vdupq_n_u64((nixtx + 16) | (cn10k_nix_tx_ext_subs(flags) + 1)); -- 2.8.4