From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1CF2FA0093; Fri, 22 Apr 2022 12:49:13 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4F691410E7; Fri, 22 Apr 2022 12:48:14 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 9197242837 for ; Fri, 22 Apr 2022 12:48:13 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 23M0paFW027292 for ; Fri, 22 Apr 2022 03:48:12 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=C/PHgs2NLXWE2k/8dn5hVKTSy3pYVhlcHJ2QrQ4/G5k=; b=DECHTfrdC/bTkoCR56gDR3jG0NJP7asVBei49rsS1+0kq1RwyS2Yp5fnOscNF9pPZiR1 BDcZfqW0hMbRDRombhnn7KbTtxHCkFDXHrHurywXHIkkSZqnlgT9iJaHCi7I9rF+X+uG Ik3IYpD82U5mB8caJkCCyenU/ApkRlCHzW/bZKtpo5Auj82BN8lV/d54AfktLLRggt1S JYya8w1OY2OrpyOSRa+6zNHSOqSvUjgBs4meR/sHeektExApiALI+Yc0UuKaynW8aT3e UMg3NOg1ZEy0QzL5fOFWNVul2ciIkrhSAqE8vP55JtCKLldT8khkuuqSegjDrfIGN8+p yQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3fhtapp13x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 22 Apr 2022 03:48:12 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 22 Apr 2022 03:48:10 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 22 Apr 2022 03:48:10 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 4C0CB3F707F; Fri, 22 Apr 2022 03:48:07 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , Akhil Goyal Subject: [PATCH v2 20/28] net/cnxk: update olflags with L3/L4 csum offload Date: Fri, 22 Apr 2022 16:17:01 +0530 Message-ID: <20220422104709.20722-20-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220422104709.20722-1-ndabilpuram@marvell.com> References: <20220422104709.20722-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: W5YUFuGJ6isknjLsSx2vyANLx52pzob5 X-Proofpoint-ORIG-GUID: W5YUFuGJ6isknjLsSx2vyANLx52pzob5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-04-22_02,2022-04-22_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Akhil Goyal When the packet is processed with inline IPsec offload, the ol_flags were updated only with RTE_MBUF_F_RX_SEC_OFFLOAD. But the hardware can also update the L3/L4 csum offload flags. Hence, ol_flags are updated with RTE_MBUF_F_RX_IP_CKSUM_GOOD, RTE_MBUF_F_RX_L4_CKSUM_GOOD, etc based on the microcode completion codes. Signed-off-by: Akhil Goyal Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cn10k_rx.h | 51 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h index 14b634e..00bec01 100644 --- a/drivers/net/cnxk/cn10k_rx.h +++ b/drivers/net/cnxk/cn10k_rx.h @@ -42,6 +42,18 @@ (uint64_t *)(((uintptr_t)((uint64_t *)(b))[i]) - (o)) : \ (uint64_t *)(((uintptr_t)(b)) + CQE_SZ(i) - (o))) +#define NIX_RX_SEC_UCC_CONST \ + ((RTE_MBUF_F_RX_IP_CKSUM_BAD >> 1) << 8 | \ + ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1) \ + << 24 | \ + ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1) \ + << 32 | \ + ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1) \ + << 40 | \ + ((RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1) \ + << 48 | \ + (RTE_MBUF_F_RX_IP_CKSUM_GOOD >> 1) << 56) + #ifdef RTE_LIBRTE_MEMPOOL_DEBUG static inline void nix_mbuf_validate_next(struct rte_mbuf *m) @@ -467,6 +479,11 @@ nix_sec_meta_to_mbuf_sc(uint64_t cq_w1, uint64_t cq_w5, const uint64_t sa_base, RTE_MBUF_F_RX_SEC_OFFLOAD : (RTE_MBUF_F_RX_SEC_OFFLOAD | RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED)); + + ucc = hdr->w3.uc_ccode; + inner->ol_flags |= ((ucc & 0xF0) == 0xF0) ? + ((NIX_RX_SEC_UCC_CONST >> ((ucc & 0xF) << 3)) + & 0xFF) << 1 : 0; } else if (!(hdr->w0.err_sum) && !(hdr->w0.reas_sts)) { /* Reassembly success */ inner = nix_sec_reassemble_frags(hdr, cq_w1, cq_w5, @@ -529,6 +546,11 @@ nix_sec_meta_to_mbuf_sc(uint64_t cq_w1, uint64_t cq_w5, const uint64_t sa_base, (RTE_MBUF_F_RX_SEC_OFFLOAD | RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED)); + ucc = hdr->w3.uc_ccode; + inner->ol_flags |= ((ucc & 0xF0) == 0xF0) ? + ((NIX_RX_SEC_UCC_CONST >> ((ucc & 0xF) << 3)) + & 0xFF) << 1 : 0; + /* Store meta in lmtline to free * Assume all meta's from same aura. */ @@ -1313,7 +1335,26 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, sa23 = vaddq_u64(sa23, vdupq_n_u64(sa_base)); const uint8x16_t tbl = { - 0, 0, 0, 0, 0, 0, 0, 0, + /* ROC_IE_OT_UCC_SUCCESS_SA_SOFTEXP_FIRST */ + 0, + /* ROC_IE_OT_UCC_SUCCESS_PKT_IP_BADCSUM */ + RTE_MBUF_F_RX_IP_CKSUM_BAD >> 1, + /* ROC_IE_OT_UCC_SUCCESS_SA_SOFTEXP_AGAIN */ + 0, + /* ROC_IE_OT_UCC_SUCCESS_PKT_L4_GOODCSUM */ + (RTE_MBUF_F_RX_IP_CKSUM_GOOD | + RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1, + /* ROC_IE_OT_UCC_SUCCESS_PKT_L4_BADCSUM */ + (RTE_MBUF_F_RX_IP_CKSUM_GOOD | + RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1, + /* ROC_IE_OT_UCC_SUCCESS_PKT_UDPESP_NZCSUM */ + (RTE_MBUF_F_RX_IP_CKSUM_GOOD | + RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1, + /* ROC_IE_OT_UCC_SUCCESS_PKT_UDP_ZEROCSUM */ + (RTE_MBUF_F_RX_IP_CKSUM_GOOD | + RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1, + /* ROC_IE_OT_UCC_SUCCESS_PKT_IP_GOODCSUM */ + RTE_MBUF_F_RX_IP_CKSUM_GOOD >> 1, /* HW_CCODE -> RTE_MBUF_F_RX_SEC_OFFLOAD_FAILED */ 1, 0, 1, 1, 1, 1, 0, 1, }; @@ -1419,6 +1460,8 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, nix_sec_meta_to_mbuf(cq0_w1, cq0_w5, sa, cpth0, mbuf0, &f0, &ol_flags0, flags, &rearm0); + ol_flags0 |= ((uint64_t)vget_lane_u8(ucc, 0)) + << 1; ol_flags0 |= (RTE_MBUF_F_RX_SEC_OFFLOAD | (uint64_t)vget_lane_u8(ucc, 1) << 19); } @@ -1441,6 +1484,8 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, nix_sec_meta_to_mbuf(cq1_w1, cq1_w5, sa, cpth1, mbuf1, &f1, &ol_flags1, flags, &rearm1); + ol_flags1 |= ((uint64_t)vget_lane_u8(ucc, 2)) + << 1; ol_flags1 |= (RTE_MBUF_F_RX_SEC_OFFLOAD | (uint64_t)vget_lane_u8(ucc, 3) << 19); } @@ -1463,6 +1508,8 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, nix_sec_meta_to_mbuf(cq2_w1, cq2_w5, sa, cpth2, mbuf2, &f2, &ol_flags2, flags, &rearm2); + ol_flags2 |= ((uint64_t)vget_lane_u8(ucc, 4)) + << 1; ol_flags2 |= (RTE_MBUF_F_RX_SEC_OFFLOAD | (uint64_t)vget_lane_u8(ucc, 5) << 19); } @@ -1485,6 +1532,8 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, nix_sec_meta_to_mbuf(cq3_w1, cq3_w5, sa, cpth3, mbuf3, &f3, &ol_flags3, flags, &rearm3); + ol_flags3 |= ((uint64_t)vget_lane_u8(ucc, 6)) + << 1; ol_flags3 |= (RTE_MBUF_F_RX_SEC_OFFLOAD | (uint64_t)vget_lane_u8(ucc, 7) << 19); } -- 2.8.4