From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 657A7A0093; Fri, 22 Apr 2022 12:47:44 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 721D8427FE; Fri, 22 Apr 2022 12:47:32 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id B8C75427EC for ; Fri, 22 Apr 2022 12:47:30 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id 23M0F66p003121; Fri, 22 Apr 2022 03:47:26 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=g3Bvaozfa7UvDjN4rCGUDtnYuAH+TzNKoiENZVElepE=; b=TqMZTrRvITasnX/5Rqdkj041hkxFmFCuJR1XeBi8OH0BBXsV7DYPVbGoi0OE/7fbSkdo H0941vGFt3BljgtVxqMjCYuxK7Z1Rf6J2GMbwmBJXD36+PUG6oGHkhuVYj/17TfLKdqu sSNGpopJul+0vOjW0RBchrlDGGfTsHNYrg1s2UDIzoGpoAANAyDVOoTcyLmopqyykrP8 q5dAqS6biIbiVilcoxsOl5zh7QNGOUI4GapD3rK4+mm6v7Lt7rUtmfpcK/dNAfGYBEY/ BjqW96rjc+a1HSK5/AwsXEBmjcMVAfgtKMI4UIIG+JJ2CjWmdOhjiQ8L0mGMlvSMmoCr Wg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3fk7mk449w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 22 Apr 2022 03:47:26 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 22 Apr 2022 03:47:25 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Fri, 22 Apr 2022 03:47:25 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id C7E5D3F7080; Fri, 22 Apr 2022 03:47:22 -0700 (PDT) From: Nithin Dabilpuram To: , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao , Ray Kinsella CC: , Vidya Sagar Velumuri Subject: [PATCH v2 04/28] common/cnxk: support to configure the ts pkind in CPT Date: Fri, 22 Apr 2022 16:16:45 +0530 Message-ID: <20220422104709.20722-4-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20220422104709.20722-1-ndabilpuram@marvell.com> References: <20220422104709.20722-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: vJTrH2vSbfasQTe_Co1GXt7bj14nz7ZB X-Proofpoint-GUID: vJTrH2vSbfasQTe_Co1GXt7bj14nz7ZB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-04-22_02,2022-04-22_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Vidya Sagar Velumuri Add new API to configure the SA table entries with new CPT PKIND when timestamp is enabled. Signed-off-by: Vidya Sagar Velumuri --- drivers/common/cnxk/roc_nix_inl.c | 59 ++++++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_nix_inl.h | 2 ++ drivers/common/cnxk/roc_nix_inl_priv.h | 1 + drivers/common/cnxk/version.map | 1 + 4 files changed, 63 insertions(+) diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index 826c6e9..bfb33b1 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -1011,6 +1011,65 @@ roc_nix_inl_ctx_write(struct roc_nix *roc_nix, void *sa_dptr, void *sa_cptr, return -ENOTSUP; } +int +roc_nix_inl_ts_pkind_set(struct roc_nix *roc_nix, bool ts_ena, bool inb_inl_dev) +{ + struct idev_cfg *idev = idev_get_cfg(); + struct nix_inl_dev *inl_dev = NULL; + void *sa, *sa_base = NULL; + struct nix *nix = NULL; + uint16_t max_spi = 0; + uint8_t pkind = 0; + int i; + + if (roc_model_is_cn9k()) + return 0; + + if (!inb_inl_dev && (roc_nix == NULL)) + return -EINVAL; + + if (inb_inl_dev) { + if ((idev == NULL) || (idev->nix_inl_dev == NULL)) + return 0; + inl_dev = idev->nix_inl_dev; + } else { + nix = roc_nix_to_nix_priv(roc_nix); + if (!nix->inl_inb_ena) + return 0; + sa_base = nix->inb_sa_base; + max_spi = roc_nix->ipsec_in_max_spi; + } + + if (inl_dev) { + if (inl_dev->rq_refs == 0) { + inl_dev->ts_ena = ts_ena; + max_spi = inl_dev->ipsec_in_max_spi; + sa_base = inl_dev->inb_sa_base; + } else if (inl_dev->ts_ena != ts_ena) { + if (inl_dev->ts_ena) + plt_err("Inline device is already configured with TS enable"); + else + plt_err("Inline device is already configured with TS disable"); + return -ENOTSUP; + } else { + return 0; + } + } + + pkind = ts_ena ? ROC_IE_OT_CPT_TS_PKIND : ROC_IE_OT_CPT_PKIND; + + sa = (uint8_t *)sa_base; + if (pkind == ((struct roc_ot_ipsec_inb_sa *)sa)->w0.s.pkind) + return 0; + + for (i = 0; i < max_spi; i++) { + sa = ((uint8_t *)sa_base) + + (i * ROC_NIX_INL_OT_IPSEC_INB_SA_SZ); + ((struct roc_ot_ipsec_inb_sa *)sa)->w0.s.pkind = pkind; + } + return 0; +} + void roc_nix_inl_dev_lock(void) { diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h index 2c2a4d7..633f090 100644 --- a/drivers/common/cnxk/roc_nix_inl.h +++ b/drivers/common/cnxk/roc_nix_inl.h @@ -174,6 +174,8 @@ int __roc_api roc_nix_inl_inb_tag_update(struct roc_nix *roc_nix, uint64_t __roc_api roc_nix_inl_dev_rq_limit_get(void); int __roc_api roc_nix_reassembly_configure(uint32_t max_wait_time, uint16_t max_frags); +int __roc_api roc_nix_inl_ts_pkind_set(struct roc_nix *roc_nix, bool ts_ena, + bool inb_inl_dev); /* NIX Inline Outbound API */ int __roc_api roc_nix_inl_outb_init(struct roc_nix *roc_nix); diff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h index 0fa5e09..f9646a3 100644 --- a/drivers/common/cnxk/roc_nix_inl_priv.h +++ b/drivers/common/cnxk/roc_nix_inl_priv.h @@ -76,6 +76,7 @@ struct nix_inl_dev { uint32_t inb_spi_mask; bool attach_cptlf; bool wqe_skip; + bool ts_ena; }; int nix_inl_sso_register_irqs(struct nix_inl_dev *inl_dev); diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 2a122e5..53586da 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -159,6 +159,7 @@ INTERNAL { roc_nix_inl_outb_is_enabled; roc_nix_inl_outb_soft_exp_poll_switch; roc_nix_inl_sa_sync; + roc_nix_inl_ts_pkind_set; roc_nix_inl_ctx_write; roc_nix_inl_dev_pffunc_get; roc_nix_cpt_ctx_cache_sync; -- 2.8.4