From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3EE2DA00BE; Mon, 25 Apr 2022 10:42:35 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CB72F41109; Mon, 25 Apr 2022 10:42:34 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id 59FEE410E6 for ; Mon, 25 Apr 2022 10:42:31 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1650876152; x=1682412152; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=Jnw0ZW765unhFHV5Pu30LZ3v3aFebepQnwzgCQ2QIHs=; b=WmHUhPJV7WoMkqUQk4MnbOCXgWxAXEgw1quArXxVgJzg6giCGP29FzPl 53rom5RiIocMn72CrMX79ldlXvtu8zdpQajhqyP7NDj5agZC+AKb+jC6E BqgNj0NaJ2UDvTvaow953Rox+CkU9Y6WbaizXm0OV6gmoVsKDRS6ZUsMF jKsdGcwNYKveD6v8T82KVAhTT6VWMxrqYbNBIzya2eBBgLXv0mpqCtccz DZGbGfsTu/QRypcyujcsuQgrA8UH677AiW2tuqVbTiakCH0v/N7XUgt9n KjhHslHeuZXZtfTtTHevCk+a6hH8niuyPWHoIU4s71i9gNkwedakPtUcS A==; X-IronPort-AV: E=McAfee;i="6400,9594,10327"; a="262783753" X-IronPort-AV: E=Sophos;i="5.90,287,1643702400"; d="scan'208";a="262783753" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2022 01:42:09 -0700 X-IronPort-AV: E=Sophos;i="5.90,287,1643702400"; d="scan'208";a="557619936" Received: from unknown (HELO localhost.localdomain) ([10.239.251.104]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2022 01:42:07 -0700 From: Ke Zhang To: xiaoyun.li@intel.com, jingjing.wu@intel.com, beilei.xing@intel.com, dev@dpdk.org Cc: Ke Zhang Subject: [PATCH] net/iavf: when E810 VF interrupt disable, only receive 4 packets once, fix 4 to 1. Date: Mon, 25 Apr 2022 08:36:28 +0000 Message-Id: <20220425083628.81133-1-ke1x.zhang@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org For Rx-Queue Interrupt Setting, when vf rx interrupt disable(INTENA=0), there are two ways to write back descriptor to host memory: 1)Set WB_ON_ITR bit 0 to Interrupt Dynamic Control Register: Completed descriptors are posted to host memory according to the internal descriptor cache policy (in other words when a full cache line is available for write-back). 2)Set WB_ON_ITR bit 1 to Interrupt Dynamic Control Register: Completed descriptors also trigger the ITR. Following ITR expiration, all leftover completed descriptors are posted to host memory. Changing 1) to 2) to make sure VF synchronizing with PF. Signed-off-by: Ke Zhang --- drivers/net/iavf/iavf_ethdev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c index d6190ac24a..17c7720600 100644 --- a/drivers/net/iavf/iavf_ethdev.c +++ b/drivers/net/iavf/iavf_ethdev.c @@ -1833,7 +1833,7 @@ iavf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) IAVF_WRITE_REG(hw, IAVF_VFINT_DYN_CTLN1(msix_intr - IAVF_RX_VEC_START), - 0); + IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK); IAVF_WRITE_FLUSH(hw); return 0; -- 2.25.1