From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3322AA0093; Thu, 5 May 2022 16:28:06 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D6B434014F; Thu, 5 May 2022 16:28:05 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 3E91A40042 for ; Thu, 5 May 2022 16:28:04 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.16.1.2) with ESMTP id 2457XG2a012012; Thu, 5 May 2022 07:28:00 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Mte16kYHxD5ZuX1lkh/m8O3pcwD8iZV1comMWchyxJo=; b=PHt02pU6ASEEviEVoxmATWEzGTEeFMpKSNznFq9tkK8YTfWgxcMn+qAfP5g8QQAkh00q QUF3/8yVw2ToLdnUWiI9iWa8pQZWetsm3nNdHft6PI4n7Vskk+ZOZGtSp8rTcuvpv7yj lK+Ss/40k3cayCVm96GxPViL6Cr4VczC49+qCpt59E1dkUNMJ32OYVCQhFogdf1C6tq0 F/Z8eNSAkIBDKH5z9hJf2m8CRc8M31OoqlW+is5Ny3/wbeC2j57EBIDWVn+kTmPRUINo gyt7dSqcxrH6hkq5Dg5t/H6Etp7Z8h2Tv0vfsJelhrSQU5OCjkmnYPD3E9dTy57VARxA Uw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3fuscx5cn9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 05 May 2022 07:28:00 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 5 May 2022 07:27:58 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 5 May 2022 07:27:58 -0700 Received: from localhost.localdomain (unknown [10.28.48.107]) by maili.marvell.com (Postfix) with ESMTP id A08F23F706C; Thu, 5 May 2022 07:27:56 -0700 (PDT) From: Rahul Bhansali To: , Ruifeng Wang , Jan Viktorin , Bruce Richardson CC: , Rahul Bhansali Subject: [PATCH 1/2] config/arm: add SVE control flag Date: Thu, 5 May 2022 19:57:43 +0530 Message-ID: <20220505142744.1423344-1-rbhansali@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: -ILNqa4nuy5lJhzt5eF73hSQCB6G_lPH X-Proofpoint-ORIG-GUID: -ILNqa4nuy5lJhzt5eF73hSQCB6G_lPH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-05_06,2022-05-05_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This add the control flag for SVE to enable or disable RTE_HAS_SVE_ACLE macro in the build. Signed-off-by: Rahul Bhansali --- config/arm/meson.build | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 8aead74086..dafb342cc6 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -603,7 +603,8 @@ if (cc.get_define('__ARM_NEON', args: machine_args) != '' or compile_time_cpuflags += ['RTE_CPUFLAG_NEON'] endif -if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' +if (cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' and + soc_config.get('sve', true)) compile_time_cpuflags += ['RTE_CPUFLAG_SVE'] if (cc.check_header('arm_sve.h')) dpdk_conf.set('RTE_HAS_SVE_ACLE', 1) -- 2.25.1