[PATCH 00/11] Introduce support for RISC-V architecture

[PATCH 00/11] Introduce support for RISC-V architecture

[Stanislaw Kardach]

This patchset adds support for building and running DPDK on 64bit RISC-V
architecture. The initial support targets rv64gc (rv64imafdc) ISA and
was tested on SiFive Unmatched development board with the Freedom U740
SoC running Linux (freedom-u-sdk based kernel).
I have tested this codebase using DPDK unit and perf tests as well as
test-pmd, l2fwd and l3fwd examples.
The NIC attached to the DUT was Intel X520-DA2 which uses ixgbe PMD.
On the UIO side, since U740 does not have an IOMMU, I've used igb_uio,
uio_pci_generic and vfio-pci noiommu drivers.

Commits 1-2 fix small issues which are encountered if a given platform
   does not support any vector operations (which is the case with U740).
Commit 3 introduces EAL and build system support for RISC-V architecture
   as well as documentation updates.
Commits 4-7 add missing defines and stubs to enable RISC-V operation in
   non-EAL parts.
Commit 8 adds RISC-V specific cpuflags test.
Commit 9 works around a bug in the current GCC in test_ring compiled
   with -O0 or -Og.
Commit 10 adds RISC-V testing to test-meson-builds.sh automatically
   iterating over cross-compile config files (currently present for
   generic rv64gc and SiFive U740).
Commit 11 extends hash r/w perf test by displaying both HTM and non-HTM
   measurements. This is an extraneous commit which is not directly
   needed for RISC-V support but was noticed when we have started
   gathering test results. If needed, I can submit it separately.

I appreciate Your comments and feedback.

Best Regards,
Stanislaw Kardach

NOTE: This work was sponsored by StarFive and SiFive which is signified by
   "Sponsored-by:" sign-offs in each commit message. After discussing it
   with Thomas Monjalon it seemed a better choice than "Suggested-by" which
   does not fully convey the nature of involvement. However it makes
   Linux checkpatch unhappy so I'm not sure if I shouldn't change the
   sign-offs.

NOTE2: I have added maintainers for each commit based on MAINTAINERS file.
   However some modules (l3fwd, net/tap and cpuflags unit tests) do not have
   any maintainers assigned, hence I've targeted dev@dpdk.org mailing list as
   if it was a commit adding new files.

Michal Mazurek (3):
  lpm: add a scalar version of lookupx4 function
  eal: add initial support for RISC-V architecture
  test/cpuflags: add test for RISC-V cpu flag

Stanislaw Kardach (8):
  examples/l3fwd: fix scalar LPM compilation
  net/ixgbe: enable vector stubs for RISC-V
  net/memif: set memfd syscall ID on RISC-V
  net/tap: set BPF syscall ID for RISC-V
  examples/l3fwd: enable RISC-V operation
  test/ring: disable problematic tests for RISC-V
  devtools: add RISC-V to test-meson-builds.sh
  test/hash: report non HTM numbers for single r/w

 MAINTAINERS                                   |   6 +
 app/test/test_cpuflags.c                      |  81 ++++++++++
 app/test/test_hash_readwrite.c                |   8 +-
 app/test/test_ring.c                          |   8 +
 app/test/test_xmmt_ops.h                      |  16 ++
 config/meson.build                            |   2 +
 config/riscv/meson.build                      | 148 ++++++++++++++++++
 config/riscv/riscv64_linux_gcc                |  17 ++
 config/riscv/riscv64_sifive_u740_linux_gcc    |  19 +++
 devtools/test-meson-builds.sh                 |   6 +
 doc/guides/contributing/design.rst            |   2 +-
 .../linux_gsg/cross_build_dpdk_for_riscv.rst  | 125 +++++++++++++++
 doc/guides/linux_gsg/index.rst                |   1 +
 doc/guides/nics/features.rst                  |   5 +
 doc/guides/nics/features/default.ini          |   1 +
 doc/guides/nics/features/ixgbe.ini            |   1 +
 doc/guides/rel_notes/release_22_07.rst        |  29 ++++
 drivers/net/i40e/meson.build                  |   6 +
 drivers/net/ixgbe/ixgbe_rxtx.c                |   4 +-
 drivers/net/memif/rte_eth_memif.h             |   2 +
 drivers/net/tap/tap_bpf.h                     |   2 +
 examples/l3fwd/l3fwd_em.c                     |   8 +
 examples/l3fwd/l3fwd_fib.c                    |   2 +
 examples/l3fwd/l3fwd_lpm.c                    |   2 +-
 lib/eal/riscv/include/meson.build             |  23 +++
 lib/eal/riscv/include/rte_atomic.h            |  52 ++++++
 lib/eal/riscv/include/rte_byteorder.h         |  44 ++++++
 lib/eal/riscv/include/rte_cpuflags.h          |  55 +++++++
 lib/eal/riscv/include/rte_cycles.h            | 103 ++++++++++++
 lib/eal/riscv/include/rte_io.h                |  21 +++
 lib/eal/riscv/include/rte_mcslock.h           |  18 +++
 lib/eal/riscv/include/rte_memcpy.h            |  63 ++++++++
 lib/eal/riscv/include/rte_pause.h             |  31 ++++
 lib/eal/riscv/include/rte_pflock.h            |  17 ++
 lib/eal/riscv/include/rte_power_intrinsics.h  |  22 +++
 lib/eal/riscv/include/rte_prefetch.h          |  50 ++++++
 lib/eal/riscv/include/rte_rwlock.h            |  44 ++++++
 lib/eal/riscv/include/rte_spinlock.h          |  67 ++++++++
 lib/eal/riscv/include/rte_ticketlock.h        |  21 +++
 lib/eal/riscv/include/rte_vect.h              |  55 +++++++
 lib/eal/riscv/meson.build                     |  11 ++
 lib/eal/riscv/rte_cpuflags.c                  | 122 +++++++++++++++
 lib/eal/riscv/rte_cycles.c                    |  77 +++++++++
 lib/eal/riscv/rte_hypervisor.c                |  13 ++
 lib/eal/riscv/rte_power_intrinsics.c          |  56 +++++++
 lib/lpm/meson.build                           |   1 +
 lib/lpm/rte_lpm.h                             |   4 +-
 lib/lpm/rte_lpm_scalar.h                      | 122 +++++++++++++++
 meson.build                                   |   2 +
 49 files changed, 1588 insertions(+), 7 deletions(-)
 create mode 100644 config/riscv/meson.build
 create mode 100644 config/riscv/riscv64_linux_gcc
 create mode 100644 config/riscv/riscv64_sifive_u740_linux_gcc
 create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
 create mode 100644 lib/eal/riscv/include/meson.build
 create mode 100644 lib/eal/riscv/include/rte_atomic.h
 create mode 100644 lib/eal/riscv/include/rte_byteorder.h
 create mode 100644 lib/eal/riscv/include/rte_cpuflags.h
 create mode 100644 lib/eal/riscv/include/rte_cycles.h
 create mode 100644 lib/eal/riscv/include/rte_io.h
 create mode 100644 lib/eal/riscv/include/rte_mcslock.h
 create mode 100644 lib/eal/riscv/include/rte_memcpy.h
 create mode 100644 lib/eal/riscv/include/rte_pause.h
 create mode 100644 lib/eal/riscv/include/rte_pflock.h
 create mode 100644 lib/eal/riscv/include/rte_power_intrinsics.h
 create mode 100644 lib/eal/riscv/include/rte_prefetch.h
 create mode 100644 lib/eal/riscv/include/rte_rwlock.h
 create mode 100644 lib/eal/riscv/include/rte_spinlock.h
 create mode 100644 lib/eal/riscv/include/rte_ticketlock.h
 create mode 100644 lib/eal/riscv/include/rte_vect.h
 create mode 100644 lib/eal/riscv/meson.build
 create mode 100644 lib/eal/riscv/rte_cpuflags.c
 create mode 100644 lib/eal/riscv/rte_cycles.c
 create mode 100644 lib/eal/riscv/rte_hypervisor.c
 create mode 100644 lib/eal/riscv/rte_power_intrinsics.c
 create mode 100644 lib/lpm/rte_lpm_scalar.h

-- 
2.30.2

[PATCH 01/11] lpm: add a scalar version of lookupx4 function

[Stanislaw Kardach]

From: Michal Mazurek <maz@semihalf.com>

Add an implementation of the rte_lpm_lookupx4() function for platforms
without support for vector operations.

Signed-off-by: Michal Mazurek <maz@semihalf.com>
Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
---
 doc/guides/rel_notes/release_22_07.rst |   5 +
 lib/lpm/meson.build                    |   1 +
 lib/lpm/rte_lpm.h                      |   4 +-
 lib/lpm/rte_lpm_scalar.h               | 122 +++++++++++++++++++++++++
 4 files changed, 131 insertions(+), 1 deletion(-)
 create mode 100644 lib/lpm/rte_lpm_scalar.h

diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst
index 88d6e96cc1..067118174b 100644
--- a/doc/guides/rel_notes/release_22_07.rst
+++ b/doc/guides/rel_notes/release_22_07.rst
@@ -65,6 +65,11 @@ New Features
   * Added support for promiscuous mode on Windows.
   * Added support for MTU on Windows.
 
+* **Added scalar version of the LPM library.**
+
+  * Added scalar implementation of ``rte_lpm_lookupx4``. This is a fall-back
+    implementation for platforms that don't support vector operations.
+
 
 Removed Items
 -------------
diff --git a/lib/lpm/meson.build b/lib/lpm/meson.build
index 78d91d3421..6b47361fce 100644
--- a/lib/lpm/meson.build
+++ b/lib/lpm/meson.build
@@ -14,6 +14,7 @@ headers = files('rte_lpm.h', 'rte_lpm6.h')
 indirect_headers += files(
         'rte_lpm_altivec.h',
         'rte_lpm_neon.h',
+        'rte_lpm_scalar.h',
         'rte_lpm_sse.h',
         'rte_lpm_sve.h',
 )
diff --git a/lib/lpm/rte_lpm.h b/lib/lpm/rte_lpm.h
index eb91960e81..b5db6a353a 100644
--- a/lib/lpm/rte_lpm.h
+++ b/lib/lpm/rte_lpm.h
@@ -405,8 +405,10 @@ rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4],
 #endif
 #elif defined(RTE_ARCH_PPC_64)
 #include "rte_lpm_altivec.h"
-#else
+#elif defined(RTE_ARCH_X86)
 #include "rte_lpm_sse.h"
+#else
+#include "rte_lpm_scalar.h"
 #endif
 
 #ifdef __cplusplus
diff --git a/lib/lpm/rte_lpm_scalar.h b/lib/lpm/rte_lpm_scalar.h
new file mode 100644
index 0000000000..991b94e687
--- /dev/null
+++ b/lib/lpm/rte_lpm_scalar.h
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef _RTE_LPM_SCALAR_H_
+#define _RTE_LPM_SCALAR_H_
+
+#include <rte_branch_prediction.h>
+#include <rte_byteorder.h>
+#include <rte_common.h>
+#include <rte_vect.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline void
+rte_lpm_lookupx4(const struct rte_lpm *lpm, xmm_t ip, uint32_t hop[4],
+		uint32_t defv)
+{
+	rte_xmm_t i24;
+	rte_xmm_t i8;
+	uint32_t tbl[4];
+	uint64_t pt, pt2;
+	const uint32_t *ptbl;
+
+	const rte_xmm_t mask8 = {
+		.u32 = {UINT8_MAX, UINT8_MAX, UINT8_MAX, UINT8_MAX}};
+
+	/*
+	 * RTE_LPM_VALID_EXT_ENTRY_BITMASK for 2 LPM entries
+	 * as one 64-bit value (0x0300000003000000).
+	 */
+	const uint64_t mask_xv =
+		((uint64_t)RTE_LPM_VALID_EXT_ENTRY_BITMASK |
+		(uint64_t)RTE_LPM_VALID_EXT_ENTRY_BITMASK << 32);
+
+	/*
+	 * RTE_LPM_LOOKUP_SUCCESS for 2 LPM entries
+	 * as one 64-bit value (0x0100000001000000).
+	 */
+	const uint64_t mask_v =
+		((uint64_t)RTE_LPM_LOOKUP_SUCCESS |
+		(uint64_t)RTE_LPM_LOOKUP_SUCCESS << 32);
+
+	/* get 4 indexes for tbl24[]. */
+	i24.x = ip;
+	i24.u32[0] >>= CHAR_BIT;
+	i24.u32[1] >>= CHAR_BIT;
+	i24.u32[2] >>= CHAR_BIT;
+	i24.u32[3] >>= CHAR_BIT;
+
+	/* extract values from tbl24[] */
+	ptbl = (const uint32_t *)&lpm->tbl24[i24.u32[0]];
+	tbl[0] = *ptbl;
+	ptbl = (const uint32_t *)&lpm->tbl24[i24.u32[1]];
+	tbl[1] = *ptbl;
+	ptbl = (const uint32_t *)&lpm->tbl24[i24.u32[2]];
+	tbl[2] = *ptbl;
+	ptbl = (const uint32_t *)&lpm->tbl24[i24.u32[3]];
+	tbl[3] = *ptbl;
+
+	/* get 4 indexes for tbl8[]. */
+	i8.x = ip;
+	i8.u64[0] &= mask8.u64[0];
+	i8.u64[1] &= mask8.u64[1];
+
+	pt = (uint64_t)tbl[0] |
+		(uint64_t)tbl[1] << 32;
+	pt2 = (uint64_t)tbl[2] |
+		(uint64_t)tbl[3] << 32;
+
+	/* search successfully finished for all 4 IP addresses. */
+	if (likely((pt & mask_xv) == mask_v) &&
+			likely((pt2 & mask_xv) == mask_v)) {
+		*(uint64_t *)hop = pt & RTE_LPM_MASKX4_RES;
+		*(uint64_t *)(hop + 2) = pt2 & RTE_LPM_MASKX4_RES;
+		return;
+	}
+
+	if (unlikely((pt & RTE_LPM_VALID_EXT_ENTRY_BITMASK) ==
+			RTE_LPM_VALID_EXT_ENTRY_BITMASK)) {
+		i8.u32[0] = i8.u32[0] +
+			(tbl[0] & 0x00FFFFFF) * RTE_LPM_TBL8_GROUP_NUM_ENTRIES;
+		ptbl = (const uint32_t *)&lpm->tbl8[i8.u32[0]];
+		tbl[0] = *ptbl;
+	}
+	if (unlikely((pt >> 32 & RTE_LPM_VALID_EXT_ENTRY_BITMASK) ==
+			RTE_LPM_VALID_EXT_ENTRY_BITMASK)) {
+		i8.u32[1] = i8.u32[1] +
+			(tbl[1] & 0x00FFFFFF) * RTE_LPM_TBL8_GROUP_NUM_ENTRIES;
+		ptbl = (const uint32_t *)&lpm->tbl8[i8.u32[1]];
+		tbl[1] = *ptbl;
+	}
+	if (unlikely((pt2 & RTE_LPM_VALID_EXT_ENTRY_BITMASK) ==
+			RTE_LPM_VALID_EXT_ENTRY_BITMASK)) {
+		i8.u32[2] = i8.u32[2] +
+			(tbl[2] & 0x00FFFFFF) * RTE_LPM_TBL8_GROUP_NUM_ENTRIES;
+		ptbl = (const uint32_t *)&lpm->tbl8[i8.u32[2]];
+		tbl[2] = *ptbl;
+	}
+	if (unlikely((pt2 >> 32 & RTE_LPM_VALID_EXT_ENTRY_BITMASK) ==
+			RTE_LPM_VALID_EXT_ENTRY_BITMASK)) {
+		i8.u32[3] = i8.u32[3] +
+			(tbl[3] & 0x00FFFFFF) * RTE_LPM_TBL8_GROUP_NUM_ENTRIES;
+		ptbl = (const uint32_t *)&lpm->tbl8[i8.u32[3]];
+		tbl[3] = *ptbl;
+	}
+
+	hop[0] = (tbl[0] & RTE_LPM_LOOKUP_SUCCESS) ? tbl[0] & 0x00FFFFFF : defv;
+	hop[1] = (tbl[1] & RTE_LPM_LOOKUP_SUCCESS) ? tbl[1] & 0x00FFFFFF : defv;
+	hop[2] = (tbl[2] & RTE_LPM_LOOKUP_SUCCESS) ? tbl[2] & 0x00FFFFFF : defv;
+	hop[3] = (tbl[3] & RTE_LPM_LOOKUP_SUCCESS) ? tbl[3] & 0x00FFFFFF : defv;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_LPM_SCALAR_H_ */
-- 
2.30.2

[PATCH 02/11] examples/l3fwd: fix scalar LPM compilation

[Stanislaw Kardach]

The lpm_process_event_pkt() can either process a packet using an
architecture specific (defined for X86/SSE, ARM/Neon and PPC64/Altivec)
path or a scalar one. The choice is however done using an ifdef
pre-processor macro. Because of that the scalar version was apparently
not widely excersized/compiled.
Due to some copy/paste errors, the scalar logic in
lpm_process_event_pkt() retained a "continue" statement where a BAD_PORT
should be returned after refactoring of the LPM logic in the l3fwd
example.

Fixes: 99fc91d18082 ("examples/l3fwd: add event lpm main loop")
Cc: pbhagavatula@marvell.com

Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
---
 examples/l3fwd/l3fwd_lpm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/l3fwd/l3fwd_lpm.c b/examples/l3fwd/l3fwd_lpm.c
index bec22c44cd..6e1defbf7f 100644
--- a/examples/l3fwd/l3fwd_lpm.c
+++ b/examples/l3fwd/l3fwd_lpm.c
@@ -248,7 +248,7 @@ lpm_process_event_pkt(const struct lcore_conf *lconf, struct rte_mbuf *mbuf)
 		if (is_valid_ipv4_pkt(ipv4_hdr, mbuf->pkt_len)
 				< 0) {
 			mbuf->port = BAD_PORT;
-			continue;
+			return mbuf->port;
 		}
 		/* Update time to live and header checksum */
 		--(ipv4_hdr->time_to_live);
-- 
2.30.2

Re: [PATCH 02/11] examples/l3fwd: fix scalar LPM compilation

[Stephen Hemminger]

On Thu,  5 May 2022 19:29:54 +0200
Stanislaw Kardach <kda@semihalf.com> wrote:

> The lpm_process_event_pkt() can either process a packet using an
> architecture specific (defined for X86/SSE, ARM/Neon and PPC64/Altivec)
> path or a scalar one. The choice is however done using an ifdef
> pre-processor macro. Because of that the scalar version was apparently
> not widely excersized/compiled.
> Due to some copy/paste errors, the scalar logic in
> lpm_process_event_pkt() retained a "continue" statement where a BAD_PORT
> should be returned after refactoring of the LPM logic in the l3fwd
> example.
> 
> Fixes: 99fc91d18082 ("examples/l3fwd: add event lpm main loop")
> Cc: pbhagavatula@marvell.com
> 
> Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
> Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
> Sponsored-by: Sam Grove <sam.grove@sifive.com>

Would be easier to get merged if bug fixes came as separate patch
submission.

Also have not seen Sponsored-by before; what do you expect it to mean?
Never used in DPDK or kernel git tree.

Re: [PATCH 02/11] examples/l3fwd: fix scalar LPM compilation

[Stanisław Kardach]

[-- Attachment #1: Type: text/plain, Size: 1832 bytes --]

On Thu, May 5, 2022 at 7:39 PM Stephen Hemminger <stephen@networkplumber.org>
wrote:

> On Thu,  5 May 2022 19:29:54 +0200
> Stanislaw Kardach <kda@semihalf.com> wrote:
>
> > The lpm_process_event_pkt() can either process a packet using an
> > architecture specific (defined for X86/SSE, ARM/Neon and PPC64/Altivec)
> > path or a scalar one. The choice is however done using an ifdef
> > pre-processor macro. Because of that the scalar version was apparently
> > not widely excersized/compiled.
> > Due to some copy/paste errors, the scalar logic in
> > lpm_process_event_pkt() retained a "continue" statement where a BAD_PORT
> > should be returned after refactoring of the LPM logic in the l3fwd
> > example.
> >
> > Fixes: 99fc91d18082 ("examples/l3fwd: add event lpm main loop")
> > Cc: pbhagavatula@marvell.com
> >
> > Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
> > Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
> > Sponsored-by: Sam Grove <sam.grove@sifive.com>
>
> Would be easier to get merged if bug fixes came as separate patch
> submission.
>
Sure, I can post this separately. The reason for posting this along with
RISC-V patches is that those depend on this one. So I could add
"depends-on" but wanted be on the safe side.

>
> Also have not seen Sponsored-by before; what do you expect it to mean?
> Never used in DPDK or kernel git tree.
>
The idea is that this work was sponsored by the companies mentioned in the
sign-off. It is used i.e. in FreeBSD though admittedly never in Linux or
DPDK.
Alternative, which makes checkpatch happy and was previously used is
"Suggested-by". However suggestion, doesn't necessary mean sponsorship.
I had a talk about this with Thomas Monjalon and he has also leaned towards
"Sponsored-by".
I'm open to suggestions as I admit, I'm not sure which route is better.

[-- Attachment #2: Type: text/html, Size: 2782 bytes --]

Re: [PATCH 02/11] examples/l3fwd: fix scalar LPM compilation

[Stephen Hemminger]

On Thu, 5 May 2022 19:49:28 +0200
Stanisław Kardach <kda@semihalf.com> wrote:

> On Thu, May 5, 2022 at 7:39 PM Stephen Hemminger <stephen@networkplumber.org>
> wrote:
> 
> > On Thu,  5 May 2022 19:29:54 +0200
> > Stanislaw Kardach <kda@semihalf.com> wrote:
> >  
> > > The lpm_process_event_pkt() can either process a packet using an
> > > architecture specific (defined for X86/SSE, ARM/Neon and PPC64/Altivec)
> > > path or a scalar one. The choice is however done using an ifdef
> > > pre-processor macro. Because of that the scalar version was apparently
> > > not widely excersized/compiled.
> > > Due to some copy/paste errors, the scalar logic in
> > > lpm_process_event_pkt() retained a "continue" statement where a BAD_PORT
> > > should be returned after refactoring of the LPM logic in the l3fwd
> > > example.
> > >
> > > Fixes: 99fc91d18082 ("examples/l3fwd: add event lpm main loop")
> > > Cc: pbhagavatula@marvell.com
> > >
> > > Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
> > > Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
> > > Sponsored-by: Sam Grove <sam.grove@sifive.com>  
> >
> > Would be easier to get merged if bug fixes came as separate patch
> > submission.
> >  
> Sure, I can post this separately. The reason for posting this along with
> RISC-V patches is that those depend on this one. So I could add
> "depends-on" but wanted be on the safe side.
> 
> >
> > Also have not seen Sponsored-by before; what do you expect it to mean?
> > Never used in DPDK or kernel git tree.
> >  
> The idea is that this work was sponsored by the companies mentioned in the
> sign-off. It is used i.e. in FreeBSD though admittedly never in Linux or
> DPDK.
> Alternative, which makes checkpatch happy and was previously used is
> "Suggested-by". However suggestion, doesn't necessary mean sponsorship.
> I had a talk about this with Thomas Monjalon and he has also leaned towards
> "Sponsored-by".
> I'm open to suggestions as I admit, I'm not sure which route is better.

So it is just advertising.

I did notice slightly different syntax in the kernel.
Could we follow that precedent?

Example:


commit 0301bcd599e552c38adf6771c25ff99680b9c4ee
Author: Bjoern A. Zeeb <bz@FreeBSD.ORG>
Date:   Fri Jan 28 15:34:26 2022 +0200

    iwlwifi: de-const properly where needed
    
    In order to de-const variables simply casting through (void *) is
    not enough: "cast from 'const .. *' to 'void *' drops const qualifier".
    Cast through (uintptr_t) as well [1] to make this compile on systems
    with more strict requirements.
    In addition passing const void *data to dma_map_single() also
    drops the (const) qualifier.  De-constify on variable on assignment
    which may be overwritten later.  In either case the (void *) cast
    to dma_map_single() is not needed (anymore) either.
    
    [1] See __DECONST() in sys/sys/cdefs.h in FreeBSD
    
    Sponsored by:  The FreeBSD Foundation
    Signed-off-by: Bjoern A. Zeeb <bz@FreeBSD.ORG>
    Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
    Link: https://lore.kernel.org/r/iwlwifi.20220128153014.eb696eb56bf6.Ide1dd041f9b908c5154a600286a7453750b0704a@changeid
    Signed-off-by: Luca Coelho <luciano.coelho@intel.com>

[PATCH 03/11] eal: add initial support for RISC-V architecture

[Stanislaw Kardach]

From: Michal Mazurek <maz@semihalf.com>

Add all necessary elements for DPDK to compile and run EAL on SiFive
Freedom U740 SoC which is based on SiFive U74-MC (ISA: rv64imafdc)
core complex.

This includes:

- EAL library implementation for rv64imafdc ISA.
- meson build structure for 'riscv' architecture. RTE_ARCH_RISCV define
  is added for architecture identification.
- xmm_t structure operation stubs as there is no vector support in the
  U74 core.

Compilation was tested on Ubuntu and Arch Linux using riscv64 toolchain.

Two rte_rdtsc() schemes are provided: stable low-resolution using rdtime
(default) and unstable high-resolution using rdcycle. User can override
the scheme by defining RTE_RISCV_RDTSC_USE_HPM=1 during compile time of
both DPDK and the application. The reasoning for this is as follows.
The RISC-V ISA mandates that clock read by rdtime has to be of constant
period and synchronized between all hardware threads within 1 tick
(chapter 10.1 in version 20191213 of RISC-V spec).
However this clock may not be of high-enough frequency for dataplane
uses. I.e. on HiFive Unmatched (FU740) it is 1MHz.
There is a high-resolution alternative in form of rdcycle which is
clocked at the core clock frequency. The drawbacks are that it may be
disabled during sleep (WFI) and its frequency might change due to DVFS.

The platform is currently marked as linux-only because rte_cycles
implementation uses the timebase-frequency device-tree node read through
the proc file system. Such approach was chosen because Linux kernel
depends on the presence of this device-tree node.

The compilation of following modules has been disabled by this commit
and will be re-enabled in later commits as fixes are introduced:
net/ixgbe, net/memif, net/tap, example/l3fwd.

Known checkpatch errors/warnings:

- ERROR:COMPLEX_MACRO in rte_atomic.h and rte_cycles.h due to inline
  assembly declarations.
- vector_size compiler attribute used in rte_vect.h directly.
- rte_*mb() used directly in rte_atomic.h to reduce code duplication.
- __atomic_thread_fence() used to implement rte_atomic_thread_fence().

Signed-off-by: Michal Mazurek <maz@semihalf.com>
Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
---
 MAINTAINERS                                   |   6 +
 app/test/test_xmmt_ops.h                      |  16 ++
 config/meson.build                            |   2 +
 config/riscv/meson.build                      | 143 ++++++++++++++++++
 config/riscv/riscv64_linux_gcc                |  17 +++
 config/riscv/riscv64_sifive_u740_linux_gcc    |  19 +++
 doc/guides/contributing/design.rst            |   2 +-
 .../linux_gsg/cross_build_dpdk_for_riscv.rst  | 125 +++++++++++++++
 doc/guides/linux_gsg/index.rst                |   1 +
 doc/guides/nics/features.rst                  |   5 +
 doc/guides/nics/features/default.ini          |   1 +
 doc/guides/rel_notes/release_22_07.rst        |  23 +++
 drivers/net/i40e/meson.build                  |   6 +
 drivers/net/ixgbe/meson.build                 |   6 +
 drivers/net/memif/meson.build                 |   5 +
 drivers/net/tap/meson.build                   |   5 +
 examples/l3fwd/meson.build                    |   6 +
 lib/eal/riscv/include/meson.build             |  23 +++
 lib/eal/riscv/include/rte_atomic.h            |  52 +++++++
 lib/eal/riscv/include/rte_byteorder.h         |  44 ++++++
 lib/eal/riscv/include/rte_cpuflags.h          |  55 +++++++
 lib/eal/riscv/include/rte_cycles.h            | 103 +++++++++++++
 lib/eal/riscv/include/rte_io.h                |  21 +++
 lib/eal/riscv/include/rte_mcslock.h           |  18 +++
 lib/eal/riscv/include/rte_memcpy.h            |  63 ++++++++
 lib/eal/riscv/include/rte_pause.h             |  31 ++++
 lib/eal/riscv/include/rte_pflock.h            |  17 +++
 lib/eal/riscv/include/rte_power_intrinsics.h  |  22 +++
 lib/eal/riscv/include/rte_prefetch.h          |  50 ++++++
 lib/eal/riscv/include/rte_rwlock.h            |  44 ++++++
 lib/eal/riscv/include/rte_spinlock.h          |  67 ++++++++
 lib/eal/riscv/include/rte_ticketlock.h        |  21 +++
 lib/eal/riscv/include/rte_vect.h              |  55 +++++++
 lib/eal/riscv/meson.build                     |  11 ++
 lib/eal/riscv/rte_cpuflags.c                  | 122 +++++++++++++++
 lib/eal/riscv/rte_cycles.c                    |  77 ++++++++++
 lib/eal/riscv/rte_hypervisor.c                |  13 ++
 lib/eal/riscv/rte_power_intrinsics.c          |  56 +++++++
 meson.build                                   |   2 +
 39 files changed, 1354 insertions(+), 1 deletion(-)
 create mode 100644 config/riscv/meson.build
 create mode 100644 config/riscv/riscv64_linux_gcc
 create mode 100644 config/riscv/riscv64_sifive_u740_linux_gcc
 create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
 create mode 100644 lib/eal/riscv/include/meson.build
 create mode 100644 lib/eal/riscv/include/rte_atomic.h
 create mode 100644 lib/eal/riscv/include/rte_byteorder.h
 create mode 100644 lib/eal/riscv/include/rte_cpuflags.h
 create mode 100644 lib/eal/riscv/include/rte_cycles.h
 create mode 100644 lib/eal/riscv/include/rte_io.h
 create mode 100644 lib/eal/riscv/include/rte_mcslock.h
 create mode 100644 lib/eal/riscv/include/rte_memcpy.h
 create mode 100644 lib/eal/riscv/include/rte_pause.h
 create mode 100644 lib/eal/riscv/include/rte_pflock.h
 create mode 100644 lib/eal/riscv/include/rte_power_intrinsics.h
 create mode 100644 lib/eal/riscv/include/rte_prefetch.h
 create mode 100644 lib/eal/riscv/include/rte_rwlock.h
 create mode 100644 lib/eal/riscv/include/rte_spinlock.h
 create mode 100644 lib/eal/riscv/include/rte_ticketlock.h
 create mode 100644 lib/eal/riscv/include/rte_vect.h
 create mode 100644 lib/eal/riscv/meson.build
 create mode 100644 lib/eal/riscv/rte_cpuflags.c
 create mode 100644 lib/eal/riscv/rte_cycles.c
 create mode 100644 lib/eal/riscv/rte_hypervisor.c
 create mode 100644 lib/eal/riscv/rte_power_intrinsics.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 7c4f541dba..2c732a1912 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -296,6 +296,12 @@ F: drivers/*/*/*_altivec.*
 F: app/*/*_altivec.*
 F: examples/*/*_altivec.*
 
+RISC-V
+M: Stanislaw Kardach <kda@semihalf.com>
+F: config/riscv/
+F: doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
+F: lib/eal/riscv/
+
 Intel x86
 M: Bruce Richardson <bruce.richardson@intel.com>
 M: Konstantin Ananyev <konstantin.ananyev@intel.com>
diff --git a/app/test/test_xmmt_ops.h b/app/test/test_xmmt_ops.h
index 3a82d5ecac..55f256599e 100644
--- a/app/test/test_xmmt_ops.h
+++ b/app/test/test_xmmt_ops.h
@@ -1,5 +1,8 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  * Copyright(c) 2015 Cavium, Inc
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
  */
 
 #ifndef _TEST_XMMT_OPS_H_
@@ -49,6 +52,19 @@ vect_set_epi32(int i3, int i2, int i1, int i0)
 	return data;
 }
 
+#elif defined(RTE_ARCH_RISCV)
+
+#define vect_loadu_sil128(p) vect_load_128(p)
+
+/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */
+static __rte_always_inline xmm_t
+vect_set_epi32(int i3, int i2, int i1, int i0)
+{
+	xmm_t data = (xmm_t){i0, i1, i2, i3};
+
+	return data;
+}
+
 #endif
 
 #endif /* _TEST_XMMT_OPS_H_ */
diff --git a/config/meson.build b/config/meson.build
index 7134e80e8d..7f7b6c92fd 100644
--- a/config/meson.build
+++ b/config/meson.build
@@ -121,6 +121,8 @@ if cpu_instruction_set == 'generic'
         cpu_instruction_set = 'generic'
     elif host_machine.cpu_family().startswith('ppc')
         cpu_instruction_set = 'power8'
+    elif host_machine.cpu_family().startswith('riscv')
+        cpu_instruction_set = 'riscv'
     endif
 endif
 
diff --git a/config/riscv/meson.build b/config/riscv/meson.build
new file mode 100644
index 0000000000..0c16c31fc2
--- /dev/null
+++ b/config/riscv/meson.build
@@ -0,0 +1,143 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2017 Intel Corporation.
+# Copyright(c) 2017 Cavium, Inc
+# Copyright(c) 2021 PANTHEON.tech s.r.o.
+# Copyright(c) 2022 StarFive
+# Copyright(c) 2022 SiFive
+# Copyright(c) 2022 Semihalf
+
+if not is_linux
+    error('Only Linux is supported at this point in time.')
+endif
+
+if not dpdk_conf.get('RTE_ARCH_64')
+    error('Only 64-bit compiles are supported for this platform type')
+endif
+
+dpdk_conf.set('RTE_ARCH', 'riscv')
+dpdk_conf.set('RTE_ARCH_RISCV', 1)
+dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
+
+# common flags to all riscv builds, with lowest priority
+flags_common = [
+    ['RTE_ARCH_RISCV', true],
+    ['RTE_CACHE_LINE_SIZE', 64],
+    # Set this to true if target emulates U-mode TIME CSR via M or S mode trap.
+    # This allows to remove a FENCE on rte_rdtsc_precise() as trap effectively
+    # acts as one.
+    ['RTE_RISCV_EMU_UTIME', false],
+    # Set this to true if target emulates U-mode CYCLE CSR via M or S mode trap.
+    # This allows to remove a FENCE on rte_rdtsc_precise() as trap effectively
+    # acts as one.
+    ['RTE_RISCV_EMU_UCYCLE', false],
+    # Manually set wall time clock frequency for the target. If 0, then it is
+    # read from /proc/device-tree/cpus/timebase-frequency. This property is
+    # guaranteed on Linux, as riscv time_init() requires it.
+    ['RTE_RISCV_TIME_FREQ', 0],
+]
+
+## SoC-specific options.
+# The priority is like this: arch > vendor > common.
+#
+# Note that currently there's no way of getting vendor/microarchitecture id
+# values in userspace which is why the logic of choosing the right flag
+# combination is strictly based on the values passed from a cross-file.
+vendor_generic = {
+    'description': 'Generic RISC-V',
+    'flags': [
+        ['RTE_MACHINE', '"riscv"'],
+        ['RTE_USE_C11_MEM_MODEL', true],
+        ['RTE_MAX_LCORE', 128],
+        ['RTE_MAX_NUMA_NODES', 2]
+    ],
+    'arch_config': {
+        'generic': {'machine_args': ['-march=rv64gc']}
+    }
+}
+
+arch_config_riscv = {
+    '0x8000000000000007': {
+        'machine_args':  ['-march=rv64gc', '-mtune=sifive-7-series'],
+        'flags': [
+            ['RTE_RISCV_EMU_UTIME', true],
+            ['RTE_RISCV_EMU_UCYCLE', true]
+        ]
+    },
+}
+
+vendor_sifive = {
+    'description': 'SiFive',
+    'flags': [
+        ['RTE_MACHINE', '"riscv"'],
+        ['RTE_USE_C11_MEM_MODEL', true],
+        ['RTE_MAX_LCORE', 4],
+        ['RTE_MAX_NUMA_NODES', 1],
+    ],
+    'arch_config': arch_config_riscv
+}
+
+vendors = {
+    'generic': vendor_generic,
+    '0x489': vendor_sifive
+}
+
+# Native/cross vendor/arch detection
+if not meson.is_cross_build()
+    if machine == 'default'
+        # default build
+        vendor_id = 'generic'
+        arch_id = 'generic'
+        message('generic RISC-V')
+    else
+        vendor_id = 'generic'
+        arch_id = 'generic'
+        warning('RISC-V arch discovery not available, using generic!')
+    endif
+else
+    # cross build
+    vendor_id = meson.get_cross_property('vendor_id')
+    arch_id = meson.get_cross_property('arch_id')
+endif
+
+if vendors.has_key(vendor_id)
+    vendor_config = vendors[vendor_id]
+else
+    error('Unsupported RISC-V vendor: @0@. '.format(vendor_id) +
+        'Please add support for it or use the generic ' +
+        '(-Dmachine=generic) build.')
+endif
+
+message('RISC-V vendor: ' + vendor_config['description'])
+message('RISC-V architecture id: ' + arch_id)
+
+arch_config = vendor_config['arch_config']
+if arch_config.has_key(arch_id)
+    # use the specified arch_id machine args if found
+    arch_config = arch_config[arch_id]
+else
+    # unknown micro-architecture id
+    error('Unsupported architecture @0@ of vendor @1@. '
+        .format(arch_id, vendor_id) +
+        'Please add support for it or use the generic ' +
+        '(-Dmachine=generic) build.')
+endif
+
+# Concatenate flags respecting priorities.
+dpdk_flags = flags_common + vendor_config['flags'] + arch_config.get('flags', [])
+
+# apply supported machine args
+machine_args = [] # Clear previous machine args
+foreach flag: arch_config['machine_args']
+    if cc.has_argument(flag)
+        machine_args += flag
+    endif
+endforeach
+
+# apply flags
+foreach flag: dpdk_flags
+    if flag.length() > 0
+        dpdk_conf.set(flag[0], flag[1])
+    endif
+endforeach
+message('Using machine args: @0@'.format(machine_args))
+
diff --git a/config/riscv/riscv64_linux_gcc b/config/riscv/riscv64_linux_gcc
new file mode 100644
index 0000000000..04248d7ecb
--- /dev/null
+++ b/config/riscv/riscv64_linux_gcc
@@ -0,0 +1,17 @@
+[binaries]
+c = 'riscv64-linux-gnu-gcc'
+cpp = 'riscv64-linux-gnu-g++'
+ar = 'riscv64-linux-gnu-ar'
+strip = 'riscv64-linux-gnu-strip'
+pcap-config = ''
+pkgconfig = 'riscv64-linux-gnu-pkg-config'
+
+[host_machine]
+system = 'linux'
+cpu_family = 'riscv64'
+cpu = 'rv64gc'
+endian = 'little'
+
+[properties]
+vendor_id = 'generic'
+arch_id = 'generic'
diff --git a/config/riscv/riscv64_sifive_u740_linux_gcc b/config/riscv/riscv64_sifive_u740_linux_gcc
new file mode 100644
index 0000000000..7b5ad2562d
--- /dev/null
+++ b/config/riscv/riscv64_sifive_u740_linux_gcc
@@ -0,0 +1,19 @@
+[binaries]
+c = 'riscv64-unknown-linux-gnu-gcc'
+cpp = 'riscv64-unknown-linux-gnu-g++'
+ar = 'riscv64-unknown-linux-gnu-ar'
+strip = 'riscv64-unknown-linux-gnu-strip'
+pcap-config = ''
+pkgconfig = 'riscv64-unknown-linux-gnu-pkg-config'
+
+[host_machine]
+system = 'linux'
+cpu_family = 'riscv64'
+cpu = 'rv64gc'
+endian = 'little'
+
+[properties]
+vendor_id = '0x489'
+arch_id = '0x8000000000000007'
+max_lcores = 4
+max_numa_nodes = 1
diff --git a/doc/guides/contributing/design.rst b/doc/guides/contributing/design.rst
index d5ca8b4d9c..0383afe5c8 100644
--- a/doc/guides/contributing/design.rst
+++ b/doc/guides/contributing/design.rst
@@ -42,7 +42,7 @@ Per Architecture Sources
 The following macro options can be used:
 
 * ``RTE_ARCH`` is a string that contains the name of the architecture.
-* ``RTE_ARCH_I686``, ``RTE_ARCH_X86_64``, ``RTE_ARCH_X86_X32``, ``RTE_ARCH_PPC_64``, ``RTE_ARCH_ARM``, ``RTE_ARCH_ARMv7`` or ``RTE_ARCH_ARM64`` are defined only if we are building for those architectures.
+* ``RTE_ARCH_I686``, ``RTE_ARCH_X86_64``, ``RTE_ARCH_X86_X32``, ``RTE_ARCH_PPC_64``, ``RTE_ARCH_RISCV``, ``RTE_ARCH_ARM``, ``RTE_ARCH_ARMv7`` or ``RTE_ARCH_ARM64`` are defined only if we are building for those architectures.
 
 Per Execution Environment Sources
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst b/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
new file mode 100644
index 0000000000..9907b35a1d
--- /dev/null
+++ b/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
@@ -0,0 +1,125 @@
+..  SPDX-License-Identifier: BSD-3-Clause
+    Copyright(c) 2020 ARM Corporation.
+    Copyright(c) 2022 StarFive
+    Copyright(c) 2022 SiFive
+    Copyright(c) 2022 Semihalf
+
+Cross compiling DPDK for RISC-V
+===============================
+
+This chapter describes how to cross compile DPDK for RISC-V from x86 build
+hosts.
+
+.. note::
+
+   While it's possible to compile DPDK natively on a RISC-V host, it is
+   currently recommended to cross-compile as Linux kernel does not offer any
+   way for userspace to discover the vendor and architecture identifiers of the
+   CPU and therefore any per-chip optimization options have to be chosen via
+   a cross-file or ``c_args``.
+
+
+Prerequisites
+-------------
+
+
+Linux kernel
+~~~~~~~~~~~~
+
+It is recommended to use Linux kernel built from
+`SiFive Freedom Unleashed SDK <https://github.com/sifive/freedom-u-sdk>`_.
+
+
+Meson prerequisites
+~~~~~~~~~~~~~~~~~~~
+
+Meson depends on pkgconfig to find the dependencies.
+The package ``pkg-config-riscv64-linux-gnu`` is required for RISC-V.
+To install it in Ubuntu::
+
+   sudo apt install pkg-config-riscv64-linux-gnu
+
+
+GNU toolchain
+-------------
+
+
+Obtain the cross toolchain
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The build process was tested using:
+
+* Ubuntu toolchain (the ``crossbuild-essential-riscv64`` package).
+
+* Latest `RISC-V GNU toolchain
+  <https://github.com/riscv/riscv-gnu-toolchain/releases>`_ on Ubuntu or Arch
+  Linux.
+
+Alternatively the toolchain may be built straight from the source, to do that
+follow the instructions on the riscv-gnu-toolchain github page.
+
+
+Unzip and add into the PATH
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+This step is only required for the riscv-gnu-toolchain. The Ubuntu toolchain is
+in the PATH already.
+
+.. code-block:: console
+
+   tar -xvf riscv64-glibc-ubuntu-20.04-<version>.tar.gz
+   export PATH=$PATH:<cross_install_dir>/riscv/bin
+
+
+Cross Compiling DPDK with GNU toolchain using Meson
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+To cross-compile DPDK for a desired target machine use the following command::
+
+   meson cross-build --cross-file <target_machine_configuration>
+   ninja -C cross-build
+
+For example if the target machine is a generic rv64gc RISC-V, use the following
+command::
+
+   meson riscv64-build-gcc --cross-file config/riscv/riscv64_linux_gcc
+   ninja -C riscv64-build-gcc
+
+If riscv-gnu-toolchain is used, binary names should be updated to match. Update the following lines in the cross-file:
+
+.. code-block:: console
+
+   [binaries]
+   c = 'riscv64-unknown-linux-gnu-gcc'
+   cpp = 'riscv64-unknown-linux-gnu-g++'
+   ar = 'riscv64-unknown-linux-gnu-ar'
+   strip = 'riscv64-unknown-linux-gnu-strip'
+   ...
+
+Some toolchains (such as freedom-u-sdk one) require also setting ``--sysroot``,
+otherwise include paths might not be resolved. To do so, add the appropriate
+paths to the cross-file:
+
+.. code-block:: console
+
+   [properties]
+   ...
+   c_args = ['--sysroot', '<path/to/toolchain/sysroot>']
+   cpp_args = c_args
+   c_link_args = ['--sysroot', '<path/to/toolchain/sysroot>']
+   cpp_link_args = c_link_args
+   ...
+
+
+Supported cross-compilation targets
+-----------------------------------
+
+Currently the following targets are supported:
+
+* Generic rv64gc ISA: ``config/riscv/riscv64_linux_gcc``
+
+* SiFive U740 SoC: ``config/riscv/riscv64_sifive_u740_linux_gcc``
+
+To add a new target support, ``config/riscv/meson.build`` has to be modified by
+adding a new vendor/architecture id and a corresponding cross-file has to be
+added to ``config/riscv`` directory.
diff --git a/doc/guides/linux_gsg/index.rst b/doc/guides/linux_gsg/index.rst
index 16a9a67260..747552c385 100644
--- a/doc/guides/linux_gsg/index.rst
+++ b/doc/guides/linux_gsg/index.rst
@@ -14,6 +14,7 @@ Getting Started Guide for Linux
     sys_reqs
     build_dpdk
     cross_build_dpdk_for_arm64
+    cross_build_dpdk_for_riscv
     linux_drivers
     build_sample_apps
     linux_eal_parameters
diff --git a/doc/guides/nics/features.rst b/doc/guides/nics/features.rst
index 21bedb743f..6c4fa74bc7 100644
--- a/doc/guides/nics/features.rst
+++ b/doc/guides/nics/features.rst
@@ -855,6 +855,11 @@ x86-64
 
 Support 64bits x86 architecture.
 
+rv64
+----
+
+Support 64-bit RISC-V architecture.
+
 
 .. _nic_features_usage_doc:
 
diff --git a/doc/guides/nics/features/default.ini b/doc/guides/nics/features/default.ini
index b1d18ac62c..02198682c6 100644
--- a/doc/guides/nics/features/default.ini
+++ b/doc/guides/nics/features/default.ini
@@ -74,6 +74,7 @@ ARMv8                =
 Power8               =
 x86-32               =
 x86-64               =
+rv64                 =
 Usage doc            =
 Design doc           =
 Perf doc             =
diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst
index 067118174b..453591e568 100644
--- a/doc/guides/rel_notes/release_22_07.rst
+++ b/doc/guides/rel_notes/release_22_07.rst
@@ -55,6 +55,29 @@ New Features
      Also, make sure to start the actual text at the margin.
      =======================================================
 
+* **Added initial RISC-V architecture support.***
+
+  Added EAL implementation for RISC-V architecture. The initial device the
+  porting was tested on is a HiFive Unmatched development board based on the
+  SiFive Freedom U740 SoC. In theory this implementation should work with any
+  ``rv64gc`` ISA compatible implementation with MMU supporting a reasonable
+  address space size (U740 uses sv39 MMU).
+
+  * Verified with meson tests. ``fast-tests`` suite passing with default config.
+  * Verified PMD operation with Intel x520-DA2 NIC (``ixgbe``) and ``test-pmd``
+    application. Packet transfer checked using all UIO drivers available for
+    non-IOMMU platforms: ``uio_pci_generic``, ``vfio-pci noiommu`` and
+    ``igb_uio``.
+  * The ``i40e`` PMD driver is disabled on RISC-V as ``rv64gc`` ISA has no
+    vector operations.
+  * RISCV support is currently limited to Linux.
+  * Clang compilation currently not supported due to issues with relocation
+    relaxation.
+  * Debug build of ``app/test/dpdk-test`` fails currently on RISC-V due to
+    seemingly invalid loop and goto jump code generation by GCC in
+    ``test_ring.c`` where extensive inlining increases the code size beyond the
+    capability of the generated instruction (JAL: +/-1MB PC-relative).
+
 * **Updated Intel iavf driver.**
 
   * Added Tx QoS queue rate limitation support.
diff --git a/drivers/net/i40e/meson.build b/drivers/net/i40e/meson.build
index efc5f93e35..a4c1c9079a 100644
--- a/drivers/net/i40e/meson.build
+++ b/drivers/net/i40e/meson.build
@@ -1,6 +1,12 @@
 # SPDX-License-Identifier: BSD-3-Clause
 # Copyright(c) 2017 Intel Corporation
 
+if arch_subdir == 'riscv'
+		build = false
+		reason = 'riscv arch not supported'
+		subdir_done()
+endif
+
 cflags += ['-DPF_DRIVER',
     '-DVF_DRIVER',
     '-DINTEGRATED_VF',
diff --git a/drivers/net/ixgbe/meson.build b/drivers/net/ixgbe/meson.build
index 162f8d5f46..88539e97d5 100644
--- a/drivers/net/ixgbe/meson.build
+++ b/drivers/net/ixgbe/meson.build
@@ -1,6 +1,12 @@
 # SPDX-License-Identifier: BSD-3-Clause
 # Copyright(c) 2017 Intel Corporation
 
+if arch_subdir == 'riscv'
+		build = false
+		reason = 'riscv arch not supported'
+		subdir_done()
+endif
+
 cflags += ['-DRTE_LIBRTE_IXGBE_BYPASS']
 
 subdir('base')
diff --git a/drivers/net/memif/meson.build b/drivers/net/memif/meson.build
index 680bc8631c..9afb495953 100644
--- a/drivers/net/memif/meson.build
+++ b/drivers/net/memif/meson.build
@@ -5,6 +5,11 @@ if not is_linux
     build = false
     reason = 'only supported on Linux'
 endif
+if arch_subdir == 'riscv'
+		build = false
+		reason = 'riscv arch not supported'
+		subdir_done()
+endif
 
 sources = files(
         'memif_socket.c',
diff --git a/drivers/net/tap/meson.build b/drivers/net/tap/meson.build
index c09713a67b..3efac9ac07 100644
--- a/drivers/net/tap/meson.build
+++ b/drivers/net/tap/meson.build
@@ -5,6 +5,11 @@ if not is_linux
     build = false
     reason = 'only supported on Linux'
 endif
+if arch_subdir == 'riscv'
+		build = false
+		reason = 'riscv arch not supported'
+		subdir_done()
+endif
 sources = files(
         'rte_eth_tap.c',
         'tap_bpf_api.c',
diff --git a/examples/l3fwd/meson.build b/examples/l3fwd/meson.build
index 0830b3eb31..75fa19b7fe 100644
--- a/examples/l3fwd/meson.build
+++ b/examples/l3fwd/meson.build
@@ -6,6 +6,12 @@
 # To build this example as a standalone application with an already-installed
 # DPDK instance, use 'make'
 
+if dpdk_conf.has('RTE_ARCH_RISCV')
+		build = false
+		reason = 'riscv arch not supported'
+		subdir_done()
+endif
+
 allow_experimental_apis = true
 deps += ['hash', 'lpm', 'fib', 'eventdev']
 sources = files(
diff --git a/lib/eal/riscv/include/meson.build b/lib/eal/riscv/include/meson.build
new file mode 100644
index 0000000000..d290ed82ed
--- /dev/null
+++ b/lib/eal/riscv/include/meson.build
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2022 StarFive
+# Copyright(c) 2022 SiFive
+# Copyright(c) 2022 Semihalf
+
+arch_headers = files(
+	'rte_atomic.h',
+	'rte_byteorder.h',
+	'rte_cpuflags.h',
+	'rte_cycles.h',
+	'rte_io.h',
+	'rte_mcslock.h',
+	'rte_memcpy.h',
+	'rte_pause.h',
+	'rte_pflock.h',
+	'rte_power_intrinsics.h',
+	'rte_prefetch.h',
+	'rte_rwlock.h',
+	'rte_spinlock.h',
+	'rte_ticketlock.h',
+	'rte_vect.h'
+)
+install_headers(arch_headers, subdir: get_option('include_subdir_arch'))
diff --git a/lib/eal/riscv/include/rte_atomic.h b/lib/eal/riscv/include/rte_atomic.h
new file mode 100644
index 0000000000..4b4633c914
--- /dev/null
+++ b/lib/eal/riscv/include/rte_atomic.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ * All rights reserved.
+ */
+
+#ifndef RTE_ATOMIC_RISCV_H
+#define RTE_ATOMIC_RISCV_H
+
+#ifndef RTE_FORCE_INTRINSICS
+#  error Platform must be built with RTE_FORCE_INTRINSICS
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <rte_common.h>
+#include <rte_config.h>
+#include "generic/rte_atomic.h"
+
+#define rte_mb()	asm volatile("fence rw, rw" : : : "memory")
+
+#define rte_wmb()	asm volatile("fence w, w" : : : "memory")
+
+#define rte_rmb()	asm volatile("fence r, r" : : : "memory")
+
+#define rte_smp_mb()	rte_mb()
+
+#define rte_smp_wmb()	rte_wmb()
+
+#define rte_smp_rmb()	rte_rmb()
+
+#define rte_io_mb()	asm volatile("fence iorw, iorw" : : : "memory")
+
+#define rte_io_wmb()	asm volatile("fence orw, ow" : : : "memory")
+
+#define rte_io_rmb()	asm volatile("fence ir, ir" : : : "memory")
+
+static __rte_always_inline void
+rte_atomic_thread_fence(int memorder)
+{
+	__atomic_thread_fence(memorder);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_ATOMIC_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_byteorder.h b/lib/eal/riscv/include/rte_byteorder.h
new file mode 100644
index 0000000000..21893505d6
--- /dev/null
+++ b/lib/eal/riscv/include/rte_byteorder.h
@@ -0,0 +1,44 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Inspired from FreeBSD src/sys/powerpc/include/endian.h
+ * Copyright(c) 1987, 1991, 1993
+ * The Regents of the University of California.  All rights reserved.
+ */
+
+#ifndef RTE_BYTEORDER_RISCV_H
+#define RTE_BYTEORDER_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <rte_common.h>
+#include "generic/rte_byteorder.h"
+
+#ifndef RTE_BYTE_ORDER
+#define RTE_BYTE_ORDER RTE_LITTLE_ENDIAN
+#endif
+
+#define rte_cpu_to_le_16(x) (x)
+#define rte_cpu_to_le_32(x) (x)
+#define rte_cpu_to_le_64(x) (x)
+
+#define rte_cpu_to_be_16(x) rte_bswap16(x)
+#define rte_cpu_to_be_32(x) rte_bswap32(x)
+#define rte_cpu_to_be_64(x) rte_bswap64(x)
+
+#define rte_le_to_cpu_16(x) (x)
+#define rte_le_to_cpu_32(x) (x)
+#define rte_le_to_cpu_64(x) (x)
+
+#define rte_be_to_cpu_16(x) rte_bswap16(x)
+#define rte_be_to_cpu_32(x) rte_bswap32(x)
+#define rte_be_to_cpu_64(x) rte_bswap64(x)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_BYTEORDER_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_cpuflags.h b/lib/eal/riscv/include/rte_cpuflags.h
new file mode 100644
index 0000000000..66e787f898
--- /dev/null
+++ b/lib/eal/riscv/include/rte_cpuflags.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014 IBM Corporation
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_CPUFLAGS_RISCV_H
+#define RTE_CPUFLAGS_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Enumeration of all CPU features supported
+ */
+enum rte_cpu_flag_t {
+	RTE_CPUFLAG_RISCV_ISA_A, /* Atomic */
+	RTE_CPUFLAG_RISCV_ISA_B, /* Bit-Manipulation */
+	RTE_CPUFLAG_RISCV_ISA_C, /* Compressed instruction */
+	RTE_CPUFLAG_RISCV_ISA_D, /* Double precision floating-point  */
+	RTE_CPUFLAG_RISCV_ISA_E, /* RV32E ISA */
+	RTE_CPUFLAG_RISCV_ISA_F, /* Single precision floating-point */
+	RTE_CPUFLAG_RISCV_ISA_G, /* Extension pack (IMAFD, Zicsr, Zifencei) */
+	RTE_CPUFLAG_RISCV_ISA_H, /* Hypervisor */
+	RTE_CPUFLAG_RISCV_ISA_I, /* RV32I/RV64I/IRV128I base ISA */
+	RTE_CPUFLAG_RISCV_ISA_J, /* Dynamic Translation Language */
+	RTE_CPUFLAG_RISCV_ISA_K, /* Reserved */
+	RTE_CPUFLAG_RISCV_ISA_L, /* Decimal Floating-Point */
+	RTE_CPUFLAG_RISCV_ISA_M, /* Integer Multiply/Divide */
+	RTE_CPUFLAG_RISCV_ISA_N, /* User-level interrupts */
+	RTE_CPUFLAG_RISCV_ISA_O, /* Reserved */
+	RTE_CPUFLAG_RISCV_ISA_P, /* Packed-SIMD */
+	RTE_CPUFLAG_RISCV_ISA_Q, /* Quad-precision floating-points */
+	RTE_CPUFLAG_RISCV_ISA_R, /* Reserved */
+	RTE_CPUFLAG_RISCV_ISA_S, /* Supervisor mode */
+	RTE_CPUFLAG_RISCV_ISA_T, /* Transactional memory */
+	RTE_CPUFLAG_RISCV_ISA_U, /* User mode */
+	RTE_CPUFLAG_RISCV_ISA_V, /* Vector */
+	RTE_CPUFLAG_RISCV_ISA_W, /* Reserved */
+	RTE_CPUFLAG_RISCV_ISA_X, /* Non-standard extension present */
+	RTE_CPUFLAG_RISCV_ISA_Y, /* Reserved */
+	RTE_CPUFLAG_RISCV_ISA_Z, /* Reserved */
+	/* The last item */
+	RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */
+};
+
+#include "generic/rte_cpuflags.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_CPUFLAGS_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_cycles.h b/lib/eal/riscv/include/rte_cycles.h
new file mode 100644
index 0000000000..1eb6e2bad2
--- /dev/null
+++ b/lib/eal/riscv/include/rte_cycles.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015 Cavium, Inc
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_CYCLES_RISCV_H
+#define RTE_CYCLES_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_cycles.h"
+
+#ifndef RTE_RISCV_RDTSC_USE_HPM
+#define RTE_RISCV_RDTSC_USE_HPM 0
+#endif
+
+#define RV64_CSRR(reg, value) \
+	asm volatile("csrr %0, " #reg : "=r" (value) : : "memory")
+
+/** Read wall time counter */
+static __rte_always_inline uint64_t
+__rte_riscv_rdtime(void)
+{
+	uint64_t tsc;
+	RV64_CSRR(time, tsc);
+	return tsc;
+}
+
+/** Read wall time counter ensuring no re-ordering */
+static __rte_always_inline uint64_t
+__rte_riscv_rdtime_precise(void)
+{
+#if !defined(RTE_RISCV_EMU_UTIME)
+	asm volatile("fence" : : : "memory");
+#endif
+	return __rte_riscv_rdtime();
+}
+
+/** Read hart cycle counter */
+static __rte_always_inline uint64_t
+__rte_riscv_rdcycle(void)
+{
+	uint64_t tsc;
+	RV64_CSRR(cycle, tsc);
+	return tsc;
+}
+
+/** Read hart cycle counter ensuring no re-ordering */
+static __rte_always_inline uint64_t
+__rte_riscv_rdcycle_precise(void)
+{
+#if !defined(RTE_RISCV_EMU_UCYCLE)
+	asm volatile("fence" : : : "memory");
+#endif
+	return __rte_riscv_rdcycle();
+}
+
+/**
+ * Read the time base register.
+ *
+ * @return
+ *   The time base for this lcore.
+ */
+static __rte_always_inline uint64_t
+rte_rdtsc(void)
+{
+	/**
+	 * By default TIME userspace counter is used. Although it's frequency
+	 * may not be enough for all applications.
+	 */
+	if (!RTE_RISCV_RDTSC_USE_HPM)
+		return __rte_riscv_rdtime();
+	/**
+	 * Alternatively HPM's CYCLE counter may be used. However this counter
+	 * is not guaranteed by ISA to either be stable frequency or always
+	 * enabled for userspace access (it may trap to kernel or firmware).
+	 */
+	return __rte_riscv_rdcycle();
+}
+
+static inline uint64_t
+rte_rdtsc_precise(void)
+{
+	if (!RTE_RISCV_RDTSC_USE_HPM)
+		return __rte_riscv_rdtime_precise();
+	return __rte_riscv_rdcycle_precise();
+}
+
+static __rte_always_inline uint64_t
+rte_get_tsc_cycles(void)
+{
+	return rte_rdtsc();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_CYCLES_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_io.h b/lib/eal/riscv/include/rte_io.h
new file mode 100644
index 0000000000..29659c9590
--- /dev/null
+++ b/lib/eal/riscv/include/rte_io.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2016 Cavium, Inc
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_IO_RISCV_H
+#define RTE_IO_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_io.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_IO_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_mcslock.h b/lib/eal/riscv/include/rte_mcslock.h
new file mode 100644
index 0000000000..b517cd5fc5
--- /dev/null
+++ b/lib/eal/riscv/include/rte_mcslock.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Arm Limited
+ */
+
+#ifndef RTE_MCSLOCK_RISCV_H
+#define RTE_MCSLOCK_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_mcslock.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_MCSLOCK_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_memcpy.h b/lib/eal/riscv/include/rte_memcpy.h
new file mode 100644
index 0000000000..e34f19396e
--- /dev/null
+++ b/lib/eal/riscv/include/rte_memcpy.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_MEMCPY_RISCV_H
+#define RTE_MEMCPY_RISCV_H
+
+#include <stdint.h>
+#include <string.h>
+
+#include "rte_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_memcpy.h"
+
+static inline void
+rte_mov16(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 16);
+}
+
+static inline void
+rte_mov32(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 32);
+}
+
+static inline void
+rte_mov48(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 48);
+}
+
+static inline void
+rte_mov64(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 64);
+}
+
+static inline void
+rte_mov128(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 128);
+}
+
+static inline void
+rte_mov256(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 256);
+}
+
+#define rte_memcpy(d, s, n)	memcpy((d), (s), (n))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_MEMCPY_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_pause.h b/lib/eal/riscv/include/rte_pause.h
new file mode 100644
index 0000000000..c24c1f32e8
--- /dev/null
+++ b/lib/eal/riscv/include/rte_pause.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_PAUSE_RISCV_H
+#define RTE_PAUSE_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "rte_atomic.h"
+
+#include "generic/rte_pause.h"
+
+static inline void rte_pause(void)
+{
+	/* Insert pause hint directly to be compatible with old compilers.
+	 * This will work even on platforms without Zihintpause extension
+	 * because this is a FENCE hint instruction which evaluates to NOP then.
+	 */
+	asm volatile(".int 0x0100000F"::: "memory");
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_PAUSE_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_pflock.h b/lib/eal/riscv/include/rte_pflock.h
new file mode 100644
index 0000000000..ce6ca02aca
--- /dev/null
+++ b/lib/eal/riscv/include/rte_pflock.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021 Microsoft Corporation
+ */
+#ifndef RTE_PFLOCK_RISCV_H
+#define RTE_PFLOCK_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_pflock.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_PFLOCK_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_power_intrinsics.h b/lib/eal/riscv/include/rte_power_intrinsics.h
new file mode 100644
index 0000000000..636e58e71f
--- /dev/null
+++ b/lib/eal/riscv/include/rte_power_intrinsics.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_POWER_INTRINSIC_RISCV_H
+#define RTE_POWER_INTRINSIC_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_common.h>
+
+#include "generic/rte_power_intrinsics.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_POWER_INTRINSIC_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_prefetch.h b/lib/eal/riscv/include/rte_prefetch.h
new file mode 100644
index 0000000000..966d9e2687
--- /dev/null
+++ b/lib/eal/riscv/include/rte_prefetch.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014 IBM Corporation
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_PREFETCH_RISCV_H
+#define RTE_PREFETCH_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_common.h>
+#include "generic/rte_prefetch.h"
+
+static inline void rte_prefetch0(const volatile void *p)
+{
+	RTE_SET_USED(p);
+}
+
+static inline void rte_prefetch1(const volatile void *p)
+{
+	RTE_SET_USED(p);
+}
+
+static inline void rte_prefetch2(const volatile void *p)
+{
+	RTE_SET_USED(p);
+}
+
+static inline void rte_prefetch_non_temporal(const volatile void *p)
+{
+	/* non-temporal version not available, fallback to rte_prefetch0 */
+	rte_prefetch0(p);
+}
+
+__rte_experimental
+static inline void
+rte_cldemote(const volatile void *p)
+{
+	RTE_SET_USED(p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_PREFETCH_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_rwlock.h b/lib/eal/riscv/include/rte_rwlock.h
new file mode 100644
index 0000000000..9cdaf1b0ef
--- /dev/null
+++ b/lib/eal/riscv/include/rte_rwlock.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_RWLOCK_RISCV_H
+#define RTE_RWLOCK_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_rwlock.h"
+
+static inline void
+rte_rwlock_read_lock_tm(rte_rwlock_t *rwl)
+{
+	rte_rwlock_read_lock(rwl);
+}
+
+static inline void
+rte_rwlock_read_unlock_tm(rte_rwlock_t *rwl)
+{
+	rte_rwlock_read_unlock(rwl);
+}
+
+static inline void
+rte_rwlock_write_lock_tm(rte_rwlock_t *rwl)
+{
+	rte_rwlock_write_lock(rwl);
+}
+
+static inline void
+rte_rwlock_write_unlock_tm(rte_rwlock_t *rwl)
+{
+	rte_rwlock_write_unlock(rwl);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_RWLOCK_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_spinlock.h b/lib/eal/riscv/include/rte_spinlock.h
new file mode 100644
index 0000000000..6af430735c
--- /dev/null
+++ b/lib/eal/riscv/include/rte_spinlock.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015 RehiveTech. All rights reserved.
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_SPINLOCK_RISCV_H
+#define RTE_SPINLOCK_RISCV_H
+
+#ifndef RTE_FORCE_INTRINSICS
+#  error Platform must be built with RTE_FORCE_INTRINSICS
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_common.h>
+#include "generic/rte_spinlock.h"
+
+static inline int rte_tm_supported(void)
+{
+	return 0;
+}
+
+static inline void
+rte_spinlock_lock_tm(rte_spinlock_t *sl)
+{
+	rte_spinlock_lock(sl); /* fall-back */
+}
+
+static inline int
+rte_spinlock_trylock_tm(rte_spinlock_t *sl)
+{
+	return rte_spinlock_trylock(sl);
+}
+
+static inline void
+rte_spinlock_unlock_tm(rte_spinlock_t *sl)
+{
+	rte_spinlock_unlock(sl);
+}
+
+static inline void
+rte_spinlock_recursive_lock_tm(rte_spinlock_recursive_t *slr)
+{
+	rte_spinlock_recursive_lock(slr); /* fall-back */
+}
+
+static inline void
+rte_spinlock_recursive_unlock_tm(rte_spinlock_recursive_t *slr)
+{
+	rte_spinlock_recursive_unlock(slr);
+}
+
+static inline int
+rte_spinlock_recursive_trylock_tm(rte_spinlock_recursive_t *slr)
+{
+	return rte_spinlock_recursive_trylock(slr);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_SPINLOCK_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_ticketlock.h b/lib/eal/riscv/include/rte_ticketlock.h
new file mode 100644
index 0000000000..b8d2a4f937
--- /dev/null
+++ b/lib/eal/riscv/include/rte_ticketlock.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Arm Limited
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_TICKETLOCK_RISCV_H
+#define RTE_TICKETLOCK_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_ticketlock.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_TICKETLOCK_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_vect.h b/lib/eal/riscv/include/rte_vect.h
new file mode 100644
index 0000000000..4600521c20
--- /dev/null
+++ b/lib/eal/riscv/include/rte_vect.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_VECT_RISCV_H
+#define RTE_VECT_RISCV_H
+
+#include <stdint.h>
+#include "generic/rte_vect.h"
+#include "rte_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RTE_VECT_DEFAULT_SIMD_BITWIDTH RTE_VECT_SIMD_DISABLED
+
+typedef int32_t		xmm_t __attribute__((vector_size(16)));
+
+#define XMM_SIZE	(sizeof(xmm_t))
+#define XMM_MASK	(XMM_SIZE - 1)
+
+typedef union rte_xmm {
+	xmm_t		x;
+	uint8_t		u8[XMM_SIZE / sizeof(uint8_t)];
+	uint16_t	u16[XMM_SIZE / sizeof(uint16_t)];
+	uint32_t	u32[XMM_SIZE / sizeof(uint32_t)];
+	uint64_t	u64[XMM_SIZE / sizeof(uint64_t)];
+	double		pd[XMM_SIZE / sizeof(double)];
+} __rte_aligned(8) rte_xmm_t;
+
+static inline xmm_t
+vect_load_128(void *p)
+{
+	xmm_t ret = *((xmm_t *)p);
+	return ret;
+}
+
+static inline xmm_t
+vect_and(xmm_t data, xmm_t mask)
+{
+	rte_xmm_t ret = (rte_xmm_t)data;
+	rte_xmm_t m = (rte_xmm_t)mask;
+	ret.u64[0] &= m.u64[0];
+	ret.u64[1] &= m.u64[1];
+	return ret.x;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_VECT_RISCV_H */
diff --git a/lib/eal/riscv/meson.build b/lib/eal/riscv/meson.build
new file mode 100644
index 0000000000..6ec53ea03a
--- /dev/null
+++ b/lib/eal/riscv/meson.build
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2017 Intel Corporation.
+
+subdir('include')
+
+sources += files(
+	'rte_cpuflags.c',
+	'rte_cycles.c',
+	'rte_hypervisor.c',
+	'rte_power_intrinsics.c',
+)
diff --git a/lib/eal/riscv/rte_cpuflags.c b/lib/eal/riscv/rte_cpuflags.c
new file mode 100644
index 0000000000..4f6d29b947
--- /dev/null
+++ b/lib/eal/riscv/rte_cpuflags.c
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#include "rte_cpuflags.h"
+
+#include <elf.h>
+#include <fcntl.h>
+#include <assert.h>
+#include <unistd.h>
+#include <string.h>
+
+#ifndef AT_HWCAP
+#define AT_HWCAP 16
+#endif
+
+#ifndef AT_HWCAP2
+#define AT_HWCAP2 26
+#endif
+
+#ifndef AT_PLATFORM
+#define AT_PLATFORM 15
+#endif
+
+enum cpu_register_t {
+	REG_NONE = 0,
+	REG_HWCAP,
+	REG_HWCAP2,
+	REG_PLATFORM,
+	REG_MAX
+};
+
+typedef uint32_t hwcap_registers_t[REG_MAX];
+
+/**
+ * Struct to hold a processor feature entry
+ */
+struct feature_entry {
+	uint32_t reg;
+	uint32_t bit;
+#define CPU_FLAG_NAME_MAX_LEN 64
+	char name[CPU_FLAG_NAME_MAX_LEN];
+};
+
+#define FEAT_DEF(name, reg, bit) \
+	[RTE_CPUFLAG_##name] = {reg, bit, #name},
+
+typedef Elf64_auxv_t _Elfx_auxv_t;
+
+const struct feature_entry rte_cpu_feature_table[] = {
+	FEAT_DEF(RISCV_ISA_A, REG_HWCAP,    0)
+	FEAT_DEF(RISCV_ISA_B, REG_HWCAP,    1)
+	FEAT_DEF(RISCV_ISA_C, REG_HWCAP,    2)
+	FEAT_DEF(RISCV_ISA_D, REG_HWCAP,    3)
+	FEAT_DEF(RISCV_ISA_E, REG_HWCAP,    4)
+	FEAT_DEF(RISCV_ISA_F, REG_HWCAP,    5)
+	FEAT_DEF(RISCV_ISA_G, REG_HWCAP,    6)
+	FEAT_DEF(RISCV_ISA_H, REG_HWCAP,    7)
+	FEAT_DEF(RISCV_ISA_I, REG_HWCAP,    8)
+	FEAT_DEF(RISCV_ISA_J, REG_HWCAP,    9)
+	FEAT_DEF(RISCV_ISA_K, REG_HWCAP,   10)
+	FEAT_DEF(RISCV_ISA_L, REG_HWCAP,   11)
+	FEAT_DEF(RISCV_ISA_M, REG_HWCAP,   12)
+	FEAT_DEF(RISCV_ISA_N, REG_HWCAP,   13)
+	FEAT_DEF(RISCV_ISA_O, REG_HWCAP,   14)
+	FEAT_DEF(RISCV_ISA_P, REG_HWCAP,   15)
+	FEAT_DEF(RISCV_ISA_Q, REG_HWCAP,   16)
+	FEAT_DEF(RISCV_ISA_R, REG_HWCAP,   17)
+	FEAT_DEF(RISCV_ISA_S, REG_HWCAP,   18)
+	FEAT_DEF(RISCV_ISA_T, REG_HWCAP,   19)
+	FEAT_DEF(RISCV_ISA_U, REG_HWCAP,   20)
+	FEAT_DEF(RISCV_ISA_V, REG_HWCAP,   21)
+	FEAT_DEF(RISCV_ISA_W, REG_HWCAP,   22)
+	FEAT_DEF(RISCV_ISA_X, REG_HWCAP,   23)
+	FEAT_DEF(RISCV_ISA_Y, REG_HWCAP,   24)
+	FEAT_DEF(RISCV_ISA_Z, REG_HWCAP,   25)
+};
+/*
+ * Read AUXV software register and get cpu features for ARM
+ */
+static void
+rte_cpu_get_features(hwcap_registers_t out)
+{
+	out[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP);
+	out[REG_HWCAP2] = rte_cpu_getauxval(AT_HWCAP2);
+}
+
+/*
+ * Checks if a particular flag is available on current machine.
+ */
+int
+rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
+{
+	const struct feature_entry *feat;
+	hwcap_registers_t regs = {0};
+
+	if (feature >= RTE_CPUFLAG_NUMFLAGS)
+		return -ENOENT;
+
+	feat = &rte_cpu_feature_table[feature];
+	if (feat->reg == REG_NONE)
+		return -EFAULT;
+
+	rte_cpu_get_features(regs);
+	return (regs[feat->reg] >> feat->bit) & 1;
+}
+
+const char *
+rte_cpu_get_flag_name(enum rte_cpu_flag_t feature)
+{
+	if (feature >= RTE_CPUFLAG_NUMFLAGS)
+		return NULL;
+	return rte_cpu_feature_table[feature].name;
+}
+
+void
+rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics)
+{
+	memset(intrinsics, 0, sizeof(*intrinsics));
+}
diff --git a/lib/eal/riscv/rte_cycles.c b/lib/eal/riscv/rte_cycles.c
new file mode 100644
index 0000000000..358f271311
--- /dev/null
+++ b/lib/eal/riscv/rte_cycles.c
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015 Cavium, Inc
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#include <stdio.h>
+
+#include "eal_private.h"
+#include "rte_byteorder.h"
+#include "rte_cycles.h"
+#include "rte_log.h"
+
+/** Read generic counter frequency */
+static uint64_t
+__rte_riscv_timefrq(void)
+{
+#define TIMEBASE_FREQ_SIZE	8
+	if (RTE_RISCV_TIME_FREQ > 0)
+		return RTE_RISCV_TIME_FREQ;
+	uint8_t buf[TIMEBASE_FREQ_SIZE];
+	ssize_t cnt;
+	FILE *file;
+
+	file = fopen("/proc/device-tree/cpus/timebase-frequency", "rb");
+	if (!file)
+		goto fail;
+
+	cnt = fread(buf, 1, TIMEBASE_FREQ_SIZE, file);
+	fclose(file);
+	switch (cnt) {
+	case 8:
+		return rte_be_to_cpu_64(*(uint64_t *)buf);
+	case 4:
+		return rte_be_to_cpu_32(*(uint32_t *)buf);
+	default:
+		break;
+	}
+fail:
+	RTE_LOG(WARNING, EAL, "Unable to read timebase-frequency from FDT.\n");
+	return 0;
+}
+
+uint64_t
+get_tsc_freq_arch(void)
+{
+	RTE_LOG(NOTICE, EAL, "TSC using RISC-V %s.\n",
+		RTE_RISCV_RDTSC_USE_HPM ? "rdcycle" : "rdtime");
+	if (!RTE_RISCV_RDTSC_USE_HPM)
+		return __rte_riscv_timefrq();
+#define CYC_PER_1MHZ 1E6
+	/*
+	 * Use real time clock to estimate current cycle frequency
+	 */
+	uint64_t ticks, frq;
+	uint64_t start_ticks, cur_ticks;
+	uint64_t start_cycle, end_cycle;
+
+	/* Do not proceed unless clock frequency can be obtained. */
+	frq = __rte_riscv_timefrq();
+	if (!frq)
+		return 0;
+
+	/* Number of ticks for 1/10 second */
+	ticks = frq / 10;
+
+	start_ticks = __rte_riscv_rdtime_precise();
+	start_cycle = rte_rdtsc_precise();
+	do {
+		cur_ticks = __rte_riscv_rdtime();
+	} while ((cur_ticks - start_ticks) < ticks);
+	end_cycle = rte_rdtsc_precise();
+
+	/* Adjust the cycles to next 1Mhz */
+	return RTE_ALIGN_MUL_CEIL((end_cycle - start_cycle) * 10, CYC_PER_1MHZ);
+}
diff --git a/lib/eal/riscv/rte_hypervisor.c b/lib/eal/riscv/rte_hypervisor.c
new file mode 100644
index 0000000000..92b5435993
--- /dev/null
+++ b/lib/eal/riscv/rte_hypervisor.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#include "rte_hypervisor.h"
+
+enum rte_hypervisor
+rte_hypervisor_get(void)
+{
+	return RTE_HYPERVISOR_UNKNOWN;
+}
diff --git a/lib/eal/riscv/rte_power_intrinsics.c b/lib/eal/riscv/rte_power_intrinsics.c
new file mode 100644
index 0000000000..240e7b6b87
--- /dev/null
+++ b/lib/eal/riscv/rte_power_intrinsics.c
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#include "rte_power_intrinsics.h"
+
+/**
+ * This function is not supported on RISC-V 64
+ */
+int
+rte_power_monitor(const struct rte_power_monitor_cond *pmc,
+		  const uint64_t tsc_timestamp)
+{
+	RTE_SET_USED(pmc);
+	RTE_SET_USED(tsc_timestamp);
+
+	return -ENOTSUP;
+}
+
+/**
+ * This function is not supported on RISC-V 64
+ */
+int
+rte_power_pause(const uint64_t tsc_timestamp)
+{
+	RTE_SET_USED(tsc_timestamp);
+
+	return -ENOTSUP;
+}
+
+/**
+ * This function is not supported on RISC-V 64
+ */
+int
+rte_power_monitor_wakeup(const unsigned int lcore_id)
+{
+	RTE_SET_USED(lcore_id);
+
+	return -ENOTSUP;
+}
+
+/**
+ * This function is not supported on RISC-V 64
+ */
+int
+rte_power_monitor_multi(const struct rte_power_monitor_cond pmc[],
+			const uint32_t num, const uint64_t tsc_timestamp)
+{
+	RTE_SET_USED(pmc);
+	RTE_SET_USED(num);
+	RTE_SET_USED(tsc_timestamp);
+
+	return -ENOTSUP;
+}
diff --git a/meson.build b/meson.build
index 937f6110c0..a8db04a1ee 100644
--- a/meson.build
+++ b/meson.build
@@ -50,6 +50,8 @@ elif host_machine.cpu_family().startswith('arm') or host_machine.cpu_family().st
     arch_subdir = 'arm'
 elif host_machine.cpu_family().startswith('ppc')
     arch_subdir = 'ppc'
+elif host_machine.cpu_family().startswith('riscv')
+    arch_subdir = 'riscv'
 endif
 
 # configure the build, and make sure configs here and in config folder are
-- 
2.30.2

[PATCH 04/11] net/ixgbe: enable vector stubs for RISC-V

[Stanislaw Kardach]

Re-use vector processing stubs in ixgbe PMD defined for PPC for RISC-V.
This enables ixgbe PMD usage in scalar mode on this architecture.

The ixgbe PMD driver was validated with Intel X520-DA2 NIC and the
test-pmd application. Packet transfer checked using all UIO drivers
available for non-IOMMU platforms: uio_pci_generic, vfio-pci noiommu and
igb_uio.

Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
---
 doc/guides/nics/features/ixgbe.ini | 1 +
 drivers/net/ixgbe/ixgbe_rxtx.c     | 4 ++--
 drivers/net/ixgbe/meson.build      | 6 ------
 3 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/doc/guides/nics/features/ixgbe.ini b/doc/guides/nics/features/ixgbe.ini
index c5333d1142..b776ca1cf1 100644
--- a/doc/guides/nics/features/ixgbe.ini
+++ b/doc/guides/nics/features/ixgbe.ini
@@ -54,6 +54,7 @@ Windows              = Y
 ARMv8                = Y
 x86-32               = Y
 x86-64               = Y
+rv64                 = Y
 
 [rte_flow items]
 eth                  = Y
diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c
index 9e8ea366a5..009d9b624a 100644
--- a/drivers/net/ixgbe/ixgbe_rxtx.c
+++ b/drivers/net/ixgbe/ixgbe_rxtx.c
@@ -5957,8 +5957,8 @@ ixgbe_config_rss_filter(struct rte_eth_dev *dev,
 	return 0;
 }
 
-/* Stubs needed for linkage when RTE_ARCH_PPC_64 is set */
-#if defined(RTE_ARCH_PPC_64)
+/* Stubs needed for linkage when RTE_ARCH_PPC_64 or RTE_ARCH_RISCV is set */
+#if defined(RTE_ARCH_PPC_64) || defined(RTE_ARCH_RISCV)
 int
 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
 {
diff --git a/drivers/net/ixgbe/meson.build b/drivers/net/ixgbe/meson.build
index 88539e97d5..162f8d5f46 100644
--- a/drivers/net/ixgbe/meson.build
+++ b/drivers/net/ixgbe/meson.build
@@ -1,12 +1,6 @@
 # SPDX-License-Identifier: BSD-3-Clause
 # Copyright(c) 2017 Intel Corporation
 
-if arch_subdir == 'riscv'
-		build = false
-		reason = 'riscv arch not supported'
-		subdir_done()
-endif
-
 cflags += ['-DRTE_LIBRTE_IXGBE_BYPASS']
 
 subdir('base')
-- 
2.30.2

[PATCH 05/11] net/memif: set memfd syscall ID on RISC-V

[Stanislaw Kardach]

Define the missing __NR_memfd_create syscall id to enable the memif PMD.

Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
---
 drivers/net/memif/meson.build     | 5 -----
 drivers/net/memif/rte_eth_memif.h | 2 ++
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/net/memif/meson.build b/drivers/net/memif/meson.build
index 9afb495953..680bc8631c 100644
--- a/drivers/net/memif/meson.build
+++ b/drivers/net/memif/meson.build
@@ -5,11 +5,6 @@ if not is_linux
     build = false
     reason = 'only supported on Linux'
 endif
-if arch_subdir == 'riscv'
-		build = false
-		reason = 'riscv arch not supported'
-		subdir_done()
-endif
 
 sources = files(
         'memif_socket.c',
diff --git a/drivers/net/memif/rte_eth_memif.h b/drivers/net/memif/rte_eth_memif.h
index a5ee23d42e..81e7dceae0 100644
--- a/drivers/net/memif/rte_eth_memif.h
+++ b/drivers/net/memif/rte_eth_memif.h
@@ -180,6 +180,8 @@ const char *memif_version(void);
 #define __NR_memfd_create 360
 #elif defined __i386__
 #define __NR_memfd_create 356
+#elif defined __riscv
+#define __NR_memfd_create 279
 #else
 #error "__NR_memfd_create unknown for this architecture"
 #endif
-- 
2.30.2

[PATCH 06/11] net/tap: set BPF syscall ID for RISC-V

[Stanislaw Kardach]

Define the missing __NR_bpf syscall id to enable the tap PMD.

Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
---
 drivers/net/tap/meson.build | 5 -----
 drivers/net/tap/tap_bpf.h   | 2 ++
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/net/tap/meson.build b/drivers/net/tap/meson.build
index 3efac9ac07..c09713a67b 100644
--- a/drivers/net/tap/meson.build
+++ b/drivers/net/tap/meson.build
@@ -5,11 +5,6 @@ if not is_linux
     build = false
     reason = 'only supported on Linux'
 endif
-if arch_subdir == 'riscv'
-		build = false
-		reason = 'riscv arch not supported'
-		subdir_done()
-endif
 sources = files(
         'rte_eth_tap.c',
         'tap_bpf_api.c',
diff --git a/drivers/net/tap/tap_bpf.h b/drivers/net/tap/tap_bpf.h
index f0b9fc7a2c..639bdf3a79 100644
--- a/drivers/net/tap/tap_bpf.h
+++ b/drivers/net/tap/tap_bpf.h
@@ -101,6 +101,8 @@ union bpf_attr {
 #  define __NR_bpf 351
 # elif defined(__powerpc__)
 #  define __NR_bpf 361
+# elif defined(__riscv)
+#  define __NR_bpf 280
 # else
 #  error __NR_bpf not defined
 # endif
-- 
2.30.2

[PATCH 07/11] examples/l3fwd: enable RISC-V operation

[Stanislaw Kardach]

Add missing em_mask_key() implementation and fix l3fwd_common.h
inclusion in FIB lookup functions to enable the l3fwd to be run on
RISC-V.

Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
---
 examples/l3fwd/l3fwd_em.c  | 8 ++++++++
 examples/l3fwd/l3fwd_fib.c | 2 ++
 examples/l3fwd/meson.build | 6 ------
 3 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
index 24d0910fe0..bbd3452546 100644
--- a/examples/l3fwd/l3fwd_em.c
+++ b/examples/l3fwd/l3fwd_em.c
@@ -239,6 +239,14 @@ em_mask_key(void *key, xmm_t mask)
 
 	return vec_and(data, mask);
 }
+#elif defined(RTE_ARCH_RISCV)
+static inline xmm_t
+em_mask_key(void *key, xmm_t mask)
+{
+	xmm_t data = vect_load_128(key);
+
+	return vect_and(data, mask);
+}
 #else
 #error No vector engine (SSE, NEON, ALTIVEC) available, check your toolchain
 #endif
diff --git a/examples/l3fwd/l3fwd_fib.c b/examples/l3fwd/l3fwd_fib.c
index 6e0054b4cb..bdb7d7535d 100644
--- a/examples/l3fwd/l3fwd_fib.c
+++ b/examples/l3fwd/l3fwd_fib.c
@@ -18,6 +18,8 @@
 #include "l3fwd_neon.h"
 #elif defined RTE_ARCH_PPC_64
 #include "l3fwd_altivec.h"
+#else
+#include "l3fwd_common.h"
 #endif
 #include "l3fwd_event.h"
 #include "l3fwd_route.h"
diff --git a/examples/l3fwd/meson.build b/examples/l3fwd/meson.build
index 75fa19b7fe..0830b3eb31 100644
--- a/examples/l3fwd/meson.build
+++ b/examples/l3fwd/meson.build
@@ -6,12 +6,6 @@
 # To build this example as a standalone application with an already-installed
 # DPDK instance, use 'make'
 
-if dpdk_conf.has('RTE_ARCH_RISCV')
-		build = false
-		reason = 'riscv arch not supported'
-		subdir_done()
-endif
-
 allow_experimental_apis = true
 deps += ['hash', 'lpm', 'fib', 'eventdev']
 sources = files(
-- 
2.30.2

[PATCH 08/11] test/cpuflags: add test for RISC-V cpu flag

[Stanislaw Kardach]

From: Michal Mazurek <maz@semihalf.com>

Add checks for all flag values defined in the RISC-V misa CSR register.

Signed-off-by: Michal Mazurek <maz@semihalf.com>
Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
---
 app/test/test_cpuflags.c | 81 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 81 insertions(+)

diff --git a/app/test/test_cpuflags.c b/app/test/test_cpuflags.c
index 40f6ac7fca..98a99c2c7d 100644
--- a/app/test/test_cpuflags.c
+++ b/app/test/test_cpuflags.c
@@ -200,6 +200,87 @@ test_cpuflags(void)
 	CHECK_FOR_FLAG(RTE_CPUFLAG_INVTSC);
 #endif
 
+#if defined(RTE_ARCH_RISCV)
+
+	printf("Check for RISCV_ISA_A:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_A);
+
+	printf("Check for RISCV_ISA_B:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_B);
+
+	printf("Check for RISCV_ISA_C:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_C);
+
+	printf("Check for RISCV_ISA_D:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_D);
+
+	printf("Check for RISCV_ISA_E:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_E);
+
+	printf("Check for RISCV_ISA_F:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_F);
+
+	printf("Check for RISCV_ISA_G:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_G);
+
+	printf("Check for RISCV_ISA_H:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_H);
+
+	printf("Check for RISCV_ISA_I:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_I);
+
+	printf("Check for RISCV_ISA_J:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_J);
+
+	printf("Check for RISCV_ISA_K:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_K);
+
+	printf("Check for RISCV_ISA_L:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_L);
+
+	printf("Check for RISCV_ISA_M:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_M);
+
+	printf("Check for RISCV_ISA_N:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_N);
+
+	printf("Check for RISCV_ISA_O:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_O);
+
+	printf("Check for RISCV_ISA_P:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_P);
+
+	printf("Check for RISCV_ISA_Q:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Q);
+
+	printf("Check for RISCV_ISA_R:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_R);
+
+	printf("Check for RISCV_ISA_S:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_S);
+
+	printf("Check for RISCV_ISA_T:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_T);
+
+	printf("Check for RISCV_ISA_U:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_U);
+
+	printf("Check for RISCV_ISA_V:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_V);
+
+	printf("Check for RISCV_ISA_W:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_W);
+
+	printf("Check for RISCV_ISA_X:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_X);
+
+	printf("Check for RISCV_ISA_Y:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Y);
+
+	printf("Check for RISCV_ISA_Z:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Z);
+#endif
+
 	/*
 	 * Check if invalid data is handled properly
 	 */
-- 
2.30.2

[PATCH 09/11] test/ring: disable problematic tests for RISC-V

[Stanislaw Kardach]

When compiling for RISC-V in debug mode the large amount of inlining in
test_ring_basic_ex() and test_ring_with_exact_size() (in test_ring.c)
leads to large loop bodies. This causes 'goto' and 'for' loop
PC-relative jumps generated by the compiler to go beyond the architecture
limitation of +/-1MB offset (the 'j <offset>' instruction). This
instruction should not be generated by the compiler since C language does
not limit the maximum distance for 'goto' or 'for' loop jumps.

This only happens in the unit test for ring which tries to perform long
loops with ring enqueue/dequeue and it seems to be caused by excessive
__rte_always_inline usage. ring perf test compiles just fine under
debug.

To work around this, disable the offending tests in debug mode.

Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
---
 app/test/test_ring.c                   | 8 ++++++++
 config/riscv/meson.build               | 5 +++++
 doc/guides/rel_notes/release_22_07.rst | 3 ++-
 3 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/app/test/test_ring.c b/app/test/test_ring.c
index bde33ab4a1..7d809c147b 100644
--- a/app/test/test_ring.c
+++ b/app/test/test_ring.c
@@ -955,6 +955,7 @@ test_ring_burst_bulk_tests4(unsigned int test_idx)
 	return -1;
 }
 
+#if !defined(RTE_RISCV_WO_DISABLE_RING_TESTS)
 /*
  * Test default, single element, bulk and burst APIs
  */
@@ -1189,6 +1190,7 @@ test_ring_with_exact_size(void)
 	rte_ring_free(exact_sz_r);
 	return -1;
 }
+#endif
 
 static int
 test_ring(void)
@@ -1200,12 +1202,18 @@ test_ring(void)
 	if (test_ring_negative_tests() < 0)
 		goto test_fail;
 
+/* Disable the following tests on RISC-V in debug mode. This is a work-around
+ * GCC bug for RISC-V which fails to generate proper jumps for loops with large
+ * bodies.
+ */
+#if !defined(RTE_RISCV_WO_DISABLE_RING_TESTS)
 	/* Some basic operations */
 	if (test_ring_basic_ex() < 0)
 		goto test_fail;
 
 	if (test_ring_with_exact_size() < 0)
 		goto test_fail;
+#endif
 
 	/* Burst and bulk operations with sp/sc, mp/mc and default.
 	 * The test cases are split into smaller test cases to
diff --git a/config/riscv/meson.build b/config/riscv/meson.build
index 0c16c31fc2..50d0b513bf 100644
--- a/config/riscv/meson.build
+++ b/config/riscv/meson.build
@@ -141,3 +141,8 @@ foreach flag: dpdk_flags
 endforeach
 message('Using machine args: @0@'.format(machine_args))
 
+# Enable work-around for ring unit tests in debug mode which fail to link
+# properly due to bad code generation by GCC.
+if get_option('optimization') == '0' or get_option('optimization') == 'g'
+    add_project_arguments('-DRTE_RISCV_WO_DISABLE_RING_TESTS', language: 'c')
+endif
diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst
index 453591e568..4d64b68dfd 100644
--- a/doc/guides/rel_notes/release_22_07.rst
+++ b/doc/guides/rel_notes/release_22_07.rst
@@ -76,7 +76,8 @@ New Features
   * Debug build of ``app/test/dpdk-test`` fails currently on RISC-V due to
     seemingly invalid loop and goto jump code generation by GCC in
     ``test_ring.c`` where extensive inlining increases the code size beyond the
-    capability of the generated instruction (JAL: +/-1MB PC-relative).
+    capability of the generated instruction (JAL: +/-1MB PC-relative). The
+    workaround is to disable ``test_ring_basic_ex()`` and ``test_ring_with_exact_size()`` on RISC-V on ``-O0`` or ``-Og``.
 
 * **Updated Intel iavf driver.**
 
-- 
2.30.2

Re: [PATCH 09/11] test/ring: disable problematic tests for RISC-V

[Stephen Hemminger]

On Thu,  5 May 2022 19:30:01 +0200
Stanislaw Kardach <kda@semihalf.com> wrote:

> When compiling for RISC-V in debug mode the large amount of inlining in
> test_ring_basic_ex() and test_ring_with_exact_size() (in test_ring.c)
> leads to large loop bodies. This causes 'goto' and 'for' loop
> PC-relative jumps generated by the compiler to go beyond the architecture
> limitation of +/-1MB offset (the 'j <offset>' instruction). This
> instruction should not be generated by the compiler since C language does
> not limit the maximum distance for 'goto' or 'for' loop jumps.
> 
> This only happens in the unit test for ring which tries to perform long
> loops with ring enqueue/dequeue and it seems to be caused by excessive
> __rte_always_inline usage. ring perf test compiles just fine under
> debug.
> 
> To work around this, disable the offending tests in debug mode.
> 
> Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
> Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
> Sponsored-by: Sam Grove <sam.grove@sifive.com>
> ---

It seems to me that fixing the excessive inlining in the ring code
could benefit all architectures, rather than neutering the tests
on RISCV.

Re: [PATCH 09/11] test/ring: disable problematic tests for RISC-V

[Stanisław Kardach]

[-- Attachment #1: Type: text/plain, Size: 1837 bytes --]

On Thu, May 5, 2022 at 7:35 PM Stephen Hemminger <stephen@networkplumber.org>
wrote:

> On Thu,  5 May 2022 19:30:01 +0200
> Stanislaw Kardach <kda@semihalf.com> wrote:
>
> > When compiling for RISC-V in debug mode the large amount of inlining in
> > test_ring_basic_ex() and test_ring_with_exact_size() (in test_ring.c)
> > leads to large loop bodies. This causes 'goto' and 'for' loop
> > PC-relative jumps generated by the compiler to go beyond the architecture
> > limitation of +/-1MB offset (the 'j <offset>' instruction). This
> > instruction should not be generated by the compiler since C language does
> > not limit the maximum distance for 'goto' or 'for' loop jumps.
> >
> > This only happens in the unit test for ring which tries to perform long
> > loops with ring enqueue/dequeue and it seems to be caused by excessive
> > __rte_always_inline usage. ring perf test compiles just fine under
> > debug.
> >
> > To work around this, disable the offending tests in debug mode.
> >
> > Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
> > Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
> > Sponsored-by: Sam Grove <sam.grove@sifive.com>
> > ---
>
> It seems to me that fixing the excessive inlining in the ring code
> could benefit all architectures, rather than neutering the tests
> on RISCV.
>
 True. Since this only happened in the tests that I've mentioned, my other
approach was to introduce a "slow" wrapper over test_ring_dequeue|enqueue()
which did not force inlining via __rte_always_inline and use it in
functional test functions. However after talking with Thomas Monjalon we've
decided to guard the debug build of RISC-V only.
Another thing is that this is a clear bug in the compiler, the relaxation
of the jump should not be done since RISC-V has long jump construct for
arbitrary jumps (auipc+jalr).

[-- Attachment #2: Type: text/html, Size: 2618 bytes --]

Re: [PATCH 09/11] test/ring: disable problematic tests for RISC-V

[Stephen Hemminger]

On Thu, 5 May 2022 19:43:43 +0200
Stanisław Kardach <kda@semihalf.com> wrote:

> On Thu, May 5, 2022 at 7:35 PM Stephen Hemminger <stephen@networkplumber.org>
> wrote:
> 
> > On Thu,  5 May 2022 19:30:01 +0200
> > Stanislaw Kardach <kda@semihalf.com> wrote:
> >  
> > > When compiling for RISC-V in debug mode the large amount of inlining in
> > > test_ring_basic_ex() and test_ring_with_exact_size() (in test_ring.c)
> > > leads to large loop bodies. This causes 'goto' and 'for' loop
> > > PC-relative jumps generated by the compiler to go beyond the architecture
> > > limitation of +/-1MB offset (the 'j <offset>' instruction). This
> > > instruction should not be generated by the compiler since C language does
> > > not limit the maximum distance for 'goto' or 'for' loop jumps.
> > >
> > > This only happens in the unit test for ring which tries to perform long
> > > loops with ring enqueue/dequeue and it seems to be caused by excessive
> > > __rte_always_inline usage. ring perf test compiles just fine under
> > > debug.
> > >
> > > To work around this, disable the offending tests in debug mode.
> > >
> > > Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
> > > Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
> > > Sponsored-by: Sam Grove <sam.grove@sifive.com>
> > > ---  
> >
> > It seems to me that fixing the excessive inlining in the ring code
> > could benefit all architectures, rather than neutering the tests
> > on RISCV.
> >  
>  True. Since this only happened in the tests that I've mentioned, my other
> approach was to introduce a "slow" wrapper over test_ring_dequeue|enqueue()
> which did not force inlining via __rte_always_inline and use it in
> functional test functions. However after talking with Thomas Monjalon we've
> decided to guard the debug build of RISC-V only.
> Another thing is that this is a clear bug in the compiler, the relaxation
> of the jump should not be done since RISC-V has long jump construct for
> arbitrary jumps (auipc+jalr).

There is no good reason the __rte_always_inline should be in the ring code.
The purpose of always inline should be only for code that would break if
not inlined.

RE: [PATCH 09/11] test/ring: disable problematic tests for RISC-V

[Honnappa Nagarahalli]

<snip>

> 
> When compiling for RISC-V in debug mode the large amount of inlining in
> test_ring_basic_ex() and test_ring_with_exact_size() (in test_ring.c) leads to
> large loop bodies. This causes 'goto' and 'for' loop PC-relative jumps generated
> by the compiler to go beyond the architecture limitation of +/-1MB offset (the
> 'j <offset>' instruction). This instruction should not be generated by the
> compiler since C language does not limit the maximum distance for 'goto' or
> 'for' loop jumps.
> 
> This only happens in the unit test for ring which tries to perform long loops
> with ring enqueue/dequeue and it seems to be caused by excessive
> __rte_always_inline usage. ring perf test compiles just fine under debug.
> 
> To work around this, disable the offending tests in debug mode.
Is this still required given you have submitted [1]

[1] http://patches.dpdk.org/project/dpdk/patch/20220510115758.457794-1-kda@semihalf.com/

> 
> Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
> Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
> Sponsored-by: Sam Grove <sam.grove@sifive.com>
> ---
>  app/test/test_ring.c                   | 8 ++++++++
>  config/riscv/meson.build               | 5 +++++
>  doc/guides/rel_notes/release_22_07.rst | 3 ++-
>  3 files changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/app/test/test_ring.c b/app/test/test_ring.c index
> bde33ab4a1..7d809c147b 100644
> --- a/app/test/test_ring.c
> +++ b/app/test/test_ring.c
> @@ -955,6 +955,7 @@ test_ring_burst_bulk_tests4(unsigned int test_idx)
>  	return -1;
>  }
> 
> +#if !defined(RTE_RISCV_WO_DISABLE_RING_TESTS)
>  /*
>   * Test default, single element, bulk and burst APIs
>   */
> @@ -1189,6 +1190,7 @@ test_ring_with_exact_size(void)
>  	rte_ring_free(exact_sz_r);
>  	return -1;
>  }
> +#endif
> 
>  static int
>  test_ring(void)
> @@ -1200,12 +1202,18 @@ test_ring(void)
>  	if (test_ring_negative_tests() < 0)
>  		goto test_fail;
> 
> +/* Disable the following tests on RISC-V in debug mode. This is a
> +work-around
> + * GCC bug for RISC-V which fails to generate proper jumps for loops
> +with large
> + * bodies.
> + */
> +#if !defined(RTE_RISCV_WO_DISABLE_RING_TESTS)
>  	/* Some basic operations */
>  	if (test_ring_basic_ex() < 0)
>  		goto test_fail;
> 
>  	if (test_ring_with_exact_size() < 0)
>  		goto test_fail;
> +#endif
> 
>  	/* Burst and bulk operations with sp/sc, mp/mc and default.
>  	 * The test cases are split into smaller test cases to diff --git
> a/config/riscv/meson.build b/config/riscv/meson.build index
> 0c16c31fc2..50d0b513bf 100644
> --- a/config/riscv/meson.build
> +++ b/config/riscv/meson.build
> @@ -141,3 +141,8 @@ foreach flag: dpdk_flags  endforeach  message('Using
> machine args: @0@'.format(machine_args))
> 
> +# Enable work-around for ring unit tests in debug mode which fail to
> +link # properly due to bad code generation by GCC.
> +if get_option('optimization') == '0' or get_option('optimization') == 'g'
> +    add_project_arguments('-DRTE_RISCV_WO_DISABLE_RING_TESTS',
> +language: 'c') endif
> diff --git a/doc/guides/rel_notes/release_22_07.rst
> b/doc/guides/rel_notes/release_22_07.rst
> index 453591e568..4d64b68dfd 100644
> --- a/doc/guides/rel_notes/release_22_07.rst
> +++ b/doc/guides/rel_notes/release_22_07.rst
> @@ -76,7 +76,8 @@ New Features
>    * Debug build of ``app/test/dpdk-test`` fails currently on RISC-V due to
>      seemingly invalid loop and goto jump code generation by GCC in
>      ``test_ring.c`` where extensive inlining increases the code size beyond the
> -    capability of the generated instruction (JAL: +/-1MB PC-relative).
> +    capability of the generated instruction (JAL: +/-1MB PC-relative). The
> +    workaround is to disable ``test_ring_basic_ex()`` and
> ``test_ring_with_exact_size()`` on RISC-V on ``-O0`` or ``-Og``.
> 
>  * **Updated Intel iavf driver.**
> 
> --
> 2.30.2

Re: [PATCH 09/11] test/ring: disable problematic tests for RISC-V

[Stanisław Kardach]

On Wed, May 11, 2022 at 1:28 AM Honnappa Nagarahalli
<Honnappa.Nagarahalli@arm.com> wrote:
>
> <snip>
>
> >
> > When compiling for RISC-V in debug mode the large amount of inlining in
> > test_ring_basic_ex() and test_ring_with_exact_size() (in test_ring.c) leads to
> > large loop bodies. This causes 'goto' and 'for' loop PC-relative jumps generated
> > by the compiler to go beyond the architecture limitation of +/-1MB offset (the
> > 'j <offset>' instruction). This instruction should not be generated by the
> > compiler since C language does not limit the maximum distance for 'goto' or
> > 'for' loop jumps.
> >
> > This only happens in the unit test for ring which tries to perform long loops
> > with ring enqueue/dequeue and it seems to be caused by excessive
> > __rte_always_inline usage. ring perf test compiles just fine under debug.
> >
> > To work around this, disable the offending tests in debug mode.
> Is this still required given you have submitted [1]
>
> [1] http://patches.dpdk.org/project/dpdk/patch/20220510115758.457794-1-kda@semihalf.com/
Correct, this patch is no longer necessary and marked as superseded in
patchwork. I did send v2 and v3 series without it. Thank you for
taking a look.

>
> >
> > Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
> > Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
> > Sponsored-by: Sam Grove <sam.grove@sifive.com>
> > ---
> >  app/test/test_ring.c                   | 8 ++++++++
> >  config/riscv/meson.build               | 5 +++++
> >  doc/guides/rel_notes/release_22_07.rst | 3 ++-
> >  3 files changed, 15 insertions(+), 1 deletion(-)
> >
> > diff --git a/app/test/test_ring.c b/app/test/test_ring.c index
> > bde33ab4a1..7d809c147b 100644
> > --- a/app/test/test_ring.c
> > +++ b/app/test/test_ring.c
> > @@ -955,6 +955,7 @@ test_ring_burst_bulk_tests4(unsigned int test_idx)
> >       return -1;
> >  }
> >
> > +#if !defined(RTE_RISCV_WO_DISABLE_RING_TESTS)
> >  /*
> >   * Test default, single element, bulk and burst APIs
> >   */
> > @@ -1189,6 +1190,7 @@ test_ring_with_exact_size(void)
> >       rte_ring_free(exact_sz_r);
> >       return -1;
> >  }
> > +#endif
> >
> >  static int
> >  test_ring(void)
> > @@ -1200,12 +1202,18 @@ test_ring(void)
> >       if (test_ring_negative_tests() < 0)
> >               goto test_fail;
> >
> > +/* Disable the following tests on RISC-V in debug mode. This is a
> > +work-around
> > + * GCC bug for RISC-V which fails to generate proper jumps for loops
> > +with large
> > + * bodies.
> > + */
> > +#if !defined(RTE_RISCV_WO_DISABLE_RING_TESTS)
> >       /* Some basic operations */
> >       if (test_ring_basic_ex() < 0)
> >               goto test_fail;
> >
> >       if (test_ring_with_exact_size() < 0)
> >               goto test_fail;
> > +#endif
> >
> >       /* Burst and bulk operations with sp/sc, mp/mc and default.
> >        * The test cases are split into smaller test cases to diff --git
> > a/config/riscv/meson.build b/config/riscv/meson.build index
> > 0c16c31fc2..50d0b513bf 100644
> > --- a/config/riscv/meson.build
> > +++ b/config/riscv/meson.build
> > @@ -141,3 +141,8 @@ foreach flag: dpdk_flags  endforeach  message('Using
> > machine args: @0@'.format(machine_args))
> >
> > +# Enable work-around for ring unit tests in debug mode which fail to
> > +link # properly due to bad code generation by GCC.
> > +if get_option('optimization') == '0' or get_option('optimization') == 'g'
> > +    add_project_arguments('-DRTE_RISCV_WO_DISABLE_RING_TESTS',
> > +language: 'c') endif
> > diff --git a/doc/guides/rel_notes/release_22_07.rst
> > b/doc/guides/rel_notes/release_22_07.rst
> > index 453591e568..4d64b68dfd 100644
> > --- a/doc/guides/rel_notes/release_22_07.rst
> > +++ b/doc/guides/rel_notes/release_22_07.rst
> > @@ -76,7 +76,8 @@ New Features
> >    * Debug build of ``app/test/dpdk-test`` fails currently on RISC-V due to
> >      seemingly invalid loop and goto jump code generation by GCC in
> >      ``test_ring.c`` where extensive inlining increases the code size beyond the
> > -    capability of the generated instruction (JAL: +/-1MB PC-relative).
> > +    capability of the generated instruction (JAL: +/-1MB PC-relative). The
> > +    workaround is to disable ``test_ring_basic_ex()`` and
> > ``test_ring_with_exact_size()`` on RISC-V on ``-O0`` or ``-Og``.
> >
> >  * **Updated Intel iavf driver.**
> >
> > --
> > 2.30.2
>

[PATCH 10/11] devtools: add RISC-V to test-meson-builds.sh

[Stanislaw Kardach]

Validate RISC-V compilation when test-meson-builds.sh is called. The
check will be only performed if appropriate toolchain is present on the
system (same as with other architectures).

Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
---
 devtools/test-meson-builds.sh | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/devtools/test-meson-builds.sh b/devtools/test-meson-builds.sh
index a653b253cb..12513e9d7f 100755
--- a/devtools/test-meson-builds.sh
+++ b/devtools/test-meson-builds.sh
@@ -275,6 +275,12 @@ for f in $srcdir/config/ppc/ppc* ; do
 	build $targetdir $f ABI $use_shared
 done
 
+# RISC-V configurations
+for f in $srcdir/config/riscv/riscv* ; do
+	targetdir=build-$(basename $f | tr '_' '-' | cut -d'-' -f-2)
+	build $targetdir $f ABI $use_shared
+done
+
 # Test installation of the x86-generic target, to be used for checking
 # the sample apps build using the pkg-config file for cflags and libs
 load_env cc
-- 
2.30.2

[PATCH 11/11] test/hash: report non HTM numbers for single r/w

[Stanislaw Kardach]

In hash_readwrite_perf_autotest a single read and write operation is
benchmarked for both HTM and non HTM cases. However the result summary
only shows the HTM value. Therefore add the non HTM value for
completeness.

Fixes: 0eb3726ebcf1 ("test/hash: add test for read/write concurrency")
Cc: yipeng1.wang@intel.com

Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
---
 app/test/test_hash_readwrite.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/app/test/test_hash_readwrite.c b/app/test/test_hash_readwrite.c
index 9b192f2b5e..6373e62d33 100644
--- a/app/test/test_hash_readwrite.c
+++ b/app/test/test_hash_readwrite.c
@@ -664,8 +664,12 @@ test_hash_rw_perf_main(void)
 	printf("Results summary:\n");
 	printf("================\n");
 
-	printf("single read: %u\n", htm_results.single_read);
-	printf("single write: %u\n", htm_results.single_write);
+	printf("HTM:\n");
+	printf("  single read: %u\n", htm_results.single_read);
+	printf("  single write: %u\n", htm_results.single_write);
+	printf("non HTM:\n");
+	printf("  single read: %u\n", non_htm_results.single_read);
+	printf("  single write: %u\n", non_htm_results.single_write);
 	for (i = 0; i < NUM_TEST; i++) {
 		printf("+++ core_cnt: %u +++\n", core_cnt[i]);
 		printf("HTM:\n");
-- 
2.30.2

Re: [PATCH 00/11] Introduce support for RISC-V architecture

[David Marchand]

On Thu, May 5, 2022 at 7:30 PM Stanislaw Kardach <kda@semihalf.com> wrote:
>
> This patchset adds support for building and running DPDK on 64bit RISC-V
> architecture. The initial support targets rv64gc (rv64imafdc) ISA and
> was tested on SiFive Unmatched development board with the Freedom U740
> SoC running Linux (freedom-u-sdk based kernel).
> I have tested this codebase using DPDK unit and perf tests as well as
> test-pmd, l2fwd and l3fwd examples.
> The NIC attached to the DUT was Intel X520-DA2 which uses ixgbe PMD.
> On the UIO side, since U740 does not have an IOMMU, I've used igb_uio,
> uio_pci_generic and vfio-pci noiommu drivers.
>
> Commits 1-2 fix small issues which are encountered if a given platform
>    does not support any vector operations (which is the case with U740).
> Commit 3 introduces EAL and build system support for RISC-V architecture
>    as well as documentation updates.
> Commits 4-7 add missing defines and stubs to enable RISC-V operation in
>    non-EAL parts.
> Commit 8 adds RISC-V specific cpuflags test.
> Commit 9 works around a bug in the current GCC in test_ring compiled
>    with -O0 or -Og.
> Commit 10 adds RISC-V testing to test-meson-builds.sh automatically
>    iterating over cross-compile config files (currently present for
>    generic rv64gc and SiFive U740).
> Commit 11 extends hash r/w perf test by displaying both HTM and non-HTM
>    measurements. This is an extraneous commit which is not directly
>    needed for RISC-V support but was noticed when we have started
>    gathering test results. If needed, I can submit it separately.
>
> I appreciate Your comments and feedback.

Thanks for working on this!

Please add a cross compilation job to GHA, something like:
https://github.com/david-marchand/dpdk/commit/4023e28f9050b85fb138eba14068bfe882036f01
Which looks to run fine:
https://github.com/david-marchand/dpdk/runs/6319625002?check_suite_focus=true

Testing all riscv configs in test-meson-buils.sh seems too much to me.
Is there a real value to test both current targets?

About the new "Sponsored-by" tag, it should not raise warnings in the
CI if we agree on its addition.

devtools/check-meson.py caught coding style issues.

In general, please avoid letting arch specific headers leak
internal/non rte_ prefixed helpers out of them.
For example, I noticed a RV64_CSRR macro that can be undefined after usage.

Patch 3 is huge, not sure it is easy to split, did you consider doing so?

The release notes update is verbose and some parts could be dropped,
like the list of verifications that are fine in a series cover letter.

Please resubmit fixes separately from this series so that we can merge
them sooner than this series.


-- 
David Marchand

Re: [PATCH 00/11] Introduce support for RISC-V architecture

[Stanisław Kardach]

[-- Attachment #1: Type: text/plain, Size: 4724 bytes --]

On Fri, May 6, 2022 at 11:13 AM David Marchand <david.marchand@redhat.com>
wrote:

> On Thu, May 5, 2022 at 7:30 PM Stanislaw Kardach <kda@semihalf.com> wrote:
> >
> > This patchset adds support for building and running DPDK on 64bit RISC-V
> > architecture. The initial support targets rv64gc (rv64imafdc) ISA and
> > was tested on SiFive Unmatched development board with the Freedom U740
> > SoC running Linux (freedom-u-sdk based kernel).
> > I have tested this codebase using DPDK unit and perf tests as well as
> > test-pmd, l2fwd and l3fwd examples.
> > The NIC attached to the DUT was Intel X520-DA2 which uses ixgbe PMD.
> > On the UIO side, since U740 does not have an IOMMU, I've used igb_uio,
> > uio_pci_generic and vfio-pci noiommu drivers.
> >
> > Commits 1-2 fix small issues which are encountered if a given platform
> >    does not support any vector operations (which is the case with U740).
> > Commit 3 introduces EAL and build system support for RISC-V architecture
> >    as well as documentation updates.
> > Commits 4-7 add missing defines and stubs to enable RISC-V operation in
> >    non-EAL parts.
> > Commit 8 adds RISC-V specific cpuflags test.
> > Commit 9 works around a bug in the current GCC in test_ring compiled
> >    with -O0 or -Og.
> > Commit 10 adds RISC-V testing to test-meson-builds.sh automatically
> >    iterating over cross-compile config files (currently present for
> >    generic rv64gc and SiFive U740).
> > Commit 11 extends hash r/w perf test by displaying both HTM and non-HTM
> >    measurements. This is an extraneous commit which is not directly
> >    needed for RISC-V support but was noticed when we have started
> >    gathering test results. If needed, I can submit it separately.
> >
> > I appreciate Your comments and feedback.
>
> Thanks for working on this!
>
Thanks for your review!

>
> Please add a cross compilation job to GHA, something like:
>
> https://github.com/david-marchand/dpdk/commit/4023e28f9050b85fb138eba14068bfe882036f01
> Which looks to run fine:
>
> https://github.com/david-marchand/dpdk/runs/6319625002?check_suite_focus=true

Will do in V2.

>
>
> Testing all riscv configs in test-meson-buils.sh seems too much to me.
> Is there a real value to test both current targets?
>
It's for sanity and compilation coverage testing. I.e. SiFive variant has a
specific build config which does not require extra barriers when reading
time and cycle registers for rte_rdtsc_precise(). I want to make sure that
if anyone changes some code based on configuration flags, it gets at least
compile-checked.
I believe similar thing is done for Aarch64 builds.

>
> About the new "Sponsored-by" tag, it should not raise warnings in the
> CI if we agree on its addition.
>
I'll modify it in V2 to be in form of:
  Sponsored by: StarFive Technology
  ...
  Signed-off-by: ...
This was suggested by Stephen Hemminger as having a precedent in Linux
kernel. Interestingly enough first use of this tag in kernel source was
this year in January.

>
> devtools/check-meson.py caught coding style issues.
>
Will fix in V2.

>
> In general, please avoid letting arch specific headers leak
> internal/non rte_ prefixed helpers out of them.
> For example, I noticed a RV64_CSRR macro that can be undefined after usage.
>
Thanks for noticing. I'l fix this one in V2.
There are 2 other symbols that leak but on purpose (out of a better
idea): vect_load_128() and vect_and(). Both are used in l3fwd_em to
simulate vector operations. Other platforms reference their intrinsics
straight in the l3fwd_em.c. As I don't have support for vector ops and I
wanted to indicate that xmm_t should be an isolated API, I've put both in
rte_vect.h. That said I'm not happy with this solution and am open to
suggestions on how to solve it neatly.

>
> Patch 3 is huge, not sure it is easy to split, did you consider doing so?
>
It seems to me the nature of a new EAL implementation, I have to include
all symbols, otherwise DPDK won't compile.
Alternatively I could have a huge initial patch with empty stubs that would
be filled in later commits. Downside of this approach is that it's hard to
verify each commit separately as tests will fail until all implementation
is there, so the division is only visual.

>
> The release notes update is verbose and some parts could be dropped,
> like the list of verifications that are fine in a series cover letter.
>
Will do. I'll move listed items to the cover letter.

>
> Please resubmit fixes separately from this series so that we can merge
> them sooner than this series.
>
Will do. Since at least 2 fixes are required for the RISC-V EAL to work or
compile, I'll put  Depends-on tag in the EAL commit.

>
>
> --
> David Marchand
>
>

[-- Attachment #2: Type: text/html, Size: 7032 bytes --]

Re: [PATCH 00/11] Introduce support for RISC-V architecture

[Thomas Monjalon]

09/05/2022 14:24, Stanisław Kardach:
> On Fri, May 6, 2022 at 11:13 AM David Marchand <david.marchand@redhat.com>
> wrote:
> > About the new "Sponsored-by" tag, it should not raise warnings in the
> > CI if we agree on its addition.
> >
> I'll modify it in V2 to be in form of:
>   Sponsored by: StarFive Technology

You mean removing the hyphen?
I think it is better to keep it so all tags have the same format.

>   ...
>   Signed-off-by: ...
> 
> This was suggested by Stephen Hemminger as having a precedent in Linux
> kernel. Interestingly enough first use of this tag in kernel source was
> this year in January.

The precedent is not strong enough to be copied in my opinion.

RE: [PATCH 00/11] Introduce support for RISC-V architecture

[Morten Brørup]

> From: Thomas Monjalon [mailto:thomas@monjalon.net]
> Sent: Monday, 9 May 2022 14.31
> 
> 09/05/2022 14:24, Stanisław Kardach:
> > On Fri, May 6, 2022 at 11:13 AM David Marchand
> <david.marchand@redhat.com>
> > wrote:
> > > About the new "Sponsored-by" tag, it should not raise warnings in
> the
> > > CI if we agree on its addition.
> > >
> > I'll modify it in V2 to be in form of:
> >   Sponsored by: StarFive Technology
> 
> You mean removing the hyphen?
> I think it is better to keep it so all tags have the same format.

I agree with Thomas. Please keep the hyphen.

> 
> >   ...
> >   Signed-off-by: ...
> >
> > This was suggested by Stephen Hemminger as having a precedent in
> Linux
> > kernel. Interestingly enough first use of this tag in kernel source
> was
> > this year in January.

I don't get it! Should employees start adding Sponsored-by: <Employer name> to their commits, when doing it as part of their job? And how about contract developers, should they also add a Sponsored-by: <Company name> tag, since they are working under contract and getting paid by that company?

Can someone please provide a reference to the discussion about this on the LKML? I'm curious why they felt the need for such a tag.

> 
> The precedent is not strong enough to be copied in my opinion.

I agree. Also, if it is an acceptable signature tag, the checkpatch.pl script should be updated:

https://elixir.bootlin.com/linux/v5.18-rc6/source/scripts/checkpatch.pl#L607

Re: [PATCH 00/11] Introduce support for RISC-V architecture

[Stanisław Kardach]

On Wed, May 11, 2022 at 10:09 AM Morten Brørup <mb@smartsharesystems.com> wrote:
>
> > From: Thomas Monjalon [mailto:thomas@monjalon.net]
> > Sent: Monday, 9 May 2022 14.31
> >
> > 09/05/2022 14:24, Stanisław Kardach:
> > > On Fri, May 6, 2022 at 11:13 AM David Marchand
> > <david.marchand@redhat.com>
> > > wrote:
> > > > About the new "Sponsored-by" tag, it should not raise warnings in
> > the
> > > > CI if we agree on its addition.
> > > >
> > > I'll modify it in V2 to be in form of:
> > >   Sponsored by: StarFive Technology
> >
> > You mean removing the hyphen?
> > I think it is better to keep it so all tags have the same format.
>
> I agree with Thomas. Please keep the hyphen.
>
> >
> > >   ...
> > >   Signed-off-by: ...
> > >
> > > This was suggested by Stephen Hemminger as having a precedent in
> > Linux
> > > kernel. Interestingly enough first use of this tag in kernel source
> > was
> > > this year in January.
>
> I don't get it! Should employees start adding Sponsored-by: <Employer name> to their commits, when doing it as part of their job? And how about contract developers, should they also add a Sponsored-by: <Company name> tag, since they are working under contract and getting paid by that company?
If I understand correctly, the concern about the commit log staying
technical and not introducing extra elements not beneficial to the
project, correct?
In the scope of this particular patchset, the companies sponsoring the
work are in copyrights for appropriate files, so I can remove the
tags.
For my own curiosity, what would be a proper way for a contract
developer to mark the company sponsoring the work? Some companies may
not care, others will. Maybe it would be beneficial to add a comment
on this into the contributing guide (or it's already there and I've
missed it)?
>
> Can someone please provide a reference to the discussion about this on the LKML? I'm curious why they felt the need for such a tag.
Actually I can't find any discussion on this. Perhaps it was missed
because: "Sponsored by" (without a hyphen) doesn't trigger checkpatch
and only 2 patches (6 and 7) in whole patchset contain it.
Patchset for reference:
https://www.spinics.net/lists/linux-wireless/msg220474.html

>
> >
> > The precedent is not strong enough to be copied in my opinion.
>
> I agree. Also, if it is an acceptable signature tag, the checkpatch.pl script should be updated:
>
> https://elixir.bootlin.com/linux/v5.18-rc6/source/scripts/checkpatch.pl#L607
>
>

Re: [PATCH 00/11] Introduce support for RISC-V architecture

[Thomas Monjalon]

11/05/2022 12:28, Stanisław Kardach:
> On Wed, May 11, 2022 at 10:09 AM Morten Brørup <mb@smartsharesystems.com> wrote:
> > > From: Thomas Monjalon [mailto:thomas@monjalon.net]
> > > 09/05/2022 14:24, Stanisław Kardach:
> > > > On Fri, May 6, 2022 at 11:13 AM David Marchand wrote:
> > > > > About the new "Sponsored-by" tag, it should not raise warnings in
> > > > > the CI if we agree on its addition.
> > > > 
> > > > I'll modify it in V2 to be in form of:
> > > >   Sponsored by: StarFive Technology
> > >
> > > You mean removing the hyphen?
> > > I think it is better to keep it so all tags have the same format.
> >
> > I agree with Thomas. Please keep the hyphen.
> >
> > > >   ...
> > > >   Signed-off-by: ...
> > > >
> > > > This was suggested by Stephen Hemminger as having a precedent in
> > > > Linux kernel. Interestingly enough first use of this tag in kernel
> > > > source was this year in January.
> >
> > I don't get it! Should employees start adding
> > Sponsored-by: <Employer name> to their commits,
> > when doing it as part of their job?
> > And how about contract developers, should they also add a
> > Sponsored-by: <Company name> tag,
> > since they are working under contract and getting paid by that company?

Nothing is mandatory.
It is just a way to give visibility of the sponsorship if requested.

> If I understand correctly, the concern about the commit log staying
> technical and not introducing extra elements not beneficial to the
> project, correct?
> In the scope of this particular patchset, the companies sponsoring the
> work are in copyrights for appropriate files, so I can remove the
> tags.
> For my own curiosity, what would be a proper way for a contract
> developer to mark the company sponsoring the work? Some companies may
> not care, others will. Maybe it would be beneficial to add a comment
> on this into the contributing guide (or it's already there and I've
> missed it)?

I don't know how to do it better.
Any other suggestions?

Re: [PATCH 00/11] Introduce support for RISC-V architecture

[David Marchand]

On Mon, May 9, 2022 at 2:24 PM Stanisław Kardach <kda@semihalf.com> wrote:
>> Testing all riscv configs in test-meson-buils.sh seems too much to me.
>> Is there a real value to test both current targets?
>
> It's for sanity and compilation coverage testing. I.e. SiFive variant has a specific build config which does not require extra barriers when reading time and cycle registers for rte_rdtsc_precise(). I want to make sure that if anyone changes some code based on configuration flags, it gets at least compile-checked.
> I believe similar thing is done for Aarch64 builds.

As far as I experienced, building all those aarch64 combinations never
revealed any specific platform compilation issue.
It only consumes cpu, disk and our (maintainers) time.
I proposed to Thomas to shrink aarch64 builds list not so long ago :-).

The best would be for SiFive to provide a system for the CI to do
those checks on their variant.


>> About the new "Sponsored-by" tag, it should not raise warnings in the
>> CI if we agree on its addition.
>
> I'll modify it in V2 to be in form of:
>   Sponsored by: StarFive Technology
>   ...
>   Signed-off-by: ...
> This was suggested by Stephen Hemminger as having a precedent in Linux kernel. Interestingly enough first use of this tag in kernel source was this year in January.

I don't have an opinion on the spelling.

At the moment, the checks raise a warning:
http://mails.dpdk.org/archives/test-report/2022-May/278580.html

My point is that for this new tag, either checkpatch.pl in kernel
handles it (which I don't think it is the case) or we need to disable
the signature check in checkpatch.pl and something is added in dpdk
checkpatches.sh to accept all known tags.


>> In general, please avoid letting arch specific headers leak
>> internal/non rte_ prefixed helpers out of them.
>> For example, I noticed a RV64_CSRR macro that can be undefined after usage.
>
> Thanks for noticing. I'l fix this one in V2.
> There are 2 other symbols that leak but on purpose (out of a better idea): vect_load_128() and vect_and(). Both are used in l3fwd_em to simulate vector operations. Other platforms reference their intrinsics straight in the l3fwd_em.c. As I don't have support for vector ops and I wanted to indicate that xmm_t should be an isolated API, I've put both in rte_vect.h. That said I'm not happy with this solution and am open to suggestions on how to solve it neatly.

I'll try to have a look in the next revision.


>>
>>
>> Patch 3 is huge, not sure it is easy to split, did you consider doing so?
>
> It seems to me the nature of a new EAL implementation, I have to include all symbols, otherwise DPDK won't compile.
> Alternatively I could have a huge initial patch with empty stubs that would be filled in later commits. Downside of this approach is that it's hard to verify each commit separately as tests will fail until all implementation is there, so the division is only visual.

If you are sure there is nothing that can be separated, let's keep it whole.



-- 
David Marchand

Re: [PATCH 00/11] Introduce support for RISC-V architecture

[Stanisław Kardach]

[-- Attachment #1: Type: text/plain, Size: 4196 bytes --]

On Mon, May 9, 2022 at 4:31 PM David Marchand <david.marchand@redhat.com>
wrote:

> On Mon, May 9, 2022 at 2:24 PM Stanisław Kardach <kda@semihalf.com> wrote:
> >> Testing all riscv configs in test-meson-buils.sh seems too much to me.
> >> Is there a real value to test both current targets?
> >
> > It's for sanity and compilation coverage testing. I.e. SiFive variant
> has a specific build config which does not require extra barriers when
> reading time and cycle registers for rte_rdtsc_precise(). I want to make
> sure that if anyone changes some code based on configuration flags, it gets
> at least compile-checked.
> > I believe similar thing is done for Aarch64 builds.
>
> As far as I experienced, building all those aarch64 combinations never
> revealed any specific platform compilation issue.
> It only consumes cpu, disk and our (maintainers) time.
> I proposed to Thomas to shrink aarch64 builds list not so long ago :-).
>
> The best would be for SiFive to provide a system for the CI to do
> those checks on their variant.
>
>
> >> About the new "Sponsored-by" tag, it should not raise warnings in the
> >> CI if we agree on its addition.
> >
> > I'll modify it in V2 to be in form of:
> >   Sponsored by: StarFive Technology
> >   ...
> >   Signed-off-by: ...
> > This was suggested by Stephen Hemminger as having a precedent in Linux
> kernel. Interestingly enough first use of this tag in kernel source was
> this year in January.
>
> I don't have an opinion on the spelling.
>
> At the moment, the checks raise a warning:
> http://mails.dpdk.org/archives/test-report/2022-May/278580.html
>
> My point is that for this new tag, either checkpatch.pl in kernel
> handles it (which I don't think it is the case) or we need to disable
> the signature check in checkpatch.pl and something is added in dpdk
> checkpatches.sh to accept all known tags.
>
BAD_SIGN_OFF handles more than just tag names (in total there's 10 cases
checked). I'm not sure replicating this to checkpatches.sh is worth the
maintenance.
Alternatively I could ignore BAD_SIGN_OFF on initial checkpatch.pl run and
then run it again with just the BAD_SIGN_OFF type and filter out the result.
In that case, what would be the acceptable content of Sponsored-by tag? For
line:
  Sponsored-by: StarFive Technology
Current checkpatch.pl generates (used --terse for brevity):
  0001-eal-add-initial-support-for-RISC-V-architecture.patch:55:
WARNING:BAD_SIGN_OFF: Non-standard signature: Sponsored-by:
  0001-eal-add-initial-support-for-RISC-V-architecture.patch:55:
ERROR:BAD_SIGN_OFF: Unrecognized email address: 'StarFive Technology'

Using "Sponsored by:" does not trigger checks above (still feels like a
hack).

>
> >> In general, please avoid letting arch specific headers leak
> >> internal/non rte_ prefixed helpers out of them.
> >> For example, I noticed a RV64_CSRR macro that can be undefined after
> usage.
> >
> > Thanks for noticing. I'l fix this one in V2.
> > There are 2 other symbols that leak but on purpose (out of a better
> idea): vect_load_128() and vect_and(). Both are used in l3fwd_em to
> simulate vector operations. Other platforms reference their intrinsics
> straight in the l3fwd_em.c. As I don't have support for vector ops and I
> wanted to indicate that xmm_t should be an isolated API, I've put both in
> rte_vect.h. That said I'm not happy with this solution and am open to
> suggestions on how to solve it neatly.
>
> I'll try to have a look in the next revision.
>
>
> >>
> >>
> >> Patch 3 is huge, not sure it is easy to split, did you consider doing
> so?
> >
> > It seems to me the nature of a new EAL implementation, I have to include
> all symbols, otherwise DPDK won't compile.
> > Alternatively I could have a huge initial patch with empty stubs that
> would be filled in later commits. Downside of this approach is that it's
> hard to verify each commit separately as tests will fail until all
> implementation is there, so the division is only visual.
>
> If you are sure there is nothing that can be separated, let's keep it
> whole.
>
>
>
> --
> David Marchand
>
>

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Re: [PATCH 00/11] Introduce support for RISC-V architecture

[Thomas Monjalon]

10/05/2022 13:21, Stanisław Kardach:
> On Mon, May 9, 2022 at 4:31 PM David Marchand <david.marchand@redhat.com>
> wrote:
> > >> About the new "Sponsored-by" tag, it should not raise warnings in the
> > >> CI if we agree on its addition.
> > >
> > > I'll modify it in V2 to be in form of:
> > >   Sponsored by: StarFive Technology
> > >   ...
> > >   Signed-off-by: ...
> > > This was suggested by Stephen Hemminger as having a precedent in Linux
> > kernel. Interestingly enough first use of this tag in kernel source was
> > this year in January.
> >
> > I don't have an opinion on the spelling.
> >
> > At the moment, the checks raise a warning:
> > http://mails.dpdk.org/archives/test-report/2022-May/278580.html
> >
> > My point is that for this new tag, either checkpatch.pl in kernel
> > handles it (which I don't think it is the case) or we need to disable
> > the signature check in checkpatch.pl and something is added in dpdk
> > checkpatches.sh to accept all known tags.
> >
> BAD_SIGN_OFF handles more than just tag names (in total there's 10 cases
> checked). I'm not sure replicating this to checkpatches.sh is worth the
> maintenance.
> Alternatively I could ignore BAD_SIGN_OFF on initial checkpatch.pl run and
> then run it again with just the BAD_SIGN_OFF type and filter out the result.
> In that case, what would be the acceptable content of Sponsored-by tag? For
> line:
>   Sponsored-by: StarFive Technology
> Current checkpatch.pl generates (used --terse for brevity):
>   0001-eal-add-initial-support-for-RISC-V-architecture.patch:55:
> WARNING:BAD_SIGN_OFF: Non-standard signature: Sponsored-by:
>   0001-eal-add-initial-support-for-RISC-V-architecture.patch:55:
> ERROR:BAD_SIGN_OFF: Unrecognized email address: 'StarFive Technology'
> 
> Using "Sponsored by:" does not trigger checks above (still feels like a
> hack).

Agree it is a hack,
and not having the hyphen breaks my Vim colouring :)

We can ignore this checkpatch warning, that's fine.

Re: [PATCH 00/11] Introduce support for RISC-V architecture

[Stanisław Kardach]

[-- Attachment #1: Type: text/plain, Size: 492 bytes --]

On Tue, May 10, 2022 at 2:32 PM Thomas Monjalon <thomas@monjalon.net> wrote:

> 10/05/2022 13:21, Stanisław Kardach:
> >
> > Using "Sponsored by:" does not trigger checks above (still feels like a
> > hack).
>
> Agree it is a hack,
> and not having the hyphen breaks my Vim colouring :)
>
> We can ignore this checkpatch warning, that's fine.
>
> Just to be sure before I post V2 - do you mean to ignore BAD_SIGN_OFF in
checkpatches.sh or rather somewhere in CI configuration?

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Re: [PATCH 00/11] Introduce support for RISC-V architecture

[Thomas Monjalon]

10/05/2022 16:00, Stanisław Kardach:
> On Tue, May 10, 2022 at 2:32 PM Thomas Monjalon <thomas@monjalon.net> wrote:
> 
> > 10/05/2022 13:21, Stanisław Kardach:
> > >
> > > Using "Sponsored by:" does not trigger checks above (still feels like a
> > > hack).
> >
> > Agree it is a hack,
> > and not having the hyphen breaks my Vim colouring :)
> >
> > We can ignore this checkpatch warning, that's fine.
> >
> > Just to be sure before I post V2 - do you mean to ignore BAD_SIGN_OFF in
> checkpatches.sh or rather somewhere in CI configuration?

Yes I mean CI will return BAD_SIGN_OFF, we'll take note,
but it won't be a blocker to accept the patch.

The CI can return minor warnings, that's OK.
We prefer avoiding the warnings, because it is more work
to check all the warnings manually, but I don't see a better solution here.

[PATCH v2 0/8] Introduce support for RISC-V architecture

[Stanislaw Kardach]

This patchset adds support for building and running DPDK on 64bit RISC-V
architecture. The initial support targets rv64gc (rv64imafdc) ISA and
was tested on SiFive Unmatched development board with the Freedom U740
SoC running Linux (freedom-u-sdk based kernel).
I have tested this codebase using DPDK unit and perf tests as well as
test-pmd, l2fwd and l3fwd examples.
The NIC attached to the DUT was Intel X520-DA2 which uses ixgbe PMD.
On the UIO side, since U740 does not have an IOMMU, I've used igb_uio,
uio_pci_generic and vfio-pci noiommu drivers.

Functional verification done using meson tests. fast-tests suite passing with
the default config.

PMD verification done using a Intel x520-DA2 NIC (ixgbe) and the test-pmd
application. Packet transfer checked using all UIO drivers available for
non-IOMMU platforms: uio_pci_generic, vfio-pci noiommu and igb_uio.

The i40e PMD driver is disabled on RISC-V as the rv64gc ISA has no vector
operations.

RISCV support is currently limited to Linux as the time measurement frequency
discovery is tied to reading a device-tree node via procfs.

Clang compilation currently not supported due to issues with missing relocation
relaxation.

Commit 1 introduces EAL and build system support for RISC-V architecture
   as well as documentation updates.
Commits 2-5 add missing defines and stubs to enable RISC-V operation in
   non-EAL parts.
Commit 6 adds RISC-V specific cpuflags test.
Commits 7-8 add RISC-V build testing to test-meson-builds.sh and github CI.

I appreciate Your comments and feedback.

Best Regards,
Stanislaw Kardach

v2:
  - Separate bug-fixes into separate series.
  - Prevent RV64_CSRR leak to API users.
  - Limit test-meson-builds.sh testing to a generic rv64gc configuration.
  - Clean-up release notes and fix style issues.


Michal Mazurek (2):
  eal: add initial support for RISC-V architecture
  test/cpuflags: add test for RISC-V cpu flag

Stanislaw Kardach (6):
  net/ixgbe: enable vector stubs for RISC-V
  net/memif: set memfd syscall ID on RISC-V
  net/tap: set BPF syscall ID for RISC-V
  examples/l3fwd: enable RISC-V operation
  devtools: add RISC-V to test-meson-builds.sh
  ci: add RISCV64 cross compilation job

---
NOTE: I have added maintainers for each commit based on MAINTAINERS file.
   However some modules (l3fwd, net/tap and cpuflags unit tests) do not have
   any maintainers assigned, hence I've targeted dev@dpdk.org mailing list as
   if it was a commit adding new files.

 .ci/linux-build.sh                            |   4 +
 .github/workflows/build.yml                   |  11 +-
 MAINTAINERS                                   |   6 +
 app/test/test_cpuflags.c                      |  81 ++++++++++
 app/test/test_xmmt_ops.h                      |  16 ++
 config/meson.build                            |   2 +
 config/riscv/meson.build                      | 143 ++++++++++++++++++
 config/riscv/riscv64_linux_gcc                |  17 +++
 config/riscv/riscv64_sifive_u740_linux_gcc    |  19 +++
 devtools/test-meson-builds.sh                 |   6 +
 doc/guides/contributing/design.rst            |   2 +-
 .../linux_gsg/cross_build_dpdk_for_riscv.rst  | 125 +++++++++++++++
 doc/guides/linux_gsg/index.rst                |   1 +
 doc/guides/nics/features.rst                  |   5 +
 doc/guides/nics/features/default.ini          |   1 +
 doc/guides/nics/features/ixgbe.ini            |   1 +
 doc/guides/rel_notes/release_22_07.rst        |   8 +
 drivers/net/i40e/meson.build                  |   6 +
 drivers/net/ixgbe/ixgbe_rxtx.c                |   4 +-
 drivers/net/memif/rte_eth_memif.h             |   2 +
 drivers/net/tap/tap_bpf.h                     |   2 +
 examples/l3fwd/l3fwd_em.c                     |   8 +
 examples/l3fwd/l3fwd_fib.c                    |   2 +
 lib/eal/riscv/include/meson.build             |  23 +++
 lib/eal/riscv/include/rte_atomic.h            |  52 +++++++
 lib/eal/riscv/include/rte_byteorder.h         |  44 ++++++
 lib/eal/riscv/include/rte_cpuflags.h          |  55 +++++++
 lib/eal/riscv/include/rte_cycles.h            | 105 +++++++++++++
 lib/eal/riscv/include/rte_io.h                |  21 +++
 lib/eal/riscv/include/rte_mcslock.h           |  18 +++
 lib/eal/riscv/include/rte_memcpy.h            |  63 ++++++++
 lib/eal/riscv/include/rte_pause.h             |  31 ++++
 lib/eal/riscv/include/rte_pflock.h            |  17 +++
 lib/eal/riscv/include/rte_power_intrinsics.h  |  22 +++
 lib/eal/riscv/include/rte_prefetch.h          |  50 ++++++
 lib/eal/riscv/include/rte_rwlock.h            |  44 ++++++
 lib/eal/riscv/include/rte_spinlock.h          |  67 ++++++++
 lib/eal/riscv/include/rte_ticketlock.h        |  21 +++
 lib/eal/riscv/include/rte_vect.h              |  55 +++++++
 lib/eal/riscv/meson.build                     |  11 ++
 lib/eal/riscv/rte_cpuflags.c                  | 122 +++++++++++++++
 lib/eal/riscv/rte_cycles.c                    |  77 ++++++++++
 lib/eal/riscv/rte_hypervisor.c                |  13 ++
 lib/eal/riscv/rte_power_intrinsics.c          |  56 +++++++
 meson.build                                   |   2 +
 45 files changed, 1437 insertions(+), 4 deletions(-)
 create mode 100644 config/riscv/meson.build
 create mode 100644 config/riscv/riscv64_linux_gcc
 create mode 100644 config/riscv/riscv64_sifive_u740_linux_gcc
 create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
 create mode 100644 lib/eal/riscv/include/meson.build
 create mode 100644 lib/eal/riscv/include/rte_atomic.h
 create mode 100644 lib/eal/riscv/include/rte_byteorder.h
 create mode 100644 lib/eal/riscv/include/rte_cpuflags.h
 create mode 100644 lib/eal/riscv/include/rte_cycles.h
 create mode 100644 lib/eal/riscv/include/rte_io.h
 create mode 100644 lib/eal/riscv/include/rte_mcslock.h
 create mode 100644 lib/eal/riscv/include/rte_memcpy.h
 create mode 100644 lib/eal/riscv/include/rte_pause.h
 create mode 100644 lib/eal/riscv/include/rte_pflock.h
 create mode 100644 lib/eal/riscv/include/rte_power_intrinsics.h
 create mode 100644 lib/eal/riscv/include/rte_prefetch.h
 create mode 100644 lib/eal/riscv/include/rte_rwlock.h
 create mode 100644 lib/eal/riscv/include/rte_spinlock.h
 create mode 100644 lib/eal/riscv/include/rte_ticketlock.h
 create mode 100644 lib/eal/riscv/include/rte_vect.h
 create mode 100644 lib/eal/riscv/meson.build
 create mode 100644 lib/eal/riscv/rte_cpuflags.c
 create mode 100644 lib/eal/riscv/rte_cycles.c
 create mode 100644 lib/eal/riscv/rte_hypervisor.c
 create mode 100644 lib/eal/riscv/rte_power_intrinsics.c

-- 
2.30.2

[PATCH v2 1/8] eal: add initial support for RISC-V architecture

[Stanislaw Kardach]

From: Michal Mazurek <maz@semihalf.com>

Add all necessary elements for DPDK to compile and run EAL on SiFive
Freedom U740 SoC which is based on SiFive U74-MC (ISA: rv64imafdc)
core complex.

This includes:

- EAL library implementation for rv64imafdc ISA.
- meson build structure for 'riscv' architecture. RTE_ARCH_RISCV define
  is added for architecture identification.
- xmm_t structure operation stubs as there is no vector support in the
  U74 core.

Compilation was tested on Ubuntu and Arch Linux using riscv64 toolchain.
Clang compilation currently not supported due to issues with missing
relocation relaxation.

Two rte_rdtsc() schemes are provided: stable low-resolution using rdtime
(default) and unstable high-resolution using rdcycle. User can override
the scheme by defining RTE_RISCV_RDTSC_USE_HPM=1 during compile time of
both DPDK and the application. The reasoning for this is as follows.
The RISC-V ISA mandates that clock read by rdtime has to be of constant
period and synchronized between all hardware threads within 1 tick
(chapter 10.1 in version 20191213 of RISC-V spec).
However this clock may not be of high-enough frequency for dataplane
uses. I.e. on HiFive Unmatched (FU740) it is 1MHz.
There is a high-resolution alternative in form of rdcycle which is
clocked at the core clock frequency. The drawbacks are that it may be
disabled during sleep (WFI) and its frequency might change due to DVFS.

The platform is currently marked as linux-only because rte_cycles
implementation uses the timebase-frequency device-tree node read through
the proc file system. Such approach was chosen because Linux kernel
depends on the presence of this device-tree node.

The i40e PMD driver is disabled on RISC-V as the rv64gc ISA has no vector
operations.

The compilation of following modules has been disabled by this commit
and will be re-enabled in later commits as fixes are introduced:
net/ixgbe, net/memif, net/tap, example/l3fwd.

Known checkpatch errors/warnings:

- ERROR:COMPLEX_MACRO in rte_atomic.h and rte_cycles.h due to inline
  assembly declarations.
- vector_size compiler attribute used in rte_vect.h directly.
- rte_*mb() used directly in rte_atomic.h to reduce code duplication.
- __atomic_thread_fence() used to implement rte_atomic_thread_fence().

Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
Signed-off-by: Michal Mazurek <maz@semihalf.com>
Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
---
Depends-on: series-22867 ("test/ring: remove excessive inlining")
Depends-on: series-22868 ("lpm: add a scalar version of lookupx4 function")
Depends-on: series-22869 ("examples/l3fwd: fix scalar LPM compilation")
---
 MAINTAINERS                                   |   6 +
 app/test/test_xmmt_ops.h                      |  16 ++
 config/meson.build                            |   2 +
 config/riscv/meson.build                      | 143 ++++++++++++++++++
 config/riscv/riscv64_linux_gcc                |  17 +++
 config/riscv/riscv64_sifive_u740_linux_gcc    |  19 +++
 doc/guides/contributing/design.rst            |   2 +-
 .../linux_gsg/cross_build_dpdk_for_riscv.rst  | 125 +++++++++++++++
 doc/guides/linux_gsg/index.rst                |   1 +
 doc/guides/nics/features.rst                  |   5 +
 doc/guides/nics/features/default.ini          |   1 +
 doc/guides/rel_notes/release_22_07.rst        |   8 +
 drivers/net/i40e/meson.build                  |   6 +
 drivers/net/ixgbe/meson.build                 |   6 +
 drivers/net/memif/meson.build                 |   5 +
 drivers/net/tap/meson.build                   |   5 +
 examples/l3fwd/meson.build                    |   6 +
 lib/eal/riscv/include/meson.build             |  23 +++
 lib/eal/riscv/include/rte_atomic.h            |  52 +++++++
 lib/eal/riscv/include/rte_byteorder.h         |  44 ++++++
 lib/eal/riscv/include/rte_cpuflags.h          |  55 +++++++
 lib/eal/riscv/include/rte_cycles.h            | 105 +++++++++++++
 lib/eal/riscv/include/rte_io.h                |  21 +++
 lib/eal/riscv/include/rte_mcslock.h           |  18 +++
 lib/eal/riscv/include/rte_memcpy.h            |  63 ++++++++
 lib/eal/riscv/include/rte_pause.h             |  31 ++++
 lib/eal/riscv/include/rte_pflock.h            |  17 +++
 lib/eal/riscv/include/rte_power_intrinsics.h  |  22 +++
 lib/eal/riscv/include/rte_prefetch.h          |  50 ++++++
 lib/eal/riscv/include/rte_rwlock.h            |  44 ++++++
 lib/eal/riscv/include/rte_spinlock.h          |  67 ++++++++
 lib/eal/riscv/include/rte_ticketlock.h        |  21 +++
 lib/eal/riscv/include/rte_vect.h              |  55 +++++++
 lib/eal/riscv/meson.build                     |  11 ++
 lib/eal/riscv/rte_cpuflags.c                  | 122 +++++++++++++++
 lib/eal/riscv/rte_cycles.c                    |  77 ++++++++++
 lib/eal/riscv/rte_hypervisor.c                |  13 ++
 lib/eal/riscv/rte_power_intrinsics.c          |  56 +++++++
 meson.build                                   |   2 +
 39 files changed, 1341 insertions(+), 1 deletion(-)
 create mode 100644 config/riscv/meson.build
 create mode 100644 config/riscv/riscv64_linux_gcc
 create mode 100644 config/riscv/riscv64_sifive_u740_linux_gcc
 create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
 create mode 100644 lib/eal/riscv/include/meson.build
 create mode 100644 lib/eal/riscv/include/rte_atomic.h
 create mode 100644 lib/eal/riscv/include/rte_byteorder.h
 create mode 100644 lib/eal/riscv/include/rte_cpuflags.h
 create mode 100644 lib/eal/riscv/include/rte_cycles.h
 create mode 100644 lib/eal/riscv/include/rte_io.h
 create mode 100644 lib/eal/riscv/include/rte_mcslock.h
 create mode 100644 lib/eal/riscv/include/rte_memcpy.h
 create mode 100644 lib/eal/riscv/include/rte_pause.h
 create mode 100644 lib/eal/riscv/include/rte_pflock.h
 create mode 100644 lib/eal/riscv/include/rte_power_intrinsics.h
 create mode 100644 lib/eal/riscv/include/rte_prefetch.h
 create mode 100644 lib/eal/riscv/include/rte_rwlock.h
 create mode 100644 lib/eal/riscv/include/rte_spinlock.h
 create mode 100644 lib/eal/riscv/include/rte_ticketlock.h
 create mode 100644 lib/eal/riscv/include/rte_vect.h
 create mode 100644 lib/eal/riscv/meson.build
 create mode 100644 lib/eal/riscv/rte_cpuflags.c
 create mode 100644 lib/eal/riscv/rte_cycles.c
 create mode 100644 lib/eal/riscv/rte_hypervisor.c
 create mode 100644 lib/eal/riscv/rte_power_intrinsics.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 7c4f541dba..2c732a1912 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -296,6 +296,12 @@ F: drivers/*/*/*_altivec.*
 F: app/*/*_altivec.*
 F: examples/*/*_altivec.*
 
+RISC-V
+M: Stanislaw Kardach <kda@semihalf.com>
+F: config/riscv/
+F: doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
+F: lib/eal/riscv/
+
 Intel x86
 M: Bruce Richardson <bruce.richardson@intel.com>
 M: Konstantin Ananyev <konstantin.ananyev@intel.com>
diff --git a/app/test/test_xmmt_ops.h b/app/test/test_xmmt_ops.h
index 3a82d5ecac..55f256599e 100644
--- a/app/test/test_xmmt_ops.h
+++ b/app/test/test_xmmt_ops.h
@@ -1,5 +1,8 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  * Copyright(c) 2015 Cavium, Inc
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
  */
 
 #ifndef _TEST_XMMT_OPS_H_
@@ -49,6 +52,19 @@ vect_set_epi32(int i3, int i2, int i1, int i0)
 	return data;
 }
 
+#elif defined(RTE_ARCH_RISCV)
+
+#define vect_loadu_sil128(p) vect_load_128(p)
+
+/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */
+static __rte_always_inline xmm_t
+vect_set_epi32(int i3, int i2, int i1, int i0)
+{
+	xmm_t data = (xmm_t){i0, i1, i2, i3};
+
+	return data;
+}
+
 #endif
 
 #endif /* _TEST_XMMT_OPS_H_ */
diff --git a/config/meson.build b/config/meson.build
index 7134e80e8d..7f7b6c92fd 100644
--- a/config/meson.build
+++ b/config/meson.build
@@ -121,6 +121,8 @@ if cpu_instruction_set == 'generic'
         cpu_instruction_set = 'generic'
     elif host_machine.cpu_family().startswith('ppc')
         cpu_instruction_set = 'power8'
+    elif host_machine.cpu_family().startswith('riscv')
+        cpu_instruction_set = 'riscv'
     endif
 endif
 
diff --git a/config/riscv/meson.build b/config/riscv/meson.build
new file mode 100644
index 0000000000..0c16c31fc2
--- /dev/null
+++ b/config/riscv/meson.build
@@ -0,0 +1,143 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2017 Intel Corporation.
+# Copyright(c) 2017 Cavium, Inc
+# Copyright(c) 2021 PANTHEON.tech s.r.o.
+# Copyright(c) 2022 StarFive
+# Copyright(c) 2022 SiFive
+# Copyright(c) 2022 Semihalf
+
+if not is_linux
+    error('Only Linux is supported at this point in time.')
+endif
+
+if not dpdk_conf.get('RTE_ARCH_64')
+    error('Only 64-bit compiles are supported for this platform type')
+endif
+
+dpdk_conf.set('RTE_ARCH', 'riscv')
+dpdk_conf.set('RTE_ARCH_RISCV', 1)
+dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
+
+# common flags to all riscv builds, with lowest priority
+flags_common = [
+    ['RTE_ARCH_RISCV', true],
+    ['RTE_CACHE_LINE_SIZE', 64],
+    # Set this to true if target emulates U-mode TIME CSR via M or S mode trap.
+    # This allows to remove a FENCE on rte_rdtsc_precise() as trap effectively
+    # acts as one.
+    ['RTE_RISCV_EMU_UTIME', false],
+    # Set this to true if target emulates U-mode CYCLE CSR via M or S mode trap.
+    # This allows to remove a FENCE on rte_rdtsc_precise() as trap effectively
+    # acts as one.
+    ['RTE_RISCV_EMU_UCYCLE', false],
+    # Manually set wall time clock frequency for the target. If 0, then it is
+    # read from /proc/device-tree/cpus/timebase-frequency. This property is
+    # guaranteed on Linux, as riscv time_init() requires it.
+    ['RTE_RISCV_TIME_FREQ', 0],
+]
+
+## SoC-specific options.
+# The priority is like this: arch > vendor > common.
+#
+# Note that currently there's no way of getting vendor/microarchitecture id
+# values in userspace which is why the logic of choosing the right flag
+# combination is strictly based on the values passed from a cross-file.
+vendor_generic = {
+    'description': 'Generic RISC-V',
+    'flags': [
+        ['RTE_MACHINE', '"riscv"'],
+        ['RTE_USE_C11_MEM_MODEL', true],
+        ['RTE_MAX_LCORE', 128],
+        ['RTE_MAX_NUMA_NODES', 2]
+    ],
+    'arch_config': {
+        'generic': {'machine_args': ['-march=rv64gc']}
+    }
+}
+
+arch_config_riscv = {
+    '0x8000000000000007': {
+        'machine_args':  ['-march=rv64gc', '-mtune=sifive-7-series'],
+        'flags': [
+            ['RTE_RISCV_EMU_UTIME', true],
+            ['RTE_RISCV_EMU_UCYCLE', true]
+        ]
+    },
+}
+
+vendor_sifive = {
+    'description': 'SiFive',
+    'flags': [
+        ['RTE_MACHINE', '"riscv"'],
+        ['RTE_USE_C11_MEM_MODEL', true],
+        ['RTE_MAX_LCORE', 4],
+        ['RTE_MAX_NUMA_NODES', 1],
+    ],
+    'arch_config': arch_config_riscv
+}
+
+vendors = {
+    'generic': vendor_generic,
+    '0x489': vendor_sifive
+}
+
+# Native/cross vendor/arch detection
+if not meson.is_cross_build()
+    if machine == 'default'
+        # default build
+        vendor_id = 'generic'
+        arch_id = 'generic'
+        message('generic RISC-V')
+    else
+        vendor_id = 'generic'
+        arch_id = 'generic'
+        warning('RISC-V arch discovery not available, using generic!')
+    endif
+else
+    # cross build
+    vendor_id = meson.get_cross_property('vendor_id')
+    arch_id = meson.get_cross_property('arch_id')
+endif
+
+if vendors.has_key(vendor_id)
+    vendor_config = vendors[vendor_id]
+else
+    error('Unsupported RISC-V vendor: @0@. '.format(vendor_id) +
+        'Please add support for it or use the generic ' +
+        '(-Dmachine=generic) build.')
+endif
+
+message('RISC-V vendor: ' + vendor_config['description'])
+message('RISC-V architecture id: ' + arch_id)
+
+arch_config = vendor_config['arch_config']
+if arch_config.has_key(arch_id)
+    # use the specified arch_id machine args if found
+    arch_config = arch_config[arch_id]
+else
+    # unknown micro-architecture id
+    error('Unsupported architecture @0@ of vendor @1@. '
+        .format(arch_id, vendor_id) +
+        'Please add support for it or use the generic ' +
+        '(-Dmachine=generic) build.')
+endif
+
+# Concatenate flags respecting priorities.
+dpdk_flags = flags_common + vendor_config['flags'] + arch_config.get('flags', [])
+
+# apply supported machine args
+machine_args = [] # Clear previous machine args
+foreach flag: arch_config['machine_args']
+    if cc.has_argument(flag)
+        machine_args += flag
+    endif
+endforeach
+
+# apply flags
+foreach flag: dpdk_flags
+    if flag.length() > 0
+        dpdk_conf.set(flag[0], flag[1])
+    endif
+endforeach
+message('Using machine args: @0@'.format(machine_args))
+
diff --git a/config/riscv/riscv64_linux_gcc b/config/riscv/riscv64_linux_gcc
new file mode 100644
index 0000000000..04248d7ecb
--- /dev/null
+++ b/config/riscv/riscv64_linux_gcc
@@ -0,0 +1,17 @@
+[binaries]
+c = 'riscv64-linux-gnu-gcc'
+cpp = 'riscv64-linux-gnu-g++'
+ar = 'riscv64-linux-gnu-ar'
+strip = 'riscv64-linux-gnu-strip'
+pcap-config = ''
+pkgconfig = 'riscv64-linux-gnu-pkg-config'
+
+[host_machine]
+system = 'linux'
+cpu_family = 'riscv64'
+cpu = 'rv64gc'
+endian = 'little'
+
+[properties]
+vendor_id = 'generic'
+arch_id = 'generic'
diff --git a/config/riscv/riscv64_sifive_u740_linux_gcc b/config/riscv/riscv64_sifive_u740_linux_gcc
new file mode 100644
index 0000000000..7b5ad2562d
--- /dev/null
+++ b/config/riscv/riscv64_sifive_u740_linux_gcc
@@ -0,0 +1,19 @@
+[binaries]
+c = 'riscv64-unknown-linux-gnu-gcc'
+cpp = 'riscv64-unknown-linux-gnu-g++'
+ar = 'riscv64-unknown-linux-gnu-ar'
+strip = 'riscv64-unknown-linux-gnu-strip'
+pcap-config = ''
+pkgconfig = 'riscv64-unknown-linux-gnu-pkg-config'
+
+[host_machine]
+system = 'linux'
+cpu_family = 'riscv64'
+cpu = 'rv64gc'
+endian = 'little'
+
+[properties]
+vendor_id = '0x489'
+arch_id = '0x8000000000000007'
+max_lcores = 4
+max_numa_nodes = 1
diff --git a/doc/guides/contributing/design.rst b/doc/guides/contributing/design.rst
index d5ca8b4d9c..0383afe5c8 100644
--- a/doc/guides/contributing/design.rst
+++ b/doc/guides/contributing/design.rst
@@ -42,7 +42,7 @@ Per Architecture Sources
 The following macro options can be used:
 
 * ``RTE_ARCH`` is a string that contains the name of the architecture.
-* ``RTE_ARCH_I686``, ``RTE_ARCH_X86_64``, ``RTE_ARCH_X86_X32``, ``RTE_ARCH_PPC_64``, ``RTE_ARCH_ARM``, ``RTE_ARCH_ARMv7`` or ``RTE_ARCH_ARM64`` are defined only if we are building for those architectures.
+* ``RTE_ARCH_I686``, ``RTE_ARCH_X86_64``, ``RTE_ARCH_X86_X32``, ``RTE_ARCH_PPC_64``, ``RTE_ARCH_RISCV``, ``RTE_ARCH_ARM``, ``RTE_ARCH_ARMv7`` or ``RTE_ARCH_ARM64`` are defined only if we are building for those architectures.
 
 Per Execution Environment Sources
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst b/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
new file mode 100644
index 0000000000..9907b35a1d
--- /dev/null
+++ b/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
@@ -0,0 +1,125 @@
+..  SPDX-License-Identifier: BSD-3-Clause
+    Copyright(c) 2020 ARM Corporation.
+    Copyright(c) 2022 StarFive
+    Copyright(c) 2022 SiFive
+    Copyright(c) 2022 Semihalf
+
+Cross compiling DPDK for RISC-V
+===============================
+
+This chapter describes how to cross compile DPDK for RISC-V from x86 build
+hosts.
+
+.. note::
+
+   While it's possible to compile DPDK natively on a RISC-V host, it is
+   currently recommended to cross-compile as Linux kernel does not offer any
+   way for userspace to discover the vendor and architecture identifiers of the
+   CPU and therefore any per-chip optimization options have to be chosen via
+   a cross-file or ``c_args``.
+
+
+Prerequisites
+-------------
+
+
+Linux kernel
+~~~~~~~~~~~~
+
+It is recommended to use Linux kernel built from
+`SiFive Freedom Unleashed SDK <https://github.com/sifive/freedom-u-sdk>`_.
+
+
+Meson prerequisites
+~~~~~~~~~~~~~~~~~~~
+
+Meson depends on pkgconfig to find the dependencies.
+The package ``pkg-config-riscv64-linux-gnu`` is required for RISC-V.
+To install it in Ubuntu::
+
+   sudo apt install pkg-config-riscv64-linux-gnu
+
+
+GNU toolchain
+-------------
+
+
+Obtain the cross toolchain
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The build process was tested using:
+
+* Ubuntu toolchain (the ``crossbuild-essential-riscv64`` package).
+
+* Latest `RISC-V GNU toolchain
+  <https://github.com/riscv/riscv-gnu-toolchain/releases>`_ on Ubuntu or Arch
+  Linux.
+
+Alternatively the toolchain may be built straight from the source, to do that
+follow the instructions on the riscv-gnu-toolchain github page.
+
+
+Unzip and add into the PATH
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+This step is only required for the riscv-gnu-toolchain. The Ubuntu toolchain is
+in the PATH already.
+
+.. code-block:: console
+
+   tar -xvf riscv64-glibc-ubuntu-20.04-<version>.tar.gz
+   export PATH=$PATH:<cross_install_dir>/riscv/bin
+
+
+Cross Compiling DPDK with GNU toolchain using Meson
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+To cross-compile DPDK for a desired target machine use the following command::
+
+   meson cross-build --cross-file <target_machine_configuration>
+   ninja -C cross-build
+
+For example if the target machine is a generic rv64gc RISC-V, use the following
+command::
+
+   meson riscv64-build-gcc --cross-file config/riscv/riscv64_linux_gcc
+   ninja -C riscv64-build-gcc
+
+If riscv-gnu-toolchain is used, binary names should be updated to match. Update the following lines in the cross-file:
+
+.. code-block:: console
+
+   [binaries]
+   c = 'riscv64-unknown-linux-gnu-gcc'
+   cpp = 'riscv64-unknown-linux-gnu-g++'
+   ar = 'riscv64-unknown-linux-gnu-ar'
+   strip = 'riscv64-unknown-linux-gnu-strip'
+   ...
+
+Some toolchains (such as freedom-u-sdk one) require also setting ``--sysroot``,
+otherwise include paths might not be resolved. To do so, add the appropriate
+paths to the cross-file:
+
+.. code-block:: console
+
+   [properties]
+   ...
+   c_args = ['--sysroot', '<path/to/toolchain/sysroot>']
+   cpp_args = c_args
+   c_link_args = ['--sysroot', '<path/to/toolchain/sysroot>']
+   cpp_link_args = c_link_args
+   ...
+
+
+Supported cross-compilation targets
+-----------------------------------
+
+Currently the following targets are supported:
+
+* Generic rv64gc ISA: ``config/riscv/riscv64_linux_gcc``
+
+* SiFive U740 SoC: ``config/riscv/riscv64_sifive_u740_linux_gcc``
+
+To add a new target support, ``config/riscv/meson.build`` has to be modified by
+adding a new vendor/architecture id and a corresponding cross-file has to be
+added to ``config/riscv`` directory.
diff --git a/doc/guides/linux_gsg/index.rst b/doc/guides/linux_gsg/index.rst
index 16a9a67260..747552c385 100644
--- a/doc/guides/linux_gsg/index.rst
+++ b/doc/guides/linux_gsg/index.rst
@@ -14,6 +14,7 @@ Getting Started Guide for Linux
     sys_reqs
     build_dpdk
     cross_build_dpdk_for_arm64
+    cross_build_dpdk_for_riscv
     linux_drivers
     build_sample_apps
     linux_eal_parameters
diff --git a/doc/guides/nics/features.rst b/doc/guides/nics/features.rst
index 21bedb743f..6c4fa74bc7 100644
--- a/doc/guides/nics/features.rst
+++ b/doc/guides/nics/features.rst
@@ -855,6 +855,11 @@ x86-64
 
 Support 64bits x86 architecture.
 
+rv64
+----
+
+Support 64-bit RISC-V architecture.
+
 
 .. _nic_features_usage_doc:
 
diff --git a/doc/guides/nics/features/default.ini b/doc/guides/nics/features/default.ini
index b1d18ac62c..02198682c6 100644
--- a/doc/guides/nics/features/default.ini
+++ b/doc/guides/nics/features/default.ini
@@ -74,6 +74,7 @@ ARMv8                =
 Power8               =
 x86-32               =
 x86-64               =
+rv64                 =
 Usage doc            =
 Design doc           =
 Perf doc             =
diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst
index 73e8d632f2..e435e29f55 100644
--- a/doc/guides/rel_notes/release_22_07.rst
+++ b/doc/guides/rel_notes/release_22_07.rst
@@ -55,6 +55,14 @@ New Features
      Also, make sure to start the actual text at the margin.
      =======================================================
 
+* **Added initial RISC-V architecture support.***
+
+  Added EAL implementation for RISC-V architecture. The initial device the
+  porting was tested on is a HiFive Unmatched development board based on the
+  SiFive Freedom U740 SoC. In theory this implementation should work with any
+  ``rv64gc`` ISA compatible implementation with MMU supporting a reasonable
+  address space size (U740 uses sv39 MMU).
+
 * **Updated Intel iavf driver.**
 
   * Added Tx QoS queue rate limitation support.
diff --git a/drivers/net/i40e/meson.build b/drivers/net/i40e/meson.build
index efc5f93e35..a4c1c9079a 100644
--- a/drivers/net/i40e/meson.build
+++ b/drivers/net/i40e/meson.build
@@ -1,6 +1,12 @@
 # SPDX-License-Identifier: BSD-3-Clause
 # Copyright(c) 2017 Intel Corporation
 
+if arch_subdir == 'riscv'
+		build = false
+		reason = 'riscv arch not supported'
+		subdir_done()
+endif
+
 cflags += ['-DPF_DRIVER',
     '-DVF_DRIVER',
     '-DINTEGRATED_VF',
diff --git a/drivers/net/ixgbe/meson.build b/drivers/net/ixgbe/meson.build
index 162f8d5f46..88539e97d5 100644
--- a/drivers/net/ixgbe/meson.build
+++ b/drivers/net/ixgbe/meson.build
@@ -1,6 +1,12 @@
 # SPDX-License-Identifier: BSD-3-Clause
 # Copyright(c) 2017 Intel Corporation
 
+if arch_subdir == 'riscv'
+		build = false
+		reason = 'riscv arch not supported'
+		subdir_done()
+endif
+
 cflags += ['-DRTE_LIBRTE_IXGBE_BYPASS']
 
 subdir('base')
diff --git a/drivers/net/memif/meson.build b/drivers/net/memif/meson.build
index 680bc8631c..9afb495953 100644
--- a/drivers/net/memif/meson.build
+++ b/drivers/net/memif/meson.build
@@ -5,6 +5,11 @@ if not is_linux
     build = false
     reason = 'only supported on Linux'
 endif
+if arch_subdir == 'riscv'
+		build = false
+		reason = 'riscv arch not supported'
+		subdir_done()
+endif
 
 sources = files(
         'memif_socket.c',
diff --git a/drivers/net/tap/meson.build b/drivers/net/tap/meson.build
index c09713a67b..3efac9ac07 100644
--- a/drivers/net/tap/meson.build
+++ b/drivers/net/tap/meson.build
@@ -5,6 +5,11 @@ if not is_linux
     build = false
     reason = 'only supported on Linux'
 endif
+if arch_subdir == 'riscv'
+		build = false
+		reason = 'riscv arch not supported'
+		subdir_done()
+endif
 sources = files(
         'rte_eth_tap.c',
         'tap_bpf_api.c',
diff --git a/examples/l3fwd/meson.build b/examples/l3fwd/meson.build
index 0830b3eb31..75fa19b7fe 100644
--- a/examples/l3fwd/meson.build
+++ b/examples/l3fwd/meson.build
@@ -6,6 +6,12 @@
 # To build this example as a standalone application with an already-installed
 # DPDK instance, use 'make'
 
+if dpdk_conf.has('RTE_ARCH_RISCV')
+		build = false
+		reason = 'riscv arch not supported'
+		subdir_done()
+endif
+
 allow_experimental_apis = true
 deps += ['hash', 'lpm', 'fib', 'eventdev']
 sources = files(
diff --git a/lib/eal/riscv/include/meson.build b/lib/eal/riscv/include/meson.build
new file mode 100644
index 0000000000..7f6e4a5b1e
--- /dev/null
+++ b/lib/eal/riscv/include/meson.build
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2022 StarFive
+# Copyright(c) 2022 SiFive
+# Copyright(c) 2022 Semihalf
+
+arch_headers = files(
+        'rte_atomic.h',
+        'rte_byteorder.h',
+        'rte_cpuflags.h',
+        'rte_cycles.h',
+        'rte_io.h',
+        'rte_mcslock.h',
+        'rte_memcpy.h',
+        'rte_pause.h',
+        'rte_pflock.h',
+        'rte_power_intrinsics.h',
+        'rte_prefetch.h',
+        'rte_rwlock.h',
+        'rte_spinlock.h',
+        'rte_ticketlock.h',
+        'rte_vect.h',
+)
+install_headers(arch_headers, subdir: get_option('include_subdir_arch'))
diff --git a/lib/eal/riscv/include/rte_atomic.h b/lib/eal/riscv/include/rte_atomic.h
new file mode 100644
index 0000000000..4b4633c914
--- /dev/null
+++ b/lib/eal/riscv/include/rte_atomic.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ * All rights reserved.
+ */
+
+#ifndef RTE_ATOMIC_RISCV_H
+#define RTE_ATOMIC_RISCV_H
+
+#ifndef RTE_FORCE_INTRINSICS
+#  error Platform must be built with RTE_FORCE_INTRINSICS
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <rte_common.h>
+#include <rte_config.h>
+#include "generic/rte_atomic.h"
+
+#define rte_mb()	asm volatile("fence rw, rw" : : : "memory")
+
+#define rte_wmb()	asm volatile("fence w, w" : : : "memory")
+
+#define rte_rmb()	asm volatile("fence r, r" : : : "memory")
+
+#define rte_smp_mb()	rte_mb()
+
+#define rte_smp_wmb()	rte_wmb()
+
+#define rte_smp_rmb()	rte_rmb()
+
+#define rte_io_mb()	asm volatile("fence iorw, iorw" : : : "memory")
+
+#define rte_io_wmb()	asm volatile("fence orw, ow" : : : "memory")
+
+#define rte_io_rmb()	asm volatile("fence ir, ir" : : : "memory")
+
+static __rte_always_inline void
+rte_atomic_thread_fence(int memorder)
+{
+	__atomic_thread_fence(memorder);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_ATOMIC_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_byteorder.h b/lib/eal/riscv/include/rte_byteorder.h
new file mode 100644
index 0000000000..21893505d6
--- /dev/null
+++ b/lib/eal/riscv/include/rte_byteorder.h
@@ -0,0 +1,44 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Inspired from FreeBSD src/sys/powerpc/include/endian.h
+ * Copyright(c) 1987, 1991, 1993
+ * The Regents of the University of California.  All rights reserved.
+ */
+
+#ifndef RTE_BYTEORDER_RISCV_H
+#define RTE_BYTEORDER_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <rte_common.h>
+#include "generic/rte_byteorder.h"
+
+#ifndef RTE_BYTE_ORDER
+#define RTE_BYTE_ORDER RTE_LITTLE_ENDIAN
+#endif
+
+#define rte_cpu_to_le_16(x) (x)
+#define rte_cpu_to_le_32(x) (x)
+#define rte_cpu_to_le_64(x) (x)
+
+#define rte_cpu_to_be_16(x) rte_bswap16(x)
+#define rte_cpu_to_be_32(x) rte_bswap32(x)
+#define rte_cpu_to_be_64(x) rte_bswap64(x)
+
+#define rte_le_to_cpu_16(x) (x)
+#define rte_le_to_cpu_32(x) (x)
+#define rte_le_to_cpu_64(x) (x)
+
+#define rte_be_to_cpu_16(x) rte_bswap16(x)
+#define rte_be_to_cpu_32(x) rte_bswap32(x)
+#define rte_be_to_cpu_64(x) rte_bswap64(x)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_BYTEORDER_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_cpuflags.h b/lib/eal/riscv/include/rte_cpuflags.h
new file mode 100644
index 0000000000..66e787f898
--- /dev/null
+++ b/lib/eal/riscv/include/rte_cpuflags.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014 IBM Corporation
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_CPUFLAGS_RISCV_H
+#define RTE_CPUFLAGS_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Enumeration of all CPU features supported
+ */
+enum rte_cpu_flag_t {
+	RTE_CPUFLAG_RISCV_ISA_A, /* Atomic */
+	RTE_CPUFLAG_RISCV_ISA_B, /* Bit-Manipulation */
+	RTE_CPUFLAG_RISCV_ISA_C, /* Compressed instruction */
+	RTE_CPUFLAG_RISCV_ISA_D, /* Double precision floating-point  */
+	RTE_CPUFLAG_RISCV_ISA_E, /* RV32E ISA */
+	RTE_CPUFLAG_RISCV_ISA_F, /* Single precision floating-point */
+	RTE_CPUFLAG_RISCV_ISA_G, /* Extension pack (IMAFD, Zicsr, Zifencei) */
+	RTE_CPUFLAG_RISCV_ISA_H, /* Hypervisor */
+	RTE_CPUFLAG_RISCV_ISA_I, /* RV32I/RV64I/IRV128I base ISA */
+	RTE_CPUFLAG_RISCV_ISA_J, /* Dynamic Translation Language */
+	RTE_CPUFLAG_RISCV_ISA_K, /* Reserved */
+	RTE_CPUFLAG_RISCV_ISA_L, /* Decimal Floating-Point */
+	RTE_CPUFLAG_RISCV_ISA_M, /* Integer Multiply/Divide */
+	RTE_CPUFLAG_RISCV_ISA_N, /* User-level interrupts */
+	RTE_CPUFLAG_RISCV_ISA_O, /* Reserved */
+	RTE_CPUFLAG_RISCV_ISA_P, /* Packed-SIMD */
+	RTE_CPUFLAG_RISCV_ISA_Q, /* Quad-precision floating-points */
+	RTE_CPUFLAG_RISCV_ISA_R, /* Reserved */
+	RTE_CPUFLAG_RISCV_ISA_S, /* Supervisor mode */
+	RTE_CPUFLAG_RISCV_ISA_T, /* Transactional memory */
+	RTE_CPUFLAG_RISCV_ISA_U, /* User mode */
+	RTE_CPUFLAG_RISCV_ISA_V, /* Vector */
+	RTE_CPUFLAG_RISCV_ISA_W, /* Reserved */
+	RTE_CPUFLAG_RISCV_ISA_X, /* Non-standard extension present */
+	RTE_CPUFLAG_RISCV_ISA_Y, /* Reserved */
+	RTE_CPUFLAG_RISCV_ISA_Z, /* Reserved */
+	/* The last item */
+	RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */
+};
+
+#include "generic/rte_cpuflags.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_CPUFLAGS_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_cycles.h b/lib/eal/riscv/include/rte_cycles.h
new file mode 100644
index 0000000000..8353cea853
--- /dev/null
+++ b/lib/eal/riscv/include/rte_cycles.h
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015 Cavium, Inc
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_CYCLES_RISCV_H
+#define RTE_CYCLES_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_cycles.h"
+
+#ifndef RTE_RISCV_RDTSC_USE_HPM
+#define RTE_RISCV_RDTSC_USE_HPM 0
+#endif
+
+#define RV64_CSRR(reg, value) \
+	asm volatile("csrr %0, " #reg : "=r" (value) : : "memory")
+
+/** Read wall time counter */
+static __rte_always_inline uint64_t
+__rte_riscv_rdtime(void)
+{
+	uint64_t tsc;
+	RV64_CSRR(time, tsc);
+	return tsc;
+}
+
+/** Read wall time counter ensuring no re-ordering */
+static __rte_always_inline uint64_t
+__rte_riscv_rdtime_precise(void)
+{
+#if !defined(RTE_RISCV_EMU_UTIME)
+	asm volatile("fence" : : : "memory");
+#endif
+	return __rte_riscv_rdtime();
+}
+
+/** Read hart cycle counter */
+static __rte_always_inline uint64_t
+__rte_riscv_rdcycle(void)
+{
+	uint64_t tsc;
+	RV64_CSRR(cycle, tsc);
+	return tsc;
+}
+
+/** Read hart cycle counter ensuring no re-ordering */
+static __rte_always_inline uint64_t
+__rte_riscv_rdcycle_precise(void)
+{
+#if !defined(RTE_RISCV_EMU_UCYCLE)
+	asm volatile("fence" : : : "memory");
+#endif
+	return __rte_riscv_rdcycle();
+}
+
+/**
+ * Read the time base register.
+ *
+ * @return
+ *   The time base for this lcore.
+ */
+static __rte_always_inline uint64_t
+rte_rdtsc(void)
+{
+	/**
+	 * By default TIME userspace counter is used. Although it's frequency
+	 * may not be enough for all applications.
+	 */
+	if (!RTE_RISCV_RDTSC_USE_HPM)
+		return __rte_riscv_rdtime();
+	/**
+	 * Alternatively HPM's CYCLE counter may be used. However this counter
+	 * is not guaranteed by ISA to either be stable frequency or always
+	 * enabled for userspace access (it may trap to kernel or firmware).
+	 */
+	return __rte_riscv_rdcycle();
+}
+
+static inline uint64_t
+rte_rdtsc_precise(void)
+{
+	if (!RTE_RISCV_RDTSC_USE_HPM)
+		return __rte_riscv_rdtime_precise();
+	return __rte_riscv_rdcycle_precise();
+}
+
+static __rte_always_inline uint64_t
+rte_get_tsc_cycles(void)
+{
+	return rte_rdtsc();
+}
+
+#undef RV64_CSRR
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_CYCLES_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_io.h b/lib/eal/riscv/include/rte_io.h
new file mode 100644
index 0000000000..29659c9590
--- /dev/null
+++ b/lib/eal/riscv/include/rte_io.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2016 Cavium, Inc
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_IO_RISCV_H
+#define RTE_IO_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_io.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_IO_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_mcslock.h b/lib/eal/riscv/include/rte_mcslock.h
new file mode 100644
index 0000000000..b517cd5fc5
--- /dev/null
+++ b/lib/eal/riscv/include/rte_mcslock.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Arm Limited
+ */
+
+#ifndef RTE_MCSLOCK_RISCV_H
+#define RTE_MCSLOCK_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_mcslock.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_MCSLOCK_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_memcpy.h b/lib/eal/riscv/include/rte_memcpy.h
new file mode 100644
index 0000000000..e34f19396e
--- /dev/null
+++ b/lib/eal/riscv/include/rte_memcpy.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_MEMCPY_RISCV_H
+#define RTE_MEMCPY_RISCV_H
+
+#include <stdint.h>
+#include <string.h>
+
+#include "rte_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_memcpy.h"
+
+static inline void
+rte_mov16(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 16);
+}
+
+static inline void
+rte_mov32(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 32);
+}
+
+static inline void
+rte_mov48(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 48);
+}
+
+static inline void
+rte_mov64(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 64);
+}
+
+static inline void
+rte_mov128(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 128);
+}
+
+static inline void
+rte_mov256(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 256);
+}
+
+#define rte_memcpy(d, s, n)	memcpy((d), (s), (n))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_MEMCPY_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_pause.h b/lib/eal/riscv/include/rte_pause.h
new file mode 100644
index 0000000000..c24c1f32e8
--- /dev/null
+++ b/lib/eal/riscv/include/rte_pause.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_PAUSE_RISCV_H
+#define RTE_PAUSE_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "rte_atomic.h"
+
+#include "generic/rte_pause.h"
+
+static inline void rte_pause(void)
+{
+	/* Insert pause hint directly to be compatible with old compilers.
+	 * This will work even on platforms without Zihintpause extension
+	 * because this is a FENCE hint instruction which evaluates to NOP then.
+	 */
+	asm volatile(".int 0x0100000F"::: "memory");
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_PAUSE_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_pflock.h b/lib/eal/riscv/include/rte_pflock.h
new file mode 100644
index 0000000000..ce6ca02aca
--- /dev/null
+++ b/lib/eal/riscv/include/rte_pflock.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021 Microsoft Corporation
+ */
+#ifndef RTE_PFLOCK_RISCV_H
+#define RTE_PFLOCK_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_pflock.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_PFLOCK_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_power_intrinsics.h b/lib/eal/riscv/include/rte_power_intrinsics.h
new file mode 100644
index 0000000000..636e58e71f
--- /dev/null
+++ b/lib/eal/riscv/include/rte_power_intrinsics.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_POWER_INTRINSIC_RISCV_H
+#define RTE_POWER_INTRINSIC_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_common.h>
+
+#include "generic/rte_power_intrinsics.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_POWER_INTRINSIC_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_prefetch.h b/lib/eal/riscv/include/rte_prefetch.h
new file mode 100644
index 0000000000..966d9e2687
--- /dev/null
+++ b/lib/eal/riscv/include/rte_prefetch.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014 IBM Corporation
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_PREFETCH_RISCV_H
+#define RTE_PREFETCH_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_common.h>
+#include "generic/rte_prefetch.h"
+
+static inline void rte_prefetch0(const volatile void *p)
+{
+	RTE_SET_USED(p);
+}
+
+static inline void rte_prefetch1(const volatile void *p)
+{
+	RTE_SET_USED(p);
+}
+
+static inline void rte_prefetch2(const volatile void *p)
+{
+	RTE_SET_USED(p);
+}
+
+static inline void rte_prefetch_non_temporal(const volatile void *p)
+{
+	/* non-temporal version not available, fallback to rte_prefetch0 */
+	rte_prefetch0(p);
+}
+
+__rte_experimental
+static inline void
+rte_cldemote(const volatile void *p)
+{
+	RTE_SET_USED(p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_PREFETCH_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_rwlock.h b/lib/eal/riscv/include/rte_rwlock.h
new file mode 100644
index 0000000000..9cdaf1b0ef
--- /dev/null
+++ b/lib/eal/riscv/include/rte_rwlock.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_RWLOCK_RISCV_H
+#define RTE_RWLOCK_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_rwlock.h"
+
+static inline void
+rte_rwlock_read_lock_tm(rte_rwlock_t *rwl)
+{
+	rte_rwlock_read_lock(rwl);
+}
+
+static inline void
+rte_rwlock_read_unlock_tm(rte_rwlock_t *rwl)
+{
+	rte_rwlock_read_unlock(rwl);
+}
+
+static inline void
+rte_rwlock_write_lock_tm(rte_rwlock_t *rwl)
+{
+	rte_rwlock_write_lock(rwl);
+}
+
+static inline void
+rte_rwlock_write_unlock_tm(rte_rwlock_t *rwl)
+{
+	rte_rwlock_write_unlock(rwl);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_RWLOCK_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_spinlock.h b/lib/eal/riscv/include/rte_spinlock.h
new file mode 100644
index 0000000000..6af430735c
--- /dev/null
+++ b/lib/eal/riscv/include/rte_spinlock.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015 RehiveTech. All rights reserved.
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_SPINLOCK_RISCV_H
+#define RTE_SPINLOCK_RISCV_H
+
+#ifndef RTE_FORCE_INTRINSICS
+#  error Platform must be built with RTE_FORCE_INTRINSICS
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_common.h>
+#include "generic/rte_spinlock.h"
+
+static inline int rte_tm_supported(void)
+{
+	return 0;
+}
+
+static inline void
+rte_spinlock_lock_tm(rte_spinlock_t *sl)
+{
+	rte_spinlock_lock(sl); /* fall-back */
+}
+
+static inline int
+rte_spinlock_trylock_tm(rte_spinlock_t *sl)
+{
+	return rte_spinlock_trylock(sl);
+}
+
+static inline void
+rte_spinlock_unlock_tm(rte_spinlock_t *sl)
+{
+	rte_spinlock_unlock(sl);
+}
+
+static inline void
+rte_spinlock_recursive_lock_tm(rte_spinlock_recursive_t *slr)
+{
+	rte_spinlock_recursive_lock(slr); /* fall-back */
+}
+
+static inline void
+rte_spinlock_recursive_unlock_tm(rte_spinlock_recursive_t *slr)
+{
+	rte_spinlock_recursive_unlock(slr);
+}
+
+static inline int
+rte_spinlock_recursive_trylock_tm(rte_spinlock_recursive_t *slr)
+{
+	return rte_spinlock_recursive_trylock(slr);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_SPINLOCK_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_ticketlock.h b/lib/eal/riscv/include/rte_ticketlock.h
new file mode 100644
index 0000000000..b8d2a4f937
--- /dev/null
+++ b/lib/eal/riscv/include/rte_ticketlock.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Arm Limited
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_TICKETLOCK_RISCV_H
+#define RTE_TICKETLOCK_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_ticketlock.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_TICKETLOCK_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_vect.h b/lib/eal/riscv/include/rte_vect.h
new file mode 100644
index 0000000000..4600521c20
--- /dev/null
+++ b/lib/eal/riscv/include/rte_vect.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_VECT_RISCV_H
+#define RTE_VECT_RISCV_H
+
+#include <stdint.h>
+#include "generic/rte_vect.h"
+#include "rte_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RTE_VECT_DEFAULT_SIMD_BITWIDTH RTE_VECT_SIMD_DISABLED
+
+typedef int32_t		xmm_t __attribute__((vector_size(16)));
+
+#define XMM_SIZE	(sizeof(xmm_t))
+#define XMM_MASK	(XMM_SIZE - 1)
+
+typedef union rte_xmm {
+	xmm_t		x;
+	uint8_t		u8[XMM_SIZE / sizeof(uint8_t)];
+	uint16_t	u16[XMM_SIZE / sizeof(uint16_t)];
+	uint32_t	u32[XMM_SIZE / sizeof(uint32_t)];
+	uint64_t	u64[XMM_SIZE / sizeof(uint64_t)];
+	double		pd[XMM_SIZE / sizeof(double)];
+} __rte_aligned(8) rte_xmm_t;
+
+static inline xmm_t
+vect_load_128(void *p)
+{
+	xmm_t ret = *((xmm_t *)p);
+	return ret;
+}
+
+static inline xmm_t
+vect_and(xmm_t data, xmm_t mask)
+{
+	rte_xmm_t ret = (rte_xmm_t)data;
+	rte_xmm_t m = (rte_xmm_t)mask;
+	ret.u64[0] &= m.u64[0];
+	ret.u64[1] &= m.u64[1];
+	return ret.x;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_VECT_RISCV_H */
diff --git a/lib/eal/riscv/meson.build b/lib/eal/riscv/meson.build
new file mode 100644
index 0000000000..dca1106aae
--- /dev/null
+++ b/lib/eal/riscv/meson.build
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2017 Intel Corporation.
+
+subdir('include')
+
+sources += files(
+        'rte_cpuflags.c',
+        'rte_cycles.c',
+        'rte_hypervisor.c',
+        'rte_power_intrinsics.c',
+)
diff --git a/lib/eal/riscv/rte_cpuflags.c b/lib/eal/riscv/rte_cpuflags.c
new file mode 100644
index 0000000000..4f6d29b947
--- /dev/null
+++ b/lib/eal/riscv/rte_cpuflags.c
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#include "rte_cpuflags.h"
+
+#include <elf.h>
+#include <fcntl.h>
+#include <assert.h>
+#include <unistd.h>
+#include <string.h>
+
+#ifndef AT_HWCAP
+#define AT_HWCAP 16
+#endif
+
+#ifndef AT_HWCAP2
+#define AT_HWCAP2 26
+#endif
+
+#ifndef AT_PLATFORM
+#define AT_PLATFORM 15
+#endif
+
+enum cpu_register_t {
+	REG_NONE = 0,
+	REG_HWCAP,
+	REG_HWCAP2,
+	REG_PLATFORM,
+	REG_MAX
+};
+
+typedef uint32_t hwcap_registers_t[REG_MAX];
+
+/**
+ * Struct to hold a processor feature entry
+ */
+struct feature_entry {
+	uint32_t reg;
+	uint32_t bit;
+#define CPU_FLAG_NAME_MAX_LEN 64
+	char name[CPU_FLAG_NAME_MAX_LEN];
+};
+
+#define FEAT_DEF(name, reg, bit) \
+	[RTE_CPUFLAG_##name] = {reg, bit, #name},
+
+typedef Elf64_auxv_t _Elfx_auxv_t;
+
+const struct feature_entry rte_cpu_feature_table[] = {
+	FEAT_DEF(RISCV_ISA_A, REG_HWCAP,    0)
+	FEAT_DEF(RISCV_ISA_B, REG_HWCAP,    1)
+	FEAT_DEF(RISCV_ISA_C, REG_HWCAP,    2)
+	FEAT_DEF(RISCV_ISA_D, REG_HWCAP,    3)
+	FEAT_DEF(RISCV_ISA_E, REG_HWCAP,    4)
+	FEAT_DEF(RISCV_ISA_F, REG_HWCAP,    5)
+	FEAT_DEF(RISCV_ISA_G, REG_HWCAP,    6)
+	FEAT_DEF(RISCV_ISA_H, REG_HWCAP,    7)
+	FEAT_DEF(RISCV_ISA_I, REG_HWCAP,    8)
+	FEAT_DEF(RISCV_ISA_J, REG_HWCAP,    9)
+	FEAT_DEF(RISCV_ISA_K, REG_HWCAP,   10)
+	FEAT_DEF(RISCV_ISA_L, REG_HWCAP,   11)
+	FEAT_DEF(RISCV_ISA_M, REG_HWCAP,   12)
+	FEAT_DEF(RISCV_ISA_N, REG_HWCAP,   13)
+	FEAT_DEF(RISCV_ISA_O, REG_HWCAP,   14)
+	FEAT_DEF(RISCV_ISA_P, REG_HWCAP,   15)
+	FEAT_DEF(RISCV_ISA_Q, REG_HWCAP,   16)
+	FEAT_DEF(RISCV_ISA_R, REG_HWCAP,   17)
+	FEAT_DEF(RISCV_ISA_S, REG_HWCAP,   18)
+	FEAT_DEF(RISCV_ISA_T, REG_HWCAP,   19)
+	FEAT_DEF(RISCV_ISA_U, REG_HWCAP,   20)
+	FEAT_DEF(RISCV_ISA_V, REG_HWCAP,   21)
+	FEAT_DEF(RISCV_ISA_W, REG_HWCAP,   22)
+	FEAT_DEF(RISCV_ISA_X, REG_HWCAP,   23)
+	FEAT_DEF(RISCV_ISA_Y, REG_HWCAP,   24)
+	FEAT_DEF(RISCV_ISA_Z, REG_HWCAP,   25)
+};
+/*
+ * Read AUXV software register and get cpu features for ARM
+ */
+static void
+rte_cpu_get_features(hwcap_registers_t out)
+{
+	out[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP);
+	out[REG_HWCAP2] = rte_cpu_getauxval(AT_HWCAP2);
+}
+
+/*
+ * Checks if a particular flag is available on current machine.
+ */
+int
+rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
+{
+	const struct feature_entry *feat;
+	hwcap_registers_t regs = {0};
+
+	if (feature >= RTE_CPUFLAG_NUMFLAGS)
+		return -ENOENT;
+
+	feat = &rte_cpu_feature_table[feature];
+	if (feat->reg == REG_NONE)
+		return -EFAULT;
+
+	rte_cpu_get_features(regs);
+	return (regs[feat->reg] >> feat->bit) & 1;
+}
+
+const char *
+rte_cpu_get_flag_name(enum rte_cpu_flag_t feature)
+{
+	if (feature >= RTE_CPUFLAG_NUMFLAGS)
+		return NULL;
+	return rte_cpu_feature_table[feature].name;
+}
+
+void
+rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics)
+{
+	memset(intrinsics, 0, sizeof(*intrinsics));
+}
diff --git a/lib/eal/riscv/rte_cycles.c b/lib/eal/riscv/rte_cycles.c
new file mode 100644
index 0000000000..358f271311
--- /dev/null
+++ b/lib/eal/riscv/rte_cycles.c
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015 Cavium, Inc
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#include <stdio.h>
+
+#include "eal_private.h"
+#include "rte_byteorder.h"
+#include "rte_cycles.h"
+#include "rte_log.h"
+
+/** Read generic counter frequency */
+static uint64_t
+__rte_riscv_timefrq(void)
+{
+#define TIMEBASE_FREQ_SIZE	8
+	if (RTE_RISCV_TIME_FREQ > 0)
+		return RTE_RISCV_TIME_FREQ;
+	uint8_t buf[TIMEBASE_FREQ_SIZE];
+	ssize_t cnt;
+	FILE *file;
+
+	file = fopen("/proc/device-tree/cpus/timebase-frequency", "rb");
+	if (!file)
+		goto fail;
+
+	cnt = fread(buf, 1, TIMEBASE_FREQ_SIZE, file);
+	fclose(file);
+	switch (cnt) {
+	case 8:
+		return rte_be_to_cpu_64(*(uint64_t *)buf);
+	case 4:
+		return rte_be_to_cpu_32(*(uint32_t *)buf);
+	default:
+		break;
+	}
+fail:
+	RTE_LOG(WARNING, EAL, "Unable to read timebase-frequency from FDT.\n");
+	return 0;
+}
+
+uint64_t
+get_tsc_freq_arch(void)
+{
+	RTE_LOG(NOTICE, EAL, "TSC using RISC-V %s.\n",
+		RTE_RISCV_RDTSC_USE_HPM ? "rdcycle" : "rdtime");
+	if (!RTE_RISCV_RDTSC_USE_HPM)
+		return __rte_riscv_timefrq();
+#define CYC_PER_1MHZ 1E6
+	/*
+	 * Use real time clock to estimate current cycle frequency
+	 */
+	uint64_t ticks, frq;
+	uint64_t start_ticks, cur_ticks;
+	uint64_t start_cycle, end_cycle;
+
+	/* Do not proceed unless clock frequency can be obtained. */
+	frq = __rte_riscv_timefrq();
+	if (!frq)
+		return 0;
+
+	/* Number of ticks for 1/10 second */
+	ticks = frq / 10;
+
+	start_ticks = __rte_riscv_rdtime_precise();
+	start_cycle = rte_rdtsc_precise();
+	do {
+		cur_ticks = __rte_riscv_rdtime();
+	} while ((cur_ticks - start_ticks) < ticks);
+	end_cycle = rte_rdtsc_precise();
+
+	/* Adjust the cycles to next 1Mhz */
+	return RTE_ALIGN_MUL_CEIL((end_cycle - start_cycle) * 10, CYC_PER_1MHZ);
+}
diff --git a/lib/eal/riscv/rte_hypervisor.c b/lib/eal/riscv/rte_hypervisor.c
new file mode 100644
index 0000000000..92b5435993
--- /dev/null
+++ b/lib/eal/riscv/rte_hypervisor.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#include "rte_hypervisor.h"
+
+enum rte_hypervisor
+rte_hypervisor_get(void)
+{
+	return RTE_HYPERVISOR_UNKNOWN;
+}
diff --git a/lib/eal/riscv/rte_power_intrinsics.c b/lib/eal/riscv/rte_power_intrinsics.c
new file mode 100644
index 0000000000..240e7b6b87
--- /dev/null
+++ b/lib/eal/riscv/rte_power_intrinsics.c
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#include "rte_power_intrinsics.h"
+
+/**
+ * This function is not supported on RISC-V 64
+ */
+int
+rte_power_monitor(const struct rte_power_monitor_cond *pmc,
+		  const uint64_t tsc_timestamp)
+{
+	RTE_SET_USED(pmc);
+	RTE_SET_USED(tsc_timestamp);
+
+	return -ENOTSUP;
+}
+
+/**
+ * This function is not supported on RISC-V 64
+ */
+int
+rte_power_pause(const uint64_t tsc_timestamp)
+{
+	RTE_SET_USED(tsc_timestamp);
+
+	return -ENOTSUP;
+}
+
+/**
+ * This function is not supported on RISC-V 64
+ */
+int
+rte_power_monitor_wakeup(const unsigned int lcore_id)
+{
+	RTE_SET_USED(lcore_id);
+
+	return -ENOTSUP;
+}
+
+/**
+ * This function is not supported on RISC-V 64
+ */
+int
+rte_power_monitor_multi(const struct rte_power_monitor_cond pmc[],
+			const uint32_t num, const uint64_t tsc_timestamp)
+{
+	RTE_SET_USED(pmc);
+	RTE_SET_USED(num);
+	RTE_SET_USED(tsc_timestamp);
+
+	return -ENOTSUP;
+}
diff --git a/meson.build b/meson.build
index 937f6110c0..a8db04a1ee 100644
--- a/meson.build
+++ b/meson.build
@@ -50,6 +50,8 @@ elif host_machine.cpu_family().startswith('arm') or host_machine.cpu_family().st
     arch_subdir = 'arm'
 elif host_machine.cpu_family().startswith('ppc')
     arch_subdir = 'ppc'
+elif host_machine.cpu_family().startswith('riscv')
+    arch_subdir = 'riscv'
 endif
 
 # configure the build, and make sure configs here and in config folder are
-- 
2.30.2

[PATCH v2 2/8] net/ixgbe: enable vector stubs for RISC-V

[Stanislaw Kardach]

Re-use vector processing stubs in ixgbe PMD defined for PPC for RISC-V.
This enables ixgbe PMD usage in scalar mode on this architecture.

The ixgbe PMD driver was validated with Intel X520-DA2 NIC and the
test-pmd application. Packet transfer checked using all UIO drivers
available for non-IOMMU platforms: uio_pci_generic, vfio-pci noiommu and
igb_uio.

Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
---
 doc/guides/nics/features/ixgbe.ini | 1 +
 drivers/net/ixgbe/ixgbe_rxtx.c     | 4 ++--
 drivers/net/ixgbe/meson.build      | 6 ------
 3 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/doc/guides/nics/features/ixgbe.ini b/doc/guides/nics/features/ixgbe.ini
index c5333d1142..b776ca1cf1 100644
--- a/doc/guides/nics/features/ixgbe.ini
+++ b/doc/guides/nics/features/ixgbe.ini
@@ -54,6 +54,7 @@ Windows              = Y
 ARMv8                = Y
 x86-32               = Y
 x86-64               = Y
+rv64                 = Y
 
 [rte_flow items]
 eth                  = Y
diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c
index 9e8ea366a5..009d9b624a 100644
--- a/drivers/net/ixgbe/ixgbe_rxtx.c
+++ b/drivers/net/ixgbe/ixgbe_rxtx.c
@@ -5957,8 +5957,8 @@ ixgbe_config_rss_filter(struct rte_eth_dev *dev,
 	return 0;
 }
 
-/* Stubs needed for linkage when RTE_ARCH_PPC_64 is set */
-#if defined(RTE_ARCH_PPC_64)
+/* Stubs needed for linkage when RTE_ARCH_PPC_64 or RTE_ARCH_RISCV is set */
+#if defined(RTE_ARCH_PPC_64) || defined(RTE_ARCH_RISCV)
 int
 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
 {
diff --git a/drivers/net/ixgbe/meson.build b/drivers/net/ixgbe/meson.build
index 88539e97d5..162f8d5f46 100644
--- a/drivers/net/ixgbe/meson.build
+++ b/drivers/net/ixgbe/meson.build
@@ -1,12 +1,6 @@
 # SPDX-License-Identifier: BSD-3-Clause
 # Copyright(c) 2017 Intel Corporation
 
-if arch_subdir == 'riscv'
-		build = false
-		reason = 'riscv arch not supported'
-		subdir_done()
-endif
-
 cflags += ['-DRTE_LIBRTE_IXGBE_BYPASS']
 
 subdir('base')
-- 
2.30.2

[PATCH v2 3/8] net/memif: set memfd syscall ID on RISC-V

[Stanislaw Kardach]

Define the missing __NR_memfd_create syscall id to enable the memif PMD.

Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
---
 drivers/net/memif/meson.build     | 5 -----
 drivers/net/memif/rte_eth_memif.h | 2 ++
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/net/memif/meson.build b/drivers/net/memif/meson.build
index 9afb495953..680bc8631c 100644
--- a/drivers/net/memif/meson.build
+++ b/drivers/net/memif/meson.build
@@ -5,11 +5,6 @@ if not is_linux
     build = false
     reason = 'only supported on Linux'
 endif
-if arch_subdir == 'riscv'
-		build = false
-		reason = 'riscv arch not supported'
-		subdir_done()
-endif
 
 sources = files(
         'memif_socket.c',
diff --git a/drivers/net/memif/rte_eth_memif.h b/drivers/net/memif/rte_eth_memif.h
index a5ee23d42e..81e7dceae0 100644
--- a/drivers/net/memif/rte_eth_memif.h
+++ b/drivers/net/memif/rte_eth_memif.h
@@ -180,6 +180,8 @@ const char *memif_version(void);
 #define __NR_memfd_create 360
 #elif defined __i386__
 #define __NR_memfd_create 356
+#elif defined __riscv
+#define __NR_memfd_create 279
 #else
 #error "__NR_memfd_create unknown for this architecture"
 #endif
-- 
2.30.2

[PATCH v2 4/8] net/tap: set BPF syscall ID for RISC-V

[Stanislaw Kardach]

Define the missing __NR_bpf syscall id to enable the tap PMD.

Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
---
 drivers/net/tap/meson.build | 5 -----
 drivers/net/tap/tap_bpf.h   | 2 ++
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/net/tap/meson.build b/drivers/net/tap/meson.build
index 3efac9ac07..c09713a67b 100644
--- a/drivers/net/tap/meson.build
+++ b/drivers/net/tap/meson.build
@@ -5,11 +5,6 @@ if not is_linux
     build = false
     reason = 'only supported on Linux'
 endif
-if arch_subdir == 'riscv'
-		build = false
-		reason = 'riscv arch not supported'
-		subdir_done()
-endif
 sources = files(
         'rte_eth_tap.c',
         'tap_bpf_api.c',
diff --git a/drivers/net/tap/tap_bpf.h b/drivers/net/tap/tap_bpf.h
index f0b9fc7a2c..639bdf3a79 100644
--- a/drivers/net/tap/tap_bpf.h
+++ b/drivers/net/tap/tap_bpf.h
@@ -101,6 +101,8 @@ union bpf_attr {
 #  define __NR_bpf 351
 # elif defined(__powerpc__)
 #  define __NR_bpf 361
+# elif defined(__riscv)
+#  define __NR_bpf 280
 # else
 #  error __NR_bpf not defined
 # endif
-- 
2.30.2

[PATCH v2 5/8] examples/l3fwd: enable RISC-V operation

[Stanislaw Kardach]

Add missing em_mask_key() implementation and fix l3fwd_common.h
inclusion in FIB lookup functions to enable the l3fwd to be run on
RISC-V.

Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
---
 examples/l3fwd/l3fwd_em.c  | 8 ++++++++
 examples/l3fwd/l3fwd_fib.c | 2 ++
 examples/l3fwd/meson.build | 6 ------
 3 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
index 24d0910fe0..bbd3452546 100644
--- a/examples/l3fwd/l3fwd_em.c
+++ b/examples/l3fwd/l3fwd_em.c
@@ -239,6 +239,14 @@ em_mask_key(void *key, xmm_t mask)
 
 	return vec_and(data, mask);
 }
+#elif defined(RTE_ARCH_RISCV)
+static inline xmm_t
+em_mask_key(void *key, xmm_t mask)
+{
+	xmm_t data = vect_load_128(key);
+
+	return vect_and(data, mask);
+}
 #else
 #error No vector engine (SSE, NEON, ALTIVEC) available, check your toolchain
 #endif
diff --git a/examples/l3fwd/l3fwd_fib.c b/examples/l3fwd/l3fwd_fib.c
index 6e0054b4cb..bdb7d7535d 100644
--- a/examples/l3fwd/l3fwd_fib.c
+++ b/examples/l3fwd/l3fwd_fib.c
@@ -18,6 +18,8 @@
 #include "l3fwd_neon.h"
 #elif defined RTE_ARCH_PPC_64
 #include "l3fwd_altivec.h"
+#else
+#include "l3fwd_common.h"
 #endif
 #include "l3fwd_event.h"
 #include "l3fwd_route.h"
diff --git a/examples/l3fwd/meson.build b/examples/l3fwd/meson.build
index 75fa19b7fe..0830b3eb31 100644
--- a/examples/l3fwd/meson.build
+++ b/examples/l3fwd/meson.build
@@ -6,12 +6,6 @@
 # To build this example as a standalone application with an already-installed
 # DPDK instance, use 'make'
 
-if dpdk_conf.has('RTE_ARCH_RISCV')
-		build = false
-		reason = 'riscv arch not supported'
-		subdir_done()
-endif
-
 allow_experimental_apis = true
 deps += ['hash', 'lpm', 'fib', 'eventdev']
 sources = files(
-- 
2.30.2

[PATCH v2 6/8] test/cpuflags: add test for RISC-V cpu flag

[Stanislaw Kardach]

From: Michal Mazurek <maz@semihalf.com>

Add checks for all flag values defined in the RISC-V misa CSR register.

Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
Signed-off-by: Michal Mazurek <maz@semihalf.com>
Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
---
 app/test/test_cpuflags.c | 81 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 81 insertions(+)

diff --git a/app/test/test_cpuflags.c b/app/test/test_cpuflags.c
index 40f6ac7fca..98a99c2c7d 100644
--- a/app/test/test_cpuflags.c
+++ b/app/test/test_cpuflags.c
@@ -200,6 +200,87 @@ test_cpuflags(void)
 	CHECK_FOR_FLAG(RTE_CPUFLAG_INVTSC);
 #endif
 
+#if defined(RTE_ARCH_RISCV)
+
+	printf("Check for RISCV_ISA_A:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_A);
+
+	printf("Check for RISCV_ISA_B:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_B);
+
+	printf("Check for RISCV_ISA_C:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_C);
+
+	printf("Check for RISCV_ISA_D:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_D);
+
+	printf("Check for RISCV_ISA_E:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_E);
+
+	printf("Check for RISCV_ISA_F:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_F);
+
+	printf("Check for RISCV_ISA_G:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_G);
+
+	printf("Check for RISCV_ISA_H:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_H);
+
+	printf("Check for RISCV_ISA_I:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_I);
+
+	printf("Check for RISCV_ISA_J:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_J);
+
+	printf("Check for RISCV_ISA_K:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_K);
+
+	printf("Check for RISCV_ISA_L:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_L);
+
+	printf("Check for RISCV_ISA_M:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_M);
+
+	printf("Check for RISCV_ISA_N:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_N);
+
+	printf("Check for RISCV_ISA_O:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_O);
+
+	printf("Check for RISCV_ISA_P:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_P);
+
+	printf("Check for RISCV_ISA_Q:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Q);
+
+	printf("Check for RISCV_ISA_R:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_R);
+
+	printf("Check for RISCV_ISA_S:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_S);
+
+	printf("Check for RISCV_ISA_T:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_T);
+
+	printf("Check for RISCV_ISA_U:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_U);
+
+	printf("Check for RISCV_ISA_V:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_V);
+
+	printf("Check for RISCV_ISA_W:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_W);
+
+	printf("Check for RISCV_ISA_X:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_X);
+
+	printf("Check for RISCV_ISA_Y:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Y);
+
+	printf("Check for RISCV_ISA_Z:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Z);
+#endif
+
 	/*
 	 * Check if invalid data is handled properly
 	 */
-- 
2.30.2

[PATCH v2 7/8] devtools: add RISC-V to test-meson-builds.sh

[Stanislaw Kardach]

Validate RISC-V compilation when test-meson-builds.sh is called. The
check will be only performed if appropriate toolchain is present on the
system (same as with other architectures).

Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
---
 devtools/test-meson-builds.sh | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/devtools/test-meson-builds.sh b/devtools/test-meson-builds.sh
index a653b253cb..12513e9d7f 100755
--- a/devtools/test-meson-builds.sh
+++ b/devtools/test-meson-builds.sh
@@ -275,6 +275,12 @@ for f in $srcdir/config/ppc/ppc* ; do
 	build $targetdir $f ABI $use_shared
 done
 
+# RISC-V configurations
+for f in $srcdir/config/riscv/riscv* ; do
+	targetdir=build-$(basename $f | tr '_' '-' | cut -d'-' -f-2)
+	build $targetdir $f ABI $use_shared
+done
+
 # Test installation of the x86-generic target, to be used for checking
 # the sample apps build using the pkg-config file for cflags and libs
 load_env cc
-- 
2.30.2

Re: [PATCH v2 7/8] devtools: add RISC-V to test-meson-builds.sh

[Stanisław Kardach]

[-- Attachment #1: Type: text/plain, Size: 1286 bytes --]

On Tue, May 10, 2022 at 5:08 PM Stanislaw Kardach <kda@semihalf.com> wrote:

> Validate RISC-V compilation when test-meson-builds.sh is called. The
> check will be only performed if appropriate toolchain is present on the
> system (same as with other architectures).
>
> Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
> Sponsored-by: Sam Grove <sam.grove@sifive.com>
> Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
> ---
>  devtools/test-meson-builds.sh | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/devtools/test-meson-builds.sh b/devtools/test-meson-builds.sh
> index a653b253cb..12513e9d7f 100755
> --- a/devtools/test-meson-builds.sh
> +++ b/devtools/test-meson-builds.sh
> @@ -275,6 +275,12 @@ for f in $srcdir/config/ppc/ppc* ; do
>         build $targetdir $f ABI $use_shared
>  done
>
> +# RISC-V configurations
> +for f in $srcdir/config/riscv/riscv* ; do
> +       targetdir=build-$(basename $f | tr '_' '-' | cut -d'-' -f-2)
> +       build $targetdir $f ABI $use_shared
> +done
> +
>
This should not be an iteration but a single build command. I'll re-send as
v3.

>  # Test installation of the x86-generic target, to be used for checking
>  # the sample apps build using the pkg-config file for cflags and libs
>  load_env cc
> --
> 2.30.2
>

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[PATCH v2 8/8] ci: add RISCV64 cross compilation job

[Stanislaw Kardach]

Checks cross-compilation using Ubuntu 20.04 x86.

Signed-off-by: David Marchand <david.marchand@redhat.com>
Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
---
 .ci/linux-build.sh          |  4 ++++
 .github/workflows/build.yml | 11 ++++++++++-
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/.ci/linux-build.sh b/.ci/linux-build.sh
index 877243c9c8..aa5e9ec114 100755
--- a/.ci/linux-build.sh
+++ b/.ci/linux-build.sh
@@ -74,6 +74,10 @@ if [ "$PPC64LE" = "true" ]; then
     cross_file=config/ppc/ppc64le-power8-linux-gcc-ubuntu
 fi
 
+if [ "$RISCV64" = "true" ]; then
+    cross_file=config/riscv/riscv64_linux_gcc
+fi
+
 if [ -n "$cross_file" ]; then
     OPTS="$OPTS --cross-file $cross_file"
 fi
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index e2f94d786b..ca468da8fa 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -25,6 +25,7 @@ jobs:
       MINI: ${{ matrix.config.mini != '' }}
       PPC64LE: ${{ matrix.config.cross == 'ppc64le' }}
       REF_GIT_TAG: v22.03
+      RISCV64: ${{ matrix.config.cross == 'riscv64' }}
       RUN_TESTS: ${{ contains(matrix.config.checks, 'tests') }}
 
     strategy:
@@ -73,6 +74,10 @@ jobs:
             compiler: gcc
             library: shared
             cross: ppc64le
+          - os: ubuntu-20.04
+            compiler: gcc
+            library: shared
+            cross: riscv64
 
     steps:
     - name: Checkout sources
@@ -131,8 +136,12 @@ jobs:
       if: env.PPC64LE == 'true'
       run: sudo apt install -y gcc-powerpc64le-linux-gnu libc6-dev-ppc64el-cross
         pkg-config-powerpc-linux-gnu
+    - name: Install riscv64 cross compiling packages
+      if: env.RISCV64 == 'true'
+      run: sudo apt install -y gcc-riscv64-linux-gnu libc6-dev-riscv64-cross
+        pkg-config-riscv64-linux-gnu
     - name: Install test tools packages
-      if: env.AARCH64 != 'true' || env.PPC64LE != 'true' || env.RUN_TESTS == 'true'
+      if: env.AARCH64 != 'true' || env.PPC64LE != 'true' || env.RISCV64 != 'true' || env.RUN_TESTS == 'true'
       run: sudo apt install -y gdb
     - name: Install doc generation packages
       if: env.BUILD_DOCS == 'true'
-- 
2.30.2

[PATCH v3 0/8] Introduce support for RISC-V architecture

[Stanislaw Kardach]

This patchset adds support for building and running DPDK on 64bit RISC-V
architecture. The initial support targets rv64gc (rv64imafdc) ISA and
was tested on SiFive Unmatched development board with the Freedom U740
SoC running Linux (freedom-u-sdk based kernel).
I have tested this codebase using DPDK unit and perf tests as well as
test-pmd, l2fwd and l3fwd examples.
The NIC attached to the DUT was Intel X520-DA2 which uses ixgbe PMD.
On the UIO side, since U740 does not have an IOMMU, I've used igb_uio,
uio_pci_generic and vfio-pci noiommu drivers.

Functional verification done using meson tests. fast-tests suite passing with
the default config.

PMD verification done using a Intel x520-DA2 NIC (ixgbe) and the test-pmd
application. Packet transfer checked using all UIO drivers available for
non-IOMMU platforms: uio_pci_generic, vfio-pci noiommu and igb_uio.

The i40e PMD driver is disabled on RISC-V as the rv64gc ISA has no vector
operations.

RISCV support is currently limited to Linux as the time measurement frequency
discovery is tied to reading a device-tree node via procfs.

Clang compilation currently not supported due to issues with missing relocation
relaxation.

Commit 1 introduces EAL and build system support for RISC-V architecture
   as well as documentation updates.
Commits 2-5 add missing defines and stubs to enable RISC-V operation in
   non-EAL parts.
Commit 6 adds RISC-V specific cpuflags test.
Commits 7-8 add RISC-V build testing to test-meson-builds.sh and github CI.

I appreciate Your comments and feedback.

Best Regards,
Stanislaw Kardach

v3:
  - Limit test-meson-builds.sh testing to a generic rv64gc configuration.
    Previous version was missing this change by mistake.
v2:
  - Separate bug-fixes into separate series.
  - Prevent RV64_CSRR leak to API users.
  - Limit test-meson-builds.sh testing to a generic rv64gc configuration.
  - Clean-up release notes and fix style issues.


Michal Mazurek (2):
  eal: add initial support for RISC-V architecture
  test/cpuflags: add test for RISC-V cpu flag

Stanislaw Kardach (6):
  net/ixgbe: enable vector stubs for RISC-V
  net/memif: set memfd syscall ID on RISC-V
  net/tap: set BPF syscall ID for RISC-V
  examples/l3fwd: enable RISC-V operation
  devtools: add RISC-V to test-meson-builds.sh
  ci: add RISCV64 cross compilation job

---
NOTE: I have added maintainers for each commit based on MAINTAINERS file.
   However some modules (l3fwd, net/tap and cpuflags unit tests) do not have
   any maintainers assigned, hence I've targeted dev@dpdk.org mailing list as
   if it was a commit adding new files.

 .ci/linux-build.sh                            |   4 +
 .github/workflows/build.yml                   |  11 +-
 MAINTAINERS                                   |   6 +
 app/test/test_cpuflags.c                      |  81 ++++++++++
 app/test/test_xmmt_ops.h                      |  16 ++
 config/meson.build                            |   2 +
 config/riscv/meson.build                      | 143 ++++++++++++++++++
 config/riscv/riscv64_linux_gcc                |  17 +++
 config/riscv/riscv64_sifive_u740_linux_gcc    |  19 +++
 devtools/test-meson-builds.sh                 |   4 +
 doc/guides/contributing/design.rst            |   2 +-
 .../linux_gsg/cross_build_dpdk_for_riscv.rst  | 125 +++++++++++++++
 doc/guides/linux_gsg/index.rst                |   1 +
 doc/guides/nics/features.rst                  |   5 +
 doc/guides/nics/features/default.ini          |   1 +
 doc/guides/nics/features/ixgbe.ini            |   1 +
 doc/guides/rel_notes/release_22_07.rst        |   8 +
 drivers/net/i40e/meson.build                  |   6 +
 drivers/net/ixgbe/ixgbe_rxtx.c                |   4 +-
 drivers/net/memif/rte_eth_memif.h             |   2 +
 drivers/net/tap/tap_bpf.h                     |   2 +
 examples/l3fwd/l3fwd_em.c                     |   8 +
 examples/l3fwd/l3fwd_fib.c                    |   2 +
 lib/eal/riscv/include/meson.build             |  23 +++
 lib/eal/riscv/include/rte_atomic.h            |  52 +++++++
 lib/eal/riscv/include/rte_byteorder.h         |  44 ++++++
 lib/eal/riscv/include/rte_cpuflags.h          |  55 +++++++
 lib/eal/riscv/include/rte_cycles.h            | 105 +++++++++++++
 lib/eal/riscv/include/rte_io.h                |  21 +++
 lib/eal/riscv/include/rte_mcslock.h           |  18 +++
 lib/eal/riscv/include/rte_memcpy.h            |  63 ++++++++
 lib/eal/riscv/include/rte_pause.h             |  31 ++++
 lib/eal/riscv/include/rte_pflock.h            |  17 +++
 lib/eal/riscv/include/rte_power_intrinsics.h  |  22 +++
 lib/eal/riscv/include/rte_prefetch.h          |  50 ++++++
 lib/eal/riscv/include/rte_rwlock.h            |  44 ++++++
 lib/eal/riscv/include/rte_spinlock.h          |  67 ++++++++
 lib/eal/riscv/include/rte_ticketlock.h        |  21 +++
 lib/eal/riscv/include/rte_vect.h              |  55 +++++++
 lib/eal/riscv/meson.build                     |  11 ++
 lib/eal/riscv/rte_cpuflags.c                  | 122 +++++++++++++++
 lib/eal/riscv/rte_cycles.c                    |  77 ++++++++++
 lib/eal/riscv/rte_hypervisor.c                |  13 ++
 lib/eal/riscv/rte_power_intrinsics.c          |  56 +++++++
 meson.build                                   |   2 +
 45 files changed, 1435 insertions(+), 4 deletions(-)
 create mode 100644 config/riscv/meson.build
 create mode 100644 config/riscv/riscv64_linux_gcc
 create mode 100644 config/riscv/riscv64_sifive_u740_linux_gcc
 create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
 create mode 100644 lib/eal/riscv/include/meson.build
 create mode 100644 lib/eal/riscv/include/rte_atomic.h
 create mode 100644 lib/eal/riscv/include/rte_byteorder.h
 create mode 100644 lib/eal/riscv/include/rte_cpuflags.h
 create mode 100644 lib/eal/riscv/include/rte_cycles.h
 create mode 100644 lib/eal/riscv/include/rte_io.h
 create mode 100644 lib/eal/riscv/include/rte_mcslock.h
 create mode 100644 lib/eal/riscv/include/rte_memcpy.h
 create mode 100644 lib/eal/riscv/include/rte_pause.h
 create mode 100644 lib/eal/riscv/include/rte_pflock.h
 create mode 100644 lib/eal/riscv/include/rte_power_intrinsics.h
 create mode 100644 lib/eal/riscv/include/rte_prefetch.h
 create mode 100644 lib/eal/riscv/include/rte_rwlock.h
 create mode 100644 lib/eal/riscv/include/rte_spinlock.h
 create mode 100644 lib/eal/riscv/include/rte_ticketlock.h
 create mode 100644 lib/eal/riscv/include/rte_vect.h
 create mode 100644 lib/eal/riscv/meson.build
 create mode 100644 lib/eal/riscv/rte_cpuflags.c
 create mode 100644 lib/eal/riscv/rte_cycles.c
 create mode 100644 lib/eal/riscv/rte_hypervisor.c
 create mode 100644 lib/eal/riscv/rte_power_intrinsics.c

-- 
2.30.2

[PATCH v3 1/8] eal: add initial support for RISC-V architecture

[Stanislaw Kardach]

From: Michal Mazurek <maz@semihalf.com>

Add all necessary elements for DPDK to compile and run EAL on SiFive
Freedom U740 SoC which is based on SiFive U74-MC (ISA: rv64imafdc)
core complex.

This includes:

- EAL library implementation for rv64imafdc ISA.
- meson build structure for 'riscv' architecture. RTE_ARCH_RISCV define
  is added for architecture identification.
- xmm_t structure operation stubs as there is no vector support in the
  U74 core.

Compilation was tested on Ubuntu and Arch Linux using riscv64 toolchain.
Clang compilation currently not supported due to issues with missing
relocation relaxation.

Two rte_rdtsc() schemes are provided: stable low-resolution using rdtime
(default) and unstable high-resolution using rdcycle. User can override
the scheme by defining RTE_RISCV_RDTSC_USE_HPM=1 during compile time of
both DPDK and the application. The reasoning for this is as follows.
The RISC-V ISA mandates that clock read by rdtime has to be of constant
period and synchronized between all hardware threads within 1 tick
(chapter 10.1 in version 20191213 of RISC-V spec).
However this clock may not be of high-enough frequency for dataplane
uses. I.e. on HiFive Unmatched (FU740) it is 1MHz.
There is a high-resolution alternative in form of rdcycle which is
clocked at the core clock frequency. The drawbacks are that it may be
disabled during sleep (WFI) and its frequency might change due to DVFS.

The platform is currently marked as linux-only because rte_cycles
implementation uses the timebase-frequency device-tree node read through
the proc file system. Such approach was chosen because Linux kernel
depends on the presence of this device-tree node.

The i40e PMD driver is disabled on RISC-V as the rv64gc ISA has no vector
operations.

The compilation of following modules has been disabled by this commit
and will be re-enabled in later commits as fixes are introduced:
net/ixgbe, net/memif, net/tap, example/l3fwd.

Known checkpatch errors/warnings:

- ERROR:COMPLEX_MACRO in rte_atomic.h and rte_cycles.h due to inline
  assembly declarations.
- vector_size compiler attribute used in rte_vect.h directly.
- rte_*mb() used directly in rte_atomic.h to reduce code duplication.
- __atomic_thread_fence() used to implement rte_atomic_thread_fence().

Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
Signed-off-by: Michal Mazurek <maz@semihalf.com>
Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
---
Depends-on: series-22867 ("test/ring: remove excessive inlining")
Depends-on: series-22868 ("lpm: add a scalar version of lookupx4 function")
Depends-on: series-22869 ("examples/l3fwd: fix scalar LPM compilation")
---
 MAINTAINERS                                   |   6 +
 app/test/test_xmmt_ops.h                      |  16 ++
 config/meson.build                            |   2 +
 config/riscv/meson.build                      | 143 ++++++++++++++++++
 config/riscv/riscv64_linux_gcc                |  17 +++
 config/riscv/riscv64_sifive_u740_linux_gcc    |  19 +++
 doc/guides/contributing/design.rst            |   2 +-
 .../linux_gsg/cross_build_dpdk_for_riscv.rst  | 125 +++++++++++++++
 doc/guides/linux_gsg/index.rst                |   1 +
 doc/guides/nics/features.rst                  |   5 +
 doc/guides/nics/features/default.ini          |   1 +
 doc/guides/rel_notes/release_22_07.rst        |   8 +
 drivers/net/i40e/meson.build                  |   6 +
 drivers/net/ixgbe/meson.build                 |   6 +
 drivers/net/memif/meson.build                 |   5 +
 drivers/net/tap/meson.build                   |   5 +
 examples/l3fwd/meson.build                    |   6 +
 lib/eal/riscv/include/meson.build             |  23 +++
 lib/eal/riscv/include/rte_atomic.h            |  52 +++++++
 lib/eal/riscv/include/rte_byteorder.h         |  44 ++++++
 lib/eal/riscv/include/rte_cpuflags.h          |  55 +++++++
 lib/eal/riscv/include/rte_cycles.h            | 105 +++++++++++++
 lib/eal/riscv/include/rte_io.h                |  21 +++
 lib/eal/riscv/include/rte_mcslock.h           |  18 +++
 lib/eal/riscv/include/rte_memcpy.h            |  63 ++++++++
 lib/eal/riscv/include/rte_pause.h             |  31 ++++
 lib/eal/riscv/include/rte_pflock.h            |  17 +++
 lib/eal/riscv/include/rte_power_intrinsics.h  |  22 +++
 lib/eal/riscv/include/rte_prefetch.h          |  50 ++++++
 lib/eal/riscv/include/rte_rwlock.h            |  44 ++++++
 lib/eal/riscv/include/rte_spinlock.h          |  67 ++++++++
 lib/eal/riscv/include/rte_ticketlock.h        |  21 +++
 lib/eal/riscv/include/rte_vect.h              |  55 +++++++
 lib/eal/riscv/meson.build                     |  11 ++
 lib/eal/riscv/rte_cpuflags.c                  | 122 +++++++++++++++
 lib/eal/riscv/rte_cycles.c                    |  77 ++++++++++
 lib/eal/riscv/rte_hypervisor.c                |  13 ++
 lib/eal/riscv/rte_power_intrinsics.c          |  56 +++++++
 meson.build                                   |   2 +
 39 files changed, 1341 insertions(+), 1 deletion(-)
 create mode 100644 config/riscv/meson.build
 create mode 100644 config/riscv/riscv64_linux_gcc
 create mode 100644 config/riscv/riscv64_sifive_u740_linux_gcc
 create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
 create mode 100644 lib/eal/riscv/include/meson.build
 create mode 100644 lib/eal/riscv/include/rte_atomic.h
 create mode 100644 lib/eal/riscv/include/rte_byteorder.h
 create mode 100644 lib/eal/riscv/include/rte_cpuflags.h
 create mode 100644 lib/eal/riscv/include/rte_cycles.h
 create mode 100644 lib/eal/riscv/include/rte_io.h
 create mode 100644 lib/eal/riscv/include/rte_mcslock.h
 create mode 100644 lib/eal/riscv/include/rte_memcpy.h
 create mode 100644 lib/eal/riscv/include/rte_pause.h
 create mode 100644 lib/eal/riscv/include/rte_pflock.h
 create mode 100644 lib/eal/riscv/include/rte_power_intrinsics.h
 create mode 100644 lib/eal/riscv/include/rte_prefetch.h
 create mode 100644 lib/eal/riscv/include/rte_rwlock.h
 create mode 100644 lib/eal/riscv/include/rte_spinlock.h
 create mode 100644 lib/eal/riscv/include/rte_ticketlock.h
 create mode 100644 lib/eal/riscv/include/rte_vect.h
 create mode 100644 lib/eal/riscv/meson.build
 create mode 100644 lib/eal/riscv/rte_cpuflags.c
 create mode 100644 lib/eal/riscv/rte_cycles.c
 create mode 100644 lib/eal/riscv/rte_hypervisor.c
 create mode 100644 lib/eal/riscv/rte_power_intrinsics.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 8f4e9c3479..7fb6dccc41 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -296,6 +296,12 @@ F: drivers/*/*/*_altivec.*
 F: app/*/*_altivec.*
 F: examples/*/*_altivec.*
 
+RISC-V
+M: Stanislaw Kardach <kda@semihalf.com>
+F: config/riscv/
+F: doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
+F: lib/eal/riscv/
+
 Intel x86
 M: Bruce Richardson <bruce.richardson@intel.com>
 M: Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>
diff --git a/app/test/test_xmmt_ops.h b/app/test/test_xmmt_ops.h
index 3a82d5ecac..55f256599e 100644
--- a/app/test/test_xmmt_ops.h
+++ b/app/test/test_xmmt_ops.h
@@ -1,5 +1,8 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  * Copyright(c) 2015 Cavium, Inc
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
  */
 
 #ifndef _TEST_XMMT_OPS_H_
@@ -49,6 +52,19 @@ vect_set_epi32(int i3, int i2, int i1, int i0)
 	return data;
 }
 
+#elif defined(RTE_ARCH_RISCV)
+
+#define vect_loadu_sil128(p) vect_load_128(p)
+
+/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */
+static __rte_always_inline xmm_t
+vect_set_epi32(int i3, int i2, int i1, int i0)
+{
+	xmm_t data = (xmm_t){i0, i1, i2, i3};
+
+	return data;
+}
+
 #endif
 
 #endif /* _TEST_XMMT_OPS_H_ */
diff --git a/config/meson.build b/config/meson.build
index 7134e80e8d..7f7b6c92fd 100644
--- a/config/meson.build
+++ b/config/meson.build
@@ -121,6 +121,8 @@ if cpu_instruction_set == 'generic'
         cpu_instruction_set = 'generic'
     elif host_machine.cpu_family().startswith('ppc')
         cpu_instruction_set = 'power8'
+    elif host_machine.cpu_family().startswith('riscv')
+        cpu_instruction_set = 'riscv'
     endif
 endif
 
diff --git a/config/riscv/meson.build b/config/riscv/meson.build
new file mode 100644
index 0000000000..0c16c31fc2
--- /dev/null
+++ b/config/riscv/meson.build
@@ -0,0 +1,143 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2017 Intel Corporation.
+# Copyright(c) 2017 Cavium, Inc
+# Copyright(c) 2021 PANTHEON.tech s.r.o.
+# Copyright(c) 2022 StarFive
+# Copyright(c) 2022 SiFive
+# Copyright(c) 2022 Semihalf
+
+if not is_linux
+    error('Only Linux is supported at this point in time.')
+endif
+
+if not dpdk_conf.get('RTE_ARCH_64')
+    error('Only 64-bit compiles are supported for this platform type')
+endif
+
+dpdk_conf.set('RTE_ARCH', 'riscv')
+dpdk_conf.set('RTE_ARCH_RISCV', 1)
+dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
+
+# common flags to all riscv builds, with lowest priority
+flags_common = [
+    ['RTE_ARCH_RISCV', true],
+    ['RTE_CACHE_LINE_SIZE', 64],
+    # Set this to true if target emulates U-mode TIME CSR via M or S mode trap.
+    # This allows to remove a FENCE on rte_rdtsc_precise() as trap effectively
+    # acts as one.
+    ['RTE_RISCV_EMU_UTIME', false],
+    # Set this to true if target emulates U-mode CYCLE CSR via M or S mode trap.
+    # This allows to remove a FENCE on rte_rdtsc_precise() as trap effectively
+    # acts as one.
+    ['RTE_RISCV_EMU_UCYCLE', false],
+    # Manually set wall time clock frequency for the target. If 0, then it is
+    # read from /proc/device-tree/cpus/timebase-frequency. This property is
+    # guaranteed on Linux, as riscv time_init() requires it.
+    ['RTE_RISCV_TIME_FREQ', 0],
+]
+
+## SoC-specific options.
+# The priority is like this: arch > vendor > common.
+#
+# Note that currently there's no way of getting vendor/microarchitecture id
+# values in userspace which is why the logic of choosing the right flag
+# combination is strictly based on the values passed from a cross-file.
+vendor_generic = {
+    'description': 'Generic RISC-V',
+    'flags': [
+        ['RTE_MACHINE', '"riscv"'],
+        ['RTE_USE_C11_MEM_MODEL', true],
+        ['RTE_MAX_LCORE', 128],
+        ['RTE_MAX_NUMA_NODES', 2]
+    ],
+    'arch_config': {
+        'generic': {'machine_args': ['-march=rv64gc']}
+    }
+}
+
+arch_config_riscv = {
+    '0x8000000000000007': {
+        'machine_args':  ['-march=rv64gc', '-mtune=sifive-7-series'],
+        'flags': [
+            ['RTE_RISCV_EMU_UTIME', true],
+            ['RTE_RISCV_EMU_UCYCLE', true]
+        ]
+    },
+}
+
+vendor_sifive = {
+    'description': 'SiFive',
+    'flags': [
+        ['RTE_MACHINE', '"riscv"'],
+        ['RTE_USE_C11_MEM_MODEL', true],
+        ['RTE_MAX_LCORE', 4],
+        ['RTE_MAX_NUMA_NODES', 1],
+    ],
+    'arch_config': arch_config_riscv
+}
+
+vendors = {
+    'generic': vendor_generic,
+    '0x489': vendor_sifive
+}
+
+# Native/cross vendor/arch detection
+if not meson.is_cross_build()
+    if machine == 'default'
+        # default build
+        vendor_id = 'generic'
+        arch_id = 'generic'
+        message('generic RISC-V')
+    else
+        vendor_id = 'generic'
+        arch_id = 'generic'
+        warning('RISC-V arch discovery not available, using generic!')
+    endif
+else
+    # cross build
+    vendor_id = meson.get_cross_property('vendor_id')
+    arch_id = meson.get_cross_property('arch_id')
+endif
+
+if vendors.has_key(vendor_id)
+    vendor_config = vendors[vendor_id]
+else
+    error('Unsupported RISC-V vendor: @0@. '.format(vendor_id) +
+        'Please add support for it or use the generic ' +
+        '(-Dmachine=generic) build.')
+endif
+
+message('RISC-V vendor: ' + vendor_config['description'])
+message('RISC-V architecture id: ' + arch_id)
+
+arch_config = vendor_config['arch_config']
+if arch_config.has_key(arch_id)
+    # use the specified arch_id machine args if found
+    arch_config = arch_config[arch_id]
+else
+    # unknown micro-architecture id
+    error('Unsupported architecture @0@ of vendor @1@. '
+        .format(arch_id, vendor_id) +
+        'Please add support for it or use the generic ' +
+        '(-Dmachine=generic) build.')
+endif
+
+# Concatenate flags respecting priorities.
+dpdk_flags = flags_common + vendor_config['flags'] + arch_config.get('flags', [])
+
+# apply supported machine args
+machine_args = [] # Clear previous machine args
+foreach flag: arch_config['machine_args']
+    if cc.has_argument(flag)
+        machine_args += flag
+    endif
+endforeach
+
+# apply flags
+foreach flag: dpdk_flags
+    if flag.length() > 0
+        dpdk_conf.set(flag[0], flag[1])
+    endif
+endforeach
+message('Using machine args: @0@'.format(machine_args))
+
diff --git a/config/riscv/riscv64_linux_gcc b/config/riscv/riscv64_linux_gcc
new file mode 100644
index 0000000000..04248d7ecb
--- /dev/null
+++ b/config/riscv/riscv64_linux_gcc
@@ -0,0 +1,17 @@
+[binaries]
+c = 'riscv64-linux-gnu-gcc'
+cpp = 'riscv64-linux-gnu-g++'
+ar = 'riscv64-linux-gnu-ar'
+strip = 'riscv64-linux-gnu-strip'
+pcap-config = ''
+pkgconfig = 'riscv64-linux-gnu-pkg-config'
+
+[host_machine]
+system = 'linux'
+cpu_family = 'riscv64'
+cpu = 'rv64gc'
+endian = 'little'
+
+[properties]
+vendor_id = 'generic'
+arch_id = 'generic'
diff --git a/config/riscv/riscv64_sifive_u740_linux_gcc b/config/riscv/riscv64_sifive_u740_linux_gcc
new file mode 100644
index 0000000000..7b5ad2562d
--- /dev/null
+++ b/config/riscv/riscv64_sifive_u740_linux_gcc
@@ -0,0 +1,19 @@
+[binaries]
+c = 'riscv64-unknown-linux-gnu-gcc'
+cpp = 'riscv64-unknown-linux-gnu-g++'
+ar = 'riscv64-unknown-linux-gnu-ar'
+strip = 'riscv64-unknown-linux-gnu-strip'
+pcap-config = ''
+pkgconfig = 'riscv64-unknown-linux-gnu-pkg-config'
+
+[host_machine]
+system = 'linux'
+cpu_family = 'riscv64'
+cpu = 'rv64gc'
+endian = 'little'
+
+[properties]
+vendor_id = '0x489'
+arch_id = '0x8000000000000007'
+max_lcores = 4
+max_numa_nodes = 1
diff --git a/doc/guides/contributing/design.rst b/doc/guides/contributing/design.rst
index d5ca8b4d9c..0383afe5c8 100644
--- a/doc/guides/contributing/design.rst
+++ b/doc/guides/contributing/design.rst
@@ -42,7 +42,7 @@ Per Architecture Sources
 The following macro options can be used:
 
 * ``RTE_ARCH`` is a string that contains the name of the architecture.
-* ``RTE_ARCH_I686``, ``RTE_ARCH_X86_64``, ``RTE_ARCH_X86_X32``, ``RTE_ARCH_PPC_64``, ``RTE_ARCH_ARM``, ``RTE_ARCH_ARMv7`` or ``RTE_ARCH_ARM64`` are defined only if we are building for those architectures.
+* ``RTE_ARCH_I686``, ``RTE_ARCH_X86_64``, ``RTE_ARCH_X86_X32``, ``RTE_ARCH_PPC_64``, ``RTE_ARCH_RISCV``, ``RTE_ARCH_ARM``, ``RTE_ARCH_ARMv7`` or ``RTE_ARCH_ARM64`` are defined only if we are building for those architectures.
 
 Per Execution Environment Sources
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst b/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
new file mode 100644
index 0000000000..9907b35a1d
--- /dev/null
+++ b/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
@@ -0,0 +1,125 @@
+..  SPDX-License-Identifier: BSD-3-Clause
+    Copyright(c) 2020 ARM Corporation.
+    Copyright(c) 2022 StarFive
+    Copyright(c) 2022 SiFive
+    Copyright(c) 2022 Semihalf
+
+Cross compiling DPDK for RISC-V
+===============================
+
+This chapter describes how to cross compile DPDK for RISC-V from x86 build
+hosts.
+
+.. note::
+
+   While it's possible to compile DPDK natively on a RISC-V host, it is
+   currently recommended to cross-compile as Linux kernel does not offer any
+   way for userspace to discover the vendor and architecture identifiers of the
+   CPU and therefore any per-chip optimization options have to be chosen via
+   a cross-file or ``c_args``.
+
+
+Prerequisites
+-------------
+
+
+Linux kernel
+~~~~~~~~~~~~
+
+It is recommended to use Linux kernel built from
+`SiFive Freedom Unleashed SDK <https://github.com/sifive/freedom-u-sdk>`_.
+
+
+Meson prerequisites
+~~~~~~~~~~~~~~~~~~~
+
+Meson depends on pkgconfig to find the dependencies.
+The package ``pkg-config-riscv64-linux-gnu`` is required for RISC-V.
+To install it in Ubuntu::
+
+   sudo apt install pkg-config-riscv64-linux-gnu
+
+
+GNU toolchain
+-------------
+
+
+Obtain the cross toolchain
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The build process was tested using:
+
+* Ubuntu toolchain (the ``crossbuild-essential-riscv64`` package).
+
+* Latest `RISC-V GNU toolchain
+  <https://github.com/riscv/riscv-gnu-toolchain/releases>`_ on Ubuntu or Arch
+  Linux.
+
+Alternatively the toolchain may be built straight from the source, to do that
+follow the instructions on the riscv-gnu-toolchain github page.
+
+
+Unzip and add into the PATH
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+This step is only required for the riscv-gnu-toolchain. The Ubuntu toolchain is
+in the PATH already.
+
+.. code-block:: console
+
+   tar -xvf riscv64-glibc-ubuntu-20.04-<version>.tar.gz
+   export PATH=$PATH:<cross_install_dir>/riscv/bin
+
+
+Cross Compiling DPDK with GNU toolchain using Meson
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+To cross-compile DPDK for a desired target machine use the following command::
+
+   meson cross-build --cross-file <target_machine_configuration>
+   ninja -C cross-build
+
+For example if the target machine is a generic rv64gc RISC-V, use the following
+command::
+
+   meson riscv64-build-gcc --cross-file config/riscv/riscv64_linux_gcc
+   ninja -C riscv64-build-gcc
+
+If riscv-gnu-toolchain is used, binary names should be updated to match. Update the following lines in the cross-file:
+
+.. code-block:: console
+
+   [binaries]
+   c = 'riscv64-unknown-linux-gnu-gcc'
+   cpp = 'riscv64-unknown-linux-gnu-g++'
+   ar = 'riscv64-unknown-linux-gnu-ar'
+   strip = 'riscv64-unknown-linux-gnu-strip'
+   ...
+
+Some toolchains (such as freedom-u-sdk one) require also setting ``--sysroot``,
+otherwise include paths might not be resolved. To do so, add the appropriate
+paths to the cross-file:
+
+.. code-block:: console
+
+   [properties]
+   ...
+   c_args = ['--sysroot', '<path/to/toolchain/sysroot>']
+   cpp_args = c_args
+   c_link_args = ['--sysroot', '<path/to/toolchain/sysroot>']
+   cpp_link_args = c_link_args
+   ...
+
+
+Supported cross-compilation targets
+-----------------------------------
+
+Currently the following targets are supported:
+
+* Generic rv64gc ISA: ``config/riscv/riscv64_linux_gcc``
+
+* SiFive U740 SoC: ``config/riscv/riscv64_sifive_u740_linux_gcc``
+
+To add a new target support, ``config/riscv/meson.build`` has to be modified by
+adding a new vendor/architecture id and a corresponding cross-file has to be
+added to ``config/riscv`` directory.
diff --git a/doc/guides/linux_gsg/index.rst b/doc/guides/linux_gsg/index.rst
index 16a9a67260..747552c385 100644
--- a/doc/guides/linux_gsg/index.rst
+++ b/doc/guides/linux_gsg/index.rst
@@ -14,6 +14,7 @@ Getting Started Guide for Linux
     sys_reqs
     build_dpdk
     cross_build_dpdk_for_arm64
+    cross_build_dpdk_for_riscv
     linux_drivers
     build_sample_apps
     linux_eal_parameters
diff --git a/doc/guides/nics/features.rst b/doc/guides/nics/features.rst
index 21bedb743f..6c4fa74bc7 100644
--- a/doc/guides/nics/features.rst
+++ b/doc/guides/nics/features.rst
@@ -855,6 +855,11 @@ x86-64
 
 Support 64bits x86 architecture.
 
+rv64
+----
+
+Support 64-bit RISC-V architecture.
+
 
 .. _nic_features_usage_doc:
 
diff --git a/doc/guides/nics/features/default.ini b/doc/guides/nics/features/default.ini
index b1d18ac62c..02198682c6 100644
--- a/doc/guides/nics/features/default.ini
+++ b/doc/guides/nics/features/default.ini
@@ -74,6 +74,7 @@ ARMv8                =
 Power8               =
 x86-32               =
 x86-64               =
+rv64                 =
 Usage doc            =
 Design doc           =
 Perf doc             =
diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst
index 4ae91dd94d..e014247bc0 100644
--- a/doc/guides/rel_notes/release_22_07.rst
+++ b/doc/guides/rel_notes/release_22_07.rst
@@ -55,6 +55,14 @@ New Features
      Also, make sure to start the actual text at the margin.
      =======================================================
 
+* **Added initial RISC-V architecture support.***
+
+  Added EAL implementation for RISC-V architecture. The initial device the
+  porting was tested on is a HiFive Unmatched development board based on the
+  SiFive Freedom U740 SoC. In theory this implementation should work with any
+  ``rv64gc`` ISA compatible implementation with MMU supporting a reasonable
+  address space size (U740 uses sv39 MMU).
+
 * **Updated Intel iavf driver.**
 
   * Added Tx QoS queue rate limitation support.
diff --git a/drivers/net/i40e/meson.build b/drivers/net/i40e/meson.build
index efc5f93e35..a4c1c9079a 100644
--- a/drivers/net/i40e/meson.build
+++ b/drivers/net/i40e/meson.build
@@ -1,6 +1,12 @@
 # SPDX-License-Identifier: BSD-3-Clause
 # Copyright(c) 2017 Intel Corporation
 
+if arch_subdir == 'riscv'
+		build = false
+		reason = 'riscv arch not supported'
+		subdir_done()
+endif
+
 cflags += ['-DPF_DRIVER',
     '-DVF_DRIVER',
     '-DINTEGRATED_VF',
diff --git a/drivers/net/ixgbe/meson.build b/drivers/net/ixgbe/meson.build
index 162f8d5f46..88539e97d5 100644
--- a/drivers/net/ixgbe/meson.build
+++ b/drivers/net/ixgbe/meson.build
@@ -1,6 +1,12 @@
 # SPDX-License-Identifier: BSD-3-Clause
 # Copyright(c) 2017 Intel Corporation
 
+if arch_subdir == 'riscv'
+		build = false
+		reason = 'riscv arch not supported'
+		subdir_done()
+endif
+
 cflags += ['-DRTE_LIBRTE_IXGBE_BYPASS']
 
 subdir('base')
diff --git a/drivers/net/memif/meson.build b/drivers/net/memif/meson.build
index 680bc8631c..9afb495953 100644
--- a/drivers/net/memif/meson.build
+++ b/drivers/net/memif/meson.build
@@ -5,6 +5,11 @@ if not is_linux
     build = false
     reason = 'only supported on Linux'
 endif
+if arch_subdir == 'riscv'
+		build = false
+		reason = 'riscv arch not supported'
+		subdir_done()
+endif
 
 sources = files(
         'memif_socket.c',
diff --git a/drivers/net/tap/meson.build b/drivers/net/tap/meson.build
index c09713a67b..3efac9ac07 100644
--- a/drivers/net/tap/meson.build
+++ b/drivers/net/tap/meson.build
@@ -5,6 +5,11 @@ if not is_linux
     build = false
     reason = 'only supported on Linux'
 endif
+if arch_subdir == 'riscv'
+		build = false
+		reason = 'riscv arch not supported'
+		subdir_done()
+endif
 sources = files(
         'rte_eth_tap.c',
         'tap_bpf_api.c',
diff --git a/examples/l3fwd/meson.build b/examples/l3fwd/meson.build
index 0830b3eb31..75fa19b7fe 100644
--- a/examples/l3fwd/meson.build
+++ b/examples/l3fwd/meson.build
@@ -6,6 +6,12 @@
 # To build this example as a standalone application with an already-installed
 # DPDK instance, use 'make'
 
+if dpdk_conf.has('RTE_ARCH_RISCV')
+		build = false
+		reason = 'riscv arch not supported'
+		subdir_done()
+endif
+
 allow_experimental_apis = true
 deps += ['hash', 'lpm', 'fib', 'eventdev']
 sources = files(
diff --git a/lib/eal/riscv/include/meson.build b/lib/eal/riscv/include/meson.build
new file mode 100644
index 0000000000..7f6e4a5b1e
--- /dev/null
+++ b/lib/eal/riscv/include/meson.build
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2022 StarFive
+# Copyright(c) 2022 SiFive
+# Copyright(c) 2022 Semihalf
+
+arch_headers = files(
+        'rte_atomic.h',
+        'rte_byteorder.h',
+        'rte_cpuflags.h',
+        'rte_cycles.h',
+        'rte_io.h',
+        'rte_mcslock.h',
+        'rte_memcpy.h',
+        'rte_pause.h',
+        'rte_pflock.h',
+        'rte_power_intrinsics.h',
+        'rte_prefetch.h',
+        'rte_rwlock.h',
+        'rte_spinlock.h',
+        'rte_ticketlock.h',
+        'rte_vect.h',
+)
+install_headers(arch_headers, subdir: get_option('include_subdir_arch'))
diff --git a/lib/eal/riscv/include/rte_atomic.h b/lib/eal/riscv/include/rte_atomic.h
new file mode 100644
index 0000000000..4b4633c914
--- /dev/null
+++ b/lib/eal/riscv/include/rte_atomic.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ * All rights reserved.
+ */
+
+#ifndef RTE_ATOMIC_RISCV_H
+#define RTE_ATOMIC_RISCV_H
+
+#ifndef RTE_FORCE_INTRINSICS
+#  error Platform must be built with RTE_FORCE_INTRINSICS
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <rte_common.h>
+#include <rte_config.h>
+#include "generic/rte_atomic.h"
+
+#define rte_mb()	asm volatile("fence rw, rw" : : : "memory")
+
+#define rte_wmb()	asm volatile("fence w, w" : : : "memory")
+
+#define rte_rmb()	asm volatile("fence r, r" : : : "memory")
+
+#define rte_smp_mb()	rte_mb()
+
+#define rte_smp_wmb()	rte_wmb()
+
+#define rte_smp_rmb()	rte_rmb()
+
+#define rte_io_mb()	asm volatile("fence iorw, iorw" : : : "memory")
+
+#define rte_io_wmb()	asm volatile("fence orw, ow" : : : "memory")
+
+#define rte_io_rmb()	asm volatile("fence ir, ir" : : : "memory")
+
+static __rte_always_inline void
+rte_atomic_thread_fence(int memorder)
+{
+	__atomic_thread_fence(memorder);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_ATOMIC_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_byteorder.h b/lib/eal/riscv/include/rte_byteorder.h
new file mode 100644
index 0000000000..21893505d6
--- /dev/null
+++ b/lib/eal/riscv/include/rte_byteorder.h
@@ -0,0 +1,44 @@
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ * Inspired from FreeBSD src/sys/powerpc/include/endian.h
+ * Copyright(c) 1987, 1991, 1993
+ * The Regents of the University of California.  All rights reserved.
+ */
+
+#ifndef RTE_BYTEORDER_RISCV_H
+#define RTE_BYTEORDER_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <rte_common.h>
+#include "generic/rte_byteorder.h"
+
+#ifndef RTE_BYTE_ORDER
+#define RTE_BYTE_ORDER RTE_LITTLE_ENDIAN
+#endif
+
+#define rte_cpu_to_le_16(x) (x)
+#define rte_cpu_to_le_32(x) (x)
+#define rte_cpu_to_le_64(x) (x)
+
+#define rte_cpu_to_be_16(x) rte_bswap16(x)
+#define rte_cpu_to_be_32(x) rte_bswap32(x)
+#define rte_cpu_to_be_64(x) rte_bswap64(x)
+
+#define rte_le_to_cpu_16(x) (x)
+#define rte_le_to_cpu_32(x) (x)
+#define rte_le_to_cpu_64(x) (x)
+
+#define rte_be_to_cpu_16(x) rte_bswap16(x)
+#define rte_be_to_cpu_32(x) rte_bswap32(x)
+#define rte_be_to_cpu_64(x) rte_bswap64(x)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_BYTEORDER_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_cpuflags.h b/lib/eal/riscv/include/rte_cpuflags.h
new file mode 100644
index 0000000000..66e787f898
--- /dev/null
+++ b/lib/eal/riscv/include/rte_cpuflags.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014 IBM Corporation
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_CPUFLAGS_RISCV_H
+#define RTE_CPUFLAGS_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Enumeration of all CPU features supported
+ */
+enum rte_cpu_flag_t {
+	RTE_CPUFLAG_RISCV_ISA_A, /* Atomic */
+	RTE_CPUFLAG_RISCV_ISA_B, /* Bit-Manipulation */
+	RTE_CPUFLAG_RISCV_ISA_C, /* Compressed instruction */
+	RTE_CPUFLAG_RISCV_ISA_D, /* Double precision floating-point  */
+	RTE_CPUFLAG_RISCV_ISA_E, /* RV32E ISA */
+	RTE_CPUFLAG_RISCV_ISA_F, /* Single precision floating-point */
+	RTE_CPUFLAG_RISCV_ISA_G, /* Extension pack (IMAFD, Zicsr, Zifencei) */
+	RTE_CPUFLAG_RISCV_ISA_H, /* Hypervisor */
+	RTE_CPUFLAG_RISCV_ISA_I, /* RV32I/RV64I/IRV128I base ISA */
+	RTE_CPUFLAG_RISCV_ISA_J, /* Dynamic Translation Language */
+	RTE_CPUFLAG_RISCV_ISA_K, /* Reserved */
+	RTE_CPUFLAG_RISCV_ISA_L, /* Decimal Floating-Point */
+	RTE_CPUFLAG_RISCV_ISA_M, /* Integer Multiply/Divide */
+	RTE_CPUFLAG_RISCV_ISA_N, /* User-level interrupts */
+	RTE_CPUFLAG_RISCV_ISA_O, /* Reserved */
+	RTE_CPUFLAG_RISCV_ISA_P, /* Packed-SIMD */
+	RTE_CPUFLAG_RISCV_ISA_Q, /* Quad-precision floating-points */
+	RTE_CPUFLAG_RISCV_ISA_R, /* Reserved */
+	RTE_CPUFLAG_RISCV_ISA_S, /* Supervisor mode */
+	RTE_CPUFLAG_RISCV_ISA_T, /* Transactional memory */
+	RTE_CPUFLAG_RISCV_ISA_U, /* User mode */
+	RTE_CPUFLAG_RISCV_ISA_V, /* Vector */
+	RTE_CPUFLAG_RISCV_ISA_W, /* Reserved */
+	RTE_CPUFLAG_RISCV_ISA_X, /* Non-standard extension present */
+	RTE_CPUFLAG_RISCV_ISA_Y, /* Reserved */
+	RTE_CPUFLAG_RISCV_ISA_Z, /* Reserved */
+	/* The last item */
+	RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */
+};
+
+#include "generic/rte_cpuflags.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_CPUFLAGS_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_cycles.h b/lib/eal/riscv/include/rte_cycles.h
new file mode 100644
index 0000000000..8353cea853
--- /dev/null
+++ b/lib/eal/riscv/include/rte_cycles.h
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015 Cavium, Inc
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_CYCLES_RISCV_H
+#define RTE_CYCLES_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_cycles.h"
+
+#ifndef RTE_RISCV_RDTSC_USE_HPM
+#define RTE_RISCV_RDTSC_USE_HPM 0
+#endif
+
+#define RV64_CSRR(reg, value) \
+	asm volatile("csrr %0, " #reg : "=r" (value) : : "memory")
+
+/** Read wall time counter */
+static __rte_always_inline uint64_t
+__rte_riscv_rdtime(void)
+{
+	uint64_t tsc;
+	RV64_CSRR(time, tsc);
+	return tsc;
+}
+
+/** Read wall time counter ensuring no re-ordering */
+static __rte_always_inline uint64_t
+__rte_riscv_rdtime_precise(void)
+{
+#if !defined(RTE_RISCV_EMU_UTIME)
+	asm volatile("fence" : : : "memory");
+#endif
+	return __rte_riscv_rdtime();
+}
+
+/** Read hart cycle counter */
+static __rte_always_inline uint64_t
+__rte_riscv_rdcycle(void)
+{
+	uint64_t tsc;
+	RV64_CSRR(cycle, tsc);
+	return tsc;
+}
+
+/** Read hart cycle counter ensuring no re-ordering */
+static __rte_always_inline uint64_t
+__rte_riscv_rdcycle_precise(void)
+{
+#if !defined(RTE_RISCV_EMU_UCYCLE)
+	asm volatile("fence" : : : "memory");
+#endif
+	return __rte_riscv_rdcycle();
+}
+
+/**
+ * Read the time base register.
+ *
+ * @return
+ *   The time base for this lcore.
+ */
+static __rte_always_inline uint64_t
+rte_rdtsc(void)
+{
+	/**
+	 * By default TIME userspace counter is used. Although it's frequency
+	 * may not be enough for all applications.
+	 */
+	if (!RTE_RISCV_RDTSC_USE_HPM)
+		return __rte_riscv_rdtime();
+	/**
+	 * Alternatively HPM's CYCLE counter may be used. However this counter
+	 * is not guaranteed by ISA to either be stable frequency or always
+	 * enabled for userspace access (it may trap to kernel or firmware).
+	 */
+	return __rte_riscv_rdcycle();
+}
+
+static inline uint64_t
+rte_rdtsc_precise(void)
+{
+	if (!RTE_RISCV_RDTSC_USE_HPM)
+		return __rte_riscv_rdtime_precise();
+	return __rte_riscv_rdcycle_precise();
+}
+
+static __rte_always_inline uint64_t
+rte_get_tsc_cycles(void)
+{
+	return rte_rdtsc();
+}
+
+#undef RV64_CSRR
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_CYCLES_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_io.h b/lib/eal/riscv/include/rte_io.h
new file mode 100644
index 0000000000..29659c9590
--- /dev/null
+++ b/lib/eal/riscv/include/rte_io.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2016 Cavium, Inc
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_IO_RISCV_H
+#define RTE_IO_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_io.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_IO_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_mcslock.h b/lib/eal/riscv/include/rte_mcslock.h
new file mode 100644
index 0000000000..b517cd5fc5
--- /dev/null
+++ b/lib/eal/riscv/include/rte_mcslock.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Arm Limited
+ */
+
+#ifndef RTE_MCSLOCK_RISCV_H
+#define RTE_MCSLOCK_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_mcslock.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_MCSLOCK_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_memcpy.h b/lib/eal/riscv/include/rte_memcpy.h
new file mode 100644
index 0000000000..e34f19396e
--- /dev/null
+++ b/lib/eal/riscv/include/rte_memcpy.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_MEMCPY_RISCV_H
+#define RTE_MEMCPY_RISCV_H
+
+#include <stdint.h>
+#include <string.h>
+
+#include "rte_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_memcpy.h"
+
+static inline void
+rte_mov16(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 16);
+}
+
+static inline void
+rte_mov32(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 32);
+}
+
+static inline void
+rte_mov48(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 48);
+}
+
+static inline void
+rte_mov64(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 64);
+}
+
+static inline void
+rte_mov128(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 128);
+}
+
+static inline void
+rte_mov256(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 256);
+}
+
+#define rte_memcpy(d, s, n)	memcpy((d), (s), (n))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_MEMCPY_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_pause.h b/lib/eal/riscv/include/rte_pause.h
new file mode 100644
index 0000000000..c24c1f32e8
--- /dev/null
+++ b/lib/eal/riscv/include/rte_pause.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_PAUSE_RISCV_H
+#define RTE_PAUSE_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "rte_atomic.h"
+
+#include "generic/rte_pause.h"
+
+static inline void rte_pause(void)
+{
+	/* Insert pause hint directly to be compatible with old compilers.
+	 * This will work even on platforms without Zihintpause extension
+	 * because this is a FENCE hint instruction which evaluates to NOP then.
+	 */
+	asm volatile(".int 0x0100000F"::: "memory");
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_PAUSE_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_pflock.h b/lib/eal/riscv/include/rte_pflock.h
new file mode 100644
index 0000000000..ce6ca02aca
--- /dev/null
+++ b/lib/eal/riscv/include/rte_pflock.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2021 Microsoft Corporation
+ */
+#ifndef RTE_PFLOCK_RISCV_H
+#define RTE_PFLOCK_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_pflock.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_PFLOCK_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_power_intrinsics.h b/lib/eal/riscv/include/rte_power_intrinsics.h
new file mode 100644
index 0000000000..636e58e71f
--- /dev/null
+++ b/lib/eal/riscv/include/rte_power_intrinsics.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_POWER_INTRINSIC_RISCV_H
+#define RTE_POWER_INTRINSIC_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_common.h>
+
+#include "generic/rte_power_intrinsics.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_POWER_INTRINSIC_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_prefetch.h b/lib/eal/riscv/include/rte_prefetch.h
new file mode 100644
index 0000000000..966d9e2687
--- /dev/null
+++ b/lib/eal/riscv/include/rte_prefetch.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2014 IBM Corporation
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_PREFETCH_RISCV_H
+#define RTE_PREFETCH_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_common.h>
+#include "generic/rte_prefetch.h"
+
+static inline void rte_prefetch0(const volatile void *p)
+{
+	RTE_SET_USED(p);
+}
+
+static inline void rte_prefetch1(const volatile void *p)
+{
+	RTE_SET_USED(p);
+}
+
+static inline void rte_prefetch2(const volatile void *p)
+{
+	RTE_SET_USED(p);
+}
+
+static inline void rte_prefetch_non_temporal(const volatile void *p)
+{
+	/* non-temporal version not available, fallback to rte_prefetch0 */
+	rte_prefetch0(p);
+}
+
+__rte_experimental
+static inline void
+rte_cldemote(const volatile void *p)
+{
+	RTE_SET_USED(p);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_PREFETCH_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_rwlock.h b/lib/eal/riscv/include/rte_rwlock.h
new file mode 100644
index 0000000000..9cdaf1b0ef
--- /dev/null
+++ b/lib/eal/riscv/include/rte_rwlock.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_RWLOCK_RISCV_H
+#define RTE_RWLOCK_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_rwlock.h"
+
+static inline void
+rte_rwlock_read_lock_tm(rte_rwlock_t *rwl)
+{
+	rte_rwlock_read_lock(rwl);
+}
+
+static inline void
+rte_rwlock_read_unlock_tm(rte_rwlock_t *rwl)
+{
+	rte_rwlock_read_unlock(rwl);
+}
+
+static inline void
+rte_rwlock_write_lock_tm(rte_rwlock_t *rwl)
+{
+	rte_rwlock_write_lock(rwl);
+}
+
+static inline void
+rte_rwlock_write_unlock_tm(rte_rwlock_t *rwl)
+{
+	rte_rwlock_write_unlock(rwl);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_RWLOCK_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_spinlock.h b/lib/eal/riscv/include/rte_spinlock.h
new file mode 100644
index 0000000000..6af430735c
--- /dev/null
+++ b/lib/eal/riscv/include/rte_spinlock.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015 RehiveTech. All rights reserved.
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_SPINLOCK_RISCV_H
+#define RTE_SPINLOCK_RISCV_H
+
+#ifndef RTE_FORCE_INTRINSICS
+#  error Platform must be built with RTE_FORCE_INTRINSICS
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_common.h>
+#include "generic/rte_spinlock.h"
+
+static inline int rte_tm_supported(void)
+{
+	return 0;
+}
+
+static inline void
+rte_spinlock_lock_tm(rte_spinlock_t *sl)
+{
+	rte_spinlock_lock(sl); /* fall-back */
+}
+
+static inline int
+rte_spinlock_trylock_tm(rte_spinlock_t *sl)
+{
+	return rte_spinlock_trylock(sl);
+}
+
+static inline void
+rte_spinlock_unlock_tm(rte_spinlock_t *sl)
+{
+	rte_spinlock_unlock(sl);
+}
+
+static inline void
+rte_spinlock_recursive_lock_tm(rte_spinlock_recursive_t *slr)
+{
+	rte_spinlock_recursive_lock(slr); /* fall-back */
+}
+
+static inline void
+rte_spinlock_recursive_unlock_tm(rte_spinlock_recursive_t *slr)
+{
+	rte_spinlock_recursive_unlock(slr);
+}
+
+static inline int
+rte_spinlock_recursive_trylock_tm(rte_spinlock_recursive_t *slr)
+{
+	return rte_spinlock_recursive_trylock(slr);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_SPINLOCK_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_ticketlock.h b/lib/eal/riscv/include/rte_ticketlock.h
new file mode 100644
index 0000000000..b8d2a4f937
--- /dev/null
+++ b/lib/eal/riscv/include/rte_ticketlock.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2019 Arm Limited
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_TICKETLOCK_RISCV_H
+#define RTE_TICKETLOCK_RISCV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_ticketlock.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_TICKETLOCK_RISCV_H */
diff --git a/lib/eal/riscv/include/rte_vect.h b/lib/eal/riscv/include/rte_vect.h
new file mode 100644
index 0000000000..4600521c20
--- /dev/null
+++ b/lib/eal/riscv/include/rte_vect.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#ifndef RTE_VECT_RISCV_H
+#define RTE_VECT_RISCV_H
+
+#include <stdint.h>
+#include "generic/rte_vect.h"
+#include "rte_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RTE_VECT_DEFAULT_SIMD_BITWIDTH RTE_VECT_SIMD_DISABLED
+
+typedef int32_t		xmm_t __attribute__((vector_size(16)));
+
+#define XMM_SIZE	(sizeof(xmm_t))
+#define XMM_MASK	(XMM_SIZE - 1)
+
+typedef union rte_xmm {
+	xmm_t		x;
+	uint8_t		u8[XMM_SIZE / sizeof(uint8_t)];
+	uint16_t	u16[XMM_SIZE / sizeof(uint16_t)];
+	uint32_t	u32[XMM_SIZE / sizeof(uint32_t)];
+	uint64_t	u64[XMM_SIZE / sizeof(uint64_t)];
+	double		pd[XMM_SIZE / sizeof(double)];
+} __rte_aligned(8) rte_xmm_t;
+
+static inline xmm_t
+vect_load_128(void *p)
+{
+	xmm_t ret = *((xmm_t *)p);
+	return ret;
+}
+
+static inline xmm_t
+vect_and(xmm_t data, xmm_t mask)
+{
+	rte_xmm_t ret = (rte_xmm_t)data;
+	rte_xmm_t m = (rte_xmm_t)mask;
+	ret.u64[0] &= m.u64[0];
+	ret.u64[1] &= m.u64[1];
+	return ret.x;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RTE_VECT_RISCV_H */
diff --git a/lib/eal/riscv/meson.build b/lib/eal/riscv/meson.build
new file mode 100644
index 0000000000..dca1106aae
--- /dev/null
+++ b/lib/eal/riscv/meson.build
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2017 Intel Corporation.
+
+subdir('include')
+
+sources += files(
+        'rte_cpuflags.c',
+        'rte_cycles.c',
+        'rte_hypervisor.c',
+        'rte_power_intrinsics.c',
+)
diff --git a/lib/eal/riscv/rte_cpuflags.c b/lib/eal/riscv/rte_cpuflags.c
new file mode 100644
index 0000000000..4f6d29b947
--- /dev/null
+++ b/lib/eal/riscv/rte_cpuflags.c
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#include "rte_cpuflags.h"
+
+#include <elf.h>
+#include <fcntl.h>
+#include <assert.h>
+#include <unistd.h>
+#include <string.h>
+
+#ifndef AT_HWCAP
+#define AT_HWCAP 16
+#endif
+
+#ifndef AT_HWCAP2
+#define AT_HWCAP2 26
+#endif
+
+#ifndef AT_PLATFORM
+#define AT_PLATFORM 15
+#endif
+
+enum cpu_register_t {
+	REG_NONE = 0,
+	REG_HWCAP,
+	REG_HWCAP2,
+	REG_PLATFORM,
+	REG_MAX
+};
+
+typedef uint32_t hwcap_registers_t[REG_MAX];
+
+/**
+ * Struct to hold a processor feature entry
+ */
+struct feature_entry {
+	uint32_t reg;
+	uint32_t bit;
+#define CPU_FLAG_NAME_MAX_LEN 64
+	char name[CPU_FLAG_NAME_MAX_LEN];
+};
+
+#define FEAT_DEF(name, reg, bit) \
+	[RTE_CPUFLAG_##name] = {reg, bit, #name},
+
+typedef Elf64_auxv_t _Elfx_auxv_t;
+
+const struct feature_entry rte_cpu_feature_table[] = {
+	FEAT_DEF(RISCV_ISA_A, REG_HWCAP,    0)
+	FEAT_DEF(RISCV_ISA_B, REG_HWCAP,    1)
+	FEAT_DEF(RISCV_ISA_C, REG_HWCAP,    2)
+	FEAT_DEF(RISCV_ISA_D, REG_HWCAP,    3)
+	FEAT_DEF(RISCV_ISA_E, REG_HWCAP,    4)
+	FEAT_DEF(RISCV_ISA_F, REG_HWCAP,    5)
+	FEAT_DEF(RISCV_ISA_G, REG_HWCAP,    6)
+	FEAT_DEF(RISCV_ISA_H, REG_HWCAP,    7)
+	FEAT_DEF(RISCV_ISA_I, REG_HWCAP,    8)
+	FEAT_DEF(RISCV_ISA_J, REG_HWCAP,    9)
+	FEAT_DEF(RISCV_ISA_K, REG_HWCAP,   10)
+	FEAT_DEF(RISCV_ISA_L, REG_HWCAP,   11)
+	FEAT_DEF(RISCV_ISA_M, REG_HWCAP,   12)
+	FEAT_DEF(RISCV_ISA_N, REG_HWCAP,   13)
+	FEAT_DEF(RISCV_ISA_O, REG_HWCAP,   14)
+	FEAT_DEF(RISCV_ISA_P, REG_HWCAP,   15)
+	FEAT_DEF(RISCV_ISA_Q, REG_HWCAP,   16)
+	FEAT_DEF(RISCV_ISA_R, REG_HWCAP,   17)
+	FEAT_DEF(RISCV_ISA_S, REG_HWCAP,   18)
+	FEAT_DEF(RISCV_ISA_T, REG_HWCAP,   19)
+	FEAT_DEF(RISCV_ISA_U, REG_HWCAP,   20)
+	FEAT_DEF(RISCV_ISA_V, REG_HWCAP,   21)
+	FEAT_DEF(RISCV_ISA_W, REG_HWCAP,   22)
+	FEAT_DEF(RISCV_ISA_X, REG_HWCAP,   23)
+	FEAT_DEF(RISCV_ISA_Y, REG_HWCAP,   24)
+	FEAT_DEF(RISCV_ISA_Z, REG_HWCAP,   25)
+};
+/*
+ * Read AUXV software register and get cpu features for ARM
+ */
+static void
+rte_cpu_get_features(hwcap_registers_t out)
+{
+	out[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP);
+	out[REG_HWCAP2] = rte_cpu_getauxval(AT_HWCAP2);
+}
+
+/*
+ * Checks if a particular flag is available on current machine.
+ */
+int
+rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
+{
+	const struct feature_entry *feat;
+	hwcap_registers_t regs = {0};
+
+	if (feature >= RTE_CPUFLAG_NUMFLAGS)
+		return -ENOENT;
+
+	feat = &rte_cpu_feature_table[feature];
+	if (feat->reg == REG_NONE)
+		return -EFAULT;
+
+	rte_cpu_get_features(regs);
+	return (regs[feat->reg] >> feat->bit) & 1;
+}
+
+const char *
+rte_cpu_get_flag_name(enum rte_cpu_flag_t feature)
+{
+	if (feature >= RTE_CPUFLAG_NUMFLAGS)
+		return NULL;
+	return rte_cpu_feature_table[feature].name;
+}
+
+void
+rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics)
+{
+	memset(intrinsics, 0, sizeof(*intrinsics));
+}
diff --git a/lib/eal/riscv/rte_cycles.c b/lib/eal/riscv/rte_cycles.c
new file mode 100644
index 0000000000..358f271311
--- /dev/null
+++ b/lib/eal/riscv/rte_cycles.c
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2015 Cavium, Inc
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#include <stdio.h>
+
+#include "eal_private.h"
+#include "rte_byteorder.h"
+#include "rte_cycles.h"
+#include "rte_log.h"
+
+/** Read generic counter frequency */
+static uint64_t
+__rte_riscv_timefrq(void)
+{
+#define TIMEBASE_FREQ_SIZE	8
+	if (RTE_RISCV_TIME_FREQ > 0)
+		return RTE_RISCV_TIME_FREQ;
+	uint8_t buf[TIMEBASE_FREQ_SIZE];
+	ssize_t cnt;
+	FILE *file;
+
+	file = fopen("/proc/device-tree/cpus/timebase-frequency", "rb");
+	if (!file)
+		goto fail;
+
+	cnt = fread(buf, 1, TIMEBASE_FREQ_SIZE, file);
+	fclose(file);
+	switch (cnt) {
+	case 8:
+		return rte_be_to_cpu_64(*(uint64_t *)buf);
+	case 4:
+		return rte_be_to_cpu_32(*(uint32_t *)buf);
+	default:
+		break;
+	}
+fail:
+	RTE_LOG(WARNING, EAL, "Unable to read timebase-frequency from FDT.\n");
+	return 0;
+}
+
+uint64_t
+get_tsc_freq_arch(void)
+{
+	RTE_LOG(NOTICE, EAL, "TSC using RISC-V %s.\n",
+		RTE_RISCV_RDTSC_USE_HPM ? "rdcycle" : "rdtime");
+	if (!RTE_RISCV_RDTSC_USE_HPM)
+		return __rte_riscv_timefrq();
+#define CYC_PER_1MHZ 1E6
+	/*
+	 * Use real time clock to estimate current cycle frequency
+	 */
+	uint64_t ticks, frq;
+	uint64_t start_ticks, cur_ticks;
+	uint64_t start_cycle, end_cycle;
+
+	/* Do not proceed unless clock frequency can be obtained. */
+	frq = __rte_riscv_timefrq();
+	if (!frq)
+		return 0;
+
+	/* Number of ticks for 1/10 second */
+	ticks = frq / 10;
+
+	start_ticks = __rte_riscv_rdtime_precise();
+	start_cycle = rte_rdtsc_precise();
+	do {
+		cur_ticks = __rte_riscv_rdtime();
+	} while ((cur_ticks - start_ticks) < ticks);
+	end_cycle = rte_rdtsc_precise();
+
+	/* Adjust the cycles to next 1Mhz */
+	return RTE_ALIGN_MUL_CEIL((end_cycle - start_cycle) * 10, CYC_PER_1MHZ);
+}
diff --git a/lib/eal/riscv/rte_hypervisor.c b/lib/eal/riscv/rte_hypervisor.c
new file mode 100644
index 0000000000..92b5435993
--- /dev/null
+++ b/lib/eal/riscv/rte_hypervisor.c
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#include "rte_hypervisor.h"
+
+enum rte_hypervisor
+rte_hypervisor_get(void)
+{
+	return RTE_HYPERVISOR_UNKNOWN;
+}
diff --git a/lib/eal/riscv/rte_power_intrinsics.c b/lib/eal/riscv/rte_power_intrinsics.c
new file mode 100644
index 0000000000..240e7b6b87
--- /dev/null
+++ b/lib/eal/riscv/rte_power_intrinsics.c
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 StarFive
+ * Copyright(c) 2022 SiFive
+ * Copyright(c) 2022 Semihalf
+ */
+
+#include "rte_power_intrinsics.h"
+
+/**
+ * This function is not supported on RISC-V 64
+ */
+int
+rte_power_monitor(const struct rte_power_monitor_cond *pmc,
+		  const uint64_t tsc_timestamp)
+{
+	RTE_SET_USED(pmc);
+	RTE_SET_USED(tsc_timestamp);
+
+	return -ENOTSUP;
+}
+
+/**
+ * This function is not supported on RISC-V 64
+ */
+int
+rte_power_pause(const uint64_t tsc_timestamp)
+{
+	RTE_SET_USED(tsc_timestamp);
+
+	return -ENOTSUP;
+}
+
+/**
+ * This function is not supported on RISC-V 64
+ */
+int
+rte_power_monitor_wakeup(const unsigned int lcore_id)
+{
+	RTE_SET_USED(lcore_id);
+
+	return -ENOTSUP;
+}
+
+/**
+ * This function is not supported on RISC-V 64
+ */
+int
+rte_power_monitor_multi(const struct rte_power_monitor_cond pmc[],
+			const uint32_t num, const uint64_t tsc_timestamp)
+{
+	RTE_SET_USED(pmc);
+	RTE_SET_USED(num);
+	RTE_SET_USED(tsc_timestamp);
+
+	return -ENOTSUP;
+}
diff --git a/meson.build b/meson.build
index 937f6110c0..a8db04a1ee 100644
--- a/meson.build
+++ b/meson.build
@@ -50,6 +50,8 @@ elif host_machine.cpu_family().startswith('arm') or host_machine.cpu_family().st
     arch_subdir = 'arm'
 elif host_machine.cpu_family().startswith('ppc')
     arch_subdir = 'ppc'
+elif host_machine.cpu_family().startswith('riscv')
+    arch_subdir = 'riscv'
 endif
 
 # configure the build, and make sure configs here and in config folder are
-- 
2.30.2

Re: [PATCH v3 1/8] eal: add initial support for RISC-V architecture

[Heinrich Schuchardt]

On 5/10/22 17:48, Stanislaw Kardach wrote:
> From: Michal Mazurek <maz@semihalf.com>
> 
> Add all necessary elements for DPDK to compile and run EAL on SiFive
> Freedom U740 SoC which is based on SiFive U74-MC (ISA: rv64imafdc)
> core complex.
> 
> This includes:
> 
> - EAL library implementation for rv64imafdc ISA.
> - meson build structure for 'riscv' architecture. RTE_ARCH_RISCV define
>    is added for architecture identification.
> - xmm_t structure operation stubs as there is no vector support in the
>    U74 core.
> 
> Compilation was tested on Ubuntu and Arch Linux using riscv64 toolchain.
> Clang compilation currently not supported due to issues with missing
> relocation relaxation.
> 
> Two rte_rdtsc() schemes are provided: stable low-resolution using rdtime
> (default) and unstable high-resolution using rdcycle. User can override
> the scheme by defining RTE_RISCV_RDTSC_USE_HPM=1 during compile time of
> both DPDK and the application. The reasoning for this is as follows.
> The RISC-V ISA mandates that clock read by rdtime has to be of constant
> period and synchronized between all hardware threads within 1 tick
> (chapter 10.1 in version 20191213 of RISC-V spec).
> However this clock may not be of high-enough frequency for dataplane
> uses. I.e. on HiFive Unmatched (FU740) it is 1MHz.
> There is a high-resolution alternative in form of rdcycle which is
> clocked at the core clock frequency. The drawbacks are that it may be
> disabled during sleep (WFI) and its frequency might change due to DVFS.
> 
> The platform is currently marked as linux-only because rte_cycles
> implementation uses the timebase-frequency device-tree node read through
> the proc file system. Such approach was chosen because Linux kernel
> depends on the presence of this device-tree node.
> 
> The i40e PMD driver is disabled on RISC-V as the rv64gc ISA has no vector
> operations.
> 
> The compilation of following modules has been disabled by this commit
> and will be re-enabled in later commits as fixes are introduced:
> net/ixgbe, net/memif, net/tap, example/l3fwd.
> 
> Known checkpatch errors/warnings:
> 
> - ERROR:COMPLEX_MACRO in rte_atomic.h and rte_cycles.h due to inline
>    assembly declarations.
> - vector_size compiler attribute used in rte_vect.h directly.
> - rte_*mb() used directly in rte_atomic.h to reduce code duplication.
> - __atomic_thread_fence() used to implement rte_atomic_thread_fence().
> 
> Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
> Sponsored-by: Sam Grove <sam.grove@sifive.com>
> Signed-off-by: Michal Mazurek <maz@semihalf.com>
> Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
> ---
> Depends-on: series-22867 ("test/ring: remove excessive inlining")
> Depends-on: series-22868 ("lpm: add a scalar version of lookupx4 function")
> Depends-on: series-22869 ("examples/l3fwd: fix scalar LPM compilation")
> ---
>   MAINTAINERS                                   |   6 +
>   app/test/test_xmmt_ops.h                      |  16 ++
>   config/meson.build                            |   2 +
>   config/riscv/meson.build                      | 143 ++++++++++++++++++
>   config/riscv/riscv64_linux_gcc                |  17 +++
>   config/riscv/riscv64_sifive_u740_linux_gcc    |  19 +++
>   doc/guides/contributing/design.rst            |   2 +-
>   .../linux_gsg/cross_build_dpdk_for_riscv.rst  | 125 +++++++++++++++
>   doc/guides/linux_gsg/index.rst                |   1 +
>   doc/guides/nics/features.rst                  |   5 +
>   doc/guides/nics/features/default.ini          |   1 +
>   doc/guides/rel_notes/release_22_07.rst        |   8 +
>   drivers/net/i40e/meson.build                  |   6 +
>   drivers/net/ixgbe/meson.build                 |   6 +
>   drivers/net/memif/meson.build                 |   5 +
>   drivers/net/tap/meson.build                   |   5 +
>   examples/l3fwd/meson.build                    |   6 +
>   lib/eal/riscv/include/meson.build             |  23 +++
>   lib/eal/riscv/include/rte_atomic.h            |  52 +++++++
>   lib/eal/riscv/include/rte_byteorder.h         |  44 ++++++
>   lib/eal/riscv/include/rte_cpuflags.h          |  55 +++++++
>   lib/eal/riscv/include/rte_cycles.h            | 105 +++++++++++++
>   lib/eal/riscv/include/rte_io.h                |  21 +++
>   lib/eal/riscv/include/rte_mcslock.h           |  18 +++
>   lib/eal/riscv/include/rte_memcpy.h            |  63 ++++++++
>   lib/eal/riscv/include/rte_pause.h             |  31 ++++
>   lib/eal/riscv/include/rte_pflock.h            |  17 +++
>   lib/eal/riscv/include/rte_power_intrinsics.h  |  22 +++
>   lib/eal/riscv/include/rte_prefetch.h          |  50 ++++++
>   lib/eal/riscv/include/rte_rwlock.h            |  44 ++++++
>   lib/eal/riscv/include/rte_spinlock.h          |  67 ++++++++
>   lib/eal/riscv/include/rte_ticketlock.h        |  21 +++
>   lib/eal/riscv/include/rte_vect.h              |  55 +++++++
>   lib/eal/riscv/meson.build                     |  11 ++
>   lib/eal/riscv/rte_cpuflags.c                  | 122 +++++++++++++++
>   lib/eal/riscv/rte_cycles.c                    |  77 ++++++++++
>   lib/eal/riscv/rte_hypervisor.c                |  13 ++
>   lib/eal/riscv/rte_power_intrinsics.c          |  56 +++++++
>   meson.build                                   |   2 +
>   39 files changed, 1341 insertions(+), 1 deletion(-)
>   create mode 100644 config/riscv/meson.build
>   create mode 100644 config/riscv/riscv64_linux_gcc
>   create mode 100644 config/riscv/riscv64_sifive_u740_linux_gcc
>   create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
>   create mode 100644 lib/eal/riscv/include/meson.build
>   create mode 100644 lib/eal/riscv/include/rte_atomic.h
>   create mode 100644 lib/eal/riscv/include/rte_byteorder.h
>   create mode 100644 lib/eal/riscv/include/rte_cpuflags.h
>   create mode 100644 lib/eal/riscv/include/rte_cycles.h
>   create mode 100644 lib/eal/riscv/include/rte_io.h
>   create mode 100644 lib/eal/riscv/include/rte_mcslock.h
>   create mode 100644 lib/eal/riscv/include/rte_memcpy.h
>   create mode 100644 lib/eal/riscv/include/rte_pause.h
>   create mode 100644 lib/eal/riscv/include/rte_pflock.h
>   create mode 100644 lib/eal/riscv/include/rte_power_intrinsics.h
>   create mode 100644 lib/eal/riscv/include/rte_prefetch.h
>   create mode 100644 lib/eal/riscv/include/rte_rwlock.h
>   create mode 100644 lib/eal/riscv/include/rte_spinlock.h
>   create mode 100644 lib/eal/riscv/include/rte_ticketlock.h
>   create mode 100644 lib/eal/riscv/include/rte_vect.h
>   create mode 100644 lib/eal/riscv/meson.build
>   create mode 100644 lib/eal/riscv/rte_cpuflags.c
>   create mode 100644 lib/eal/riscv/rte_cycles.c
>   create mode 100644 lib/eal/riscv/rte_hypervisor.c
>   create mode 100644 lib/eal/riscv/rte_power_intrinsics.c
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 8f4e9c3479..7fb6dccc41 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -296,6 +296,12 @@ F: drivers/*/*/*_altivec.*
>   F: app/*/*_altivec.*
>   F: examples/*/*_altivec.*
>   
> +RISC-V
> +M: Stanislaw Kardach <kda@semihalf.com>
> +F: config/riscv/
> +F: doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
> +F: lib/eal/riscv/
> +
>   Intel x86
>   M: Bruce Richardson <bruce.richardson@intel.com>
>   M: Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>
> diff --git a/app/test/test_xmmt_ops.h b/app/test/test_xmmt_ops.h
> index 3a82d5ecac..55f256599e 100644
> --- a/app/test/test_xmmt_ops.h
> +++ b/app/test/test_xmmt_ops.h
> @@ -1,5 +1,8 @@
>   /* SPDX-License-Identifier: BSD-3-Clause
>    * Copyright(c) 2015 Cavium, Inc
> + * Copyright(c) 2022 StarFive
> + * Copyright(c) 2022 SiFive
> + * Copyright(c) 2022 Semihalf
>    */
>   
>   #ifndef _TEST_XMMT_OPS_H_
> @@ -49,6 +52,19 @@ vect_set_epi32(int i3, int i2, int i1, int i0)
>   	return data;
>   }
>   
> +#elif defined(RTE_ARCH_RISCV)
> +
> +#define vect_loadu_sil128(p) vect_load_128(p)
> +
> +/* sets the 4 signed 32-bit integer values and returns the xmm_t variable */
> +static __rte_always_inline xmm_t
> +vect_set_epi32(int i3, int i2, int i1, int i0)
> +{
> +	xmm_t data = (xmm_t){i0, i1, i2, i3};
> +
> +	return data;
> +}
> +
>   #endif
>   
>   #endif /* _TEST_XMMT_OPS_H_ */
> diff --git a/config/meson.build b/config/meson.build
> index 7134e80e8d..7f7b6c92fd 100644
> --- a/config/meson.build
> +++ b/config/meson.build
> @@ -121,6 +121,8 @@ if cpu_instruction_set == 'generic'
>           cpu_instruction_set = 'generic'
>       elif host_machine.cpu_family().startswith('ppc')
>           cpu_instruction_set = 'power8'
> +    elif host_machine.cpu_family().startswith('riscv')
> +        cpu_instruction_set = 'riscv'
>       endif
>   endif
>   
> diff --git a/config/riscv/meson.build b/config/riscv/meson.build
> new file mode 100644
> index 0000000000..0c16c31fc2
> --- /dev/null
> +++ b/config/riscv/meson.build
> @@ -0,0 +1,143 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(c) 2017 Intel Corporation.
> +# Copyright(c) 2017 Cavium, Inc
> +# Copyright(c) 2021 PANTHEON.tech s.r.o.
> +# Copyright(c) 2022 StarFive
> +# Copyright(c) 2022 SiFive
> +# Copyright(c) 2022 Semihalf
> +
> +if not is_linux
> +    error('Only Linux is supported at this point in time.')
> +endif
> +
> +if not dpdk_conf.get('RTE_ARCH_64')
> +    error('Only 64-bit compiles are supported for this platform type')
> +endif
> +
> +dpdk_conf.set('RTE_ARCH', 'riscv')
> +dpdk_conf.set('RTE_ARCH_RISCV', 1)
> +dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
> +
> +# common flags to all riscv builds, with lowest priority
> +flags_common = [
> +    ['RTE_ARCH_RISCV', true],
> +    ['RTE_CACHE_LINE_SIZE', 64],
> +    # Set this to true if target emulates U-mode TIME CSR via M or S mode trap.
> +    # This allows to remove a FENCE on rte_rdtsc_precise() as trap effectively
> +    # acts as one.
> +    ['RTE_RISCV_EMU_UTIME', false],
> +    # Set this to true if target emulates U-mode CYCLE CSR via M or S mode trap.
> +    # This allows to remove a FENCE on rte_rdtsc_precise() as trap effectively
> +    # acts as one.
> +    ['RTE_RISCV_EMU_UCYCLE', false],
> +    # Manually set wall time clock frequency for the target. If 0, then it is
> +    # read from /proc/device-tree/cpus/timebase-frequency. This property is
> +    # guaranteed on Linux, as riscv time_init() requires it.
> +    ['RTE_RISCV_TIME_FREQ', 0],
> +]
> +
> +## SoC-specific options.
> +# The priority is like this: arch > vendor > common.
> +#
> +# Note that currently there's no way of getting vendor/microarchitecture id
> +# values in userspace which is why the logic of choosing the right flag
> +# combination is strictly based on the values passed from a cross-file.
> +vendor_generic = {
> +    'description': 'Generic RISC-V',
> +    'flags': [
> +        ['RTE_MACHINE', '"riscv"'],
> +        ['RTE_USE_C11_MEM_MODEL', true],
> +        ['RTE_MAX_LCORE', 128],
> +        ['RTE_MAX_NUMA_NODES', 2]
> +    ],
> +    'arch_config': {
> +        'generic': {'machine_args': ['-march=rv64gc']}
> +    }
> +}
> +
> +arch_config_riscv = {
> +    '0x8000000000000007': {
> +        'machine_args':  ['-march=rv64gc', '-mtune=sifive-7-series'],
> +        'flags': [
> +            ['RTE_RISCV_EMU_UTIME', true],
> +            ['RTE_RISCV_EMU_UCYCLE', true]
> +        ]
> +    },
> +}
> +
> +vendor_sifive = {
> +    'description': 'SiFive',
> +    'flags': [
> +        ['RTE_MACHINE', '"riscv"'],
> +        ['RTE_USE_C11_MEM_MODEL', true],
> +        ['RTE_MAX_LCORE', 4],
> +        ['RTE_MAX_NUMA_NODES', 1],
> +    ],
> +    'arch_config': arch_config_riscv
> +}
> +
> +vendors = {
> +    'generic': vendor_generic,
> +    '0x489': vendor_sifive
> +}
> +
> +# Native/cross vendor/arch detection
> +if not meson.is_cross_build()
> +    if machine == 'default'
> +        # default build
> +        vendor_id = 'generic'
> +        arch_id = 'generic'
> +        message('generic RISC-V')
> +    else
> +        vendor_id = 'generic'
> +        arch_id = 'generic'
> +        warning('RISC-V arch discovery not available, using generic!')
> +    endif
> +else
> +    # cross build
> +    vendor_id = meson.get_cross_property('vendor_id')
> +    arch_id = meson.get_cross_property('arch_id')
> +endif
> +
> +if vendors.has_key(vendor_id)
> +    vendor_config = vendors[vendor_id]
> +else
> +    error('Unsupported RISC-V vendor: @0@. '.format(vendor_id) +
> +        'Please add support for it or use the generic ' +
> +        '(-Dmachine=generic) build.')
> +endif
> +
> +message('RISC-V vendor: ' + vendor_config['description'])
> +message('RISC-V architecture id: ' + arch_id)
> +
> +arch_config = vendor_config['arch_config']
> +if arch_config.has_key(arch_id)
> +    # use the specified arch_id machine args if found
> +    arch_config = arch_config[arch_id]
> +else
> +    # unknown micro-architecture id
> +    error('Unsupported architecture @0@ of vendor @1@. '
> +        .format(arch_id, vendor_id) +
> +        'Please add support for it or use the generic ' +
> +        '(-Dmachine=generic) build.')
> +endif
> +
> +# Concatenate flags respecting priorities.
> +dpdk_flags = flags_common + vendor_config['flags'] + arch_config.get('flags', [])
> +
> +# apply supported machine args
> +machine_args = [] # Clear previous machine args
> +foreach flag: arch_config['machine_args']
> +    if cc.has_argument(flag)
> +        machine_args += flag
> +    endif
> +endforeach
> +
> +# apply flags
> +foreach flag: dpdk_flags
> +    if flag.length() > 0
> +        dpdk_conf.set(flag[0], flag[1])
> +    endif
> +endforeach
> +message('Using machine args: @0@'.format(machine_args))
> +
> diff --git a/config/riscv/riscv64_linux_gcc b/config/riscv/riscv64_linux_gcc
> new file mode 100644
> index 0000000000..04248d7ecb
> --- /dev/null
> +++ b/config/riscv/riscv64_linux_gcc
> @@ -0,0 +1,17 @@
> +[binaries]
> +c = 'riscv64-linux-gnu-gcc'
> +cpp = 'riscv64-linux-gnu-g++'
> +ar = 'riscv64-linux-gnu-ar'
> +strip = 'riscv64-linux-gnu-strip'
> +pcap-config = ''
> +pkgconfig = 'riscv64-linux-gnu-pkg-config'
> +
> +[host_machine]
> +system = 'linux'
> +cpu_family = 'riscv64'
> +cpu = 'rv64gc'
> +endian = 'little'
> +
> +[properties]
> +vendor_id = 'generic'
> +arch_id = 'generic'
> diff --git a/config/riscv/riscv64_sifive_u740_linux_gcc b/config/riscv/riscv64_sifive_u740_linux_gcc
> new file mode 100644
> index 0000000000..7b5ad2562d
> --- /dev/null
> +++ b/config/riscv/riscv64_sifive_u740_linux_gcc
> @@ -0,0 +1,19 @@
> +[binaries]
> +c = 'riscv64-unknown-linux-gnu-gcc'
> +cpp = 'riscv64-unknown-linux-gnu-g++'
> +ar = 'riscv64-unknown-linux-gnu-ar'
> +strip = 'riscv64-unknown-linux-gnu-strip'
> +pcap-config = ''
> +pkgconfig = 'riscv64-unknown-linux-gnu-pkg-config'
> +
> +[host_machine]
> +system = 'linux'
> +cpu_family = 'riscv64'
> +cpu = 'rv64gc'
> +endian = 'little'
> +
> +[properties]
> +vendor_id = '0x489'
> +arch_id = '0x8000000000000007'
> +max_lcores = 4
> +max_numa_nodes = 1
> diff --git a/doc/guides/contributing/design.rst b/doc/guides/contributing/design.rst
> index d5ca8b4d9c..0383afe5c8 100644
> --- a/doc/guides/contributing/design.rst
> +++ b/doc/guides/contributing/design.rst
> @@ -42,7 +42,7 @@ Per Architecture Sources
>   The following macro options can be used:
>   
>   * ``RTE_ARCH`` is a string that contains the name of the architecture.
> -* ``RTE_ARCH_I686``, ``RTE_ARCH_X86_64``, ``RTE_ARCH_X86_X32``, ``RTE_ARCH_PPC_64``, ``RTE_ARCH_ARM``, ``RTE_ARCH_ARMv7`` or ``RTE_ARCH_ARM64`` are defined only if we are building for those architectures.
> +* ``RTE_ARCH_I686``, ``RTE_ARCH_X86_64``, ``RTE_ARCH_X86_X32``, ``RTE_ARCH_PPC_64``, ``RTE_ARCH_RISCV``, ``RTE_ARCH_ARM``, ``RTE_ARCH_ARMv7`` or ``RTE_ARCH_ARM64`` are defined only if we are building for those architectures.
>   
>   Per Execution Environment Sources
>   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> diff --git a/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst b/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
> new file mode 100644
> index 0000000000..9907b35a1d
> --- /dev/null
> +++ b/doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
> @@ -0,0 +1,125 @@
> +..  SPDX-License-Identifier: BSD-3-Clause
> +    Copyright(c) 2020 ARM Corporation.
> +    Copyright(c) 2022 StarFive
> +    Copyright(c) 2022 SiFive
> +    Copyright(c) 2022 Semihalf
> +
> +Cross compiling DPDK for RISC-V
> +===============================
> +
> +This chapter describes how to cross compile DPDK for RISC-V from x86 build
> +hosts.
> +
> +.. note::
> +
> +   While it's possible to compile DPDK natively on a RISC-V host, it is
> +   currently recommended to cross-compile as Linux kernel does not offer any
> +   way for userspace to discover the vendor and architecture identifiers of the
> +   CPU and therefore any per-chip optimization options have to be chosen via
> +   a cross-file or ``c_args``.
> +
> +
> +Prerequisites
> +-------------
> +
> +
> +Linux kernel
> +~~~~~~~~~~~~
> +
> +It is recommended to use Linux kernel built from
> +`SiFive Freedom Unleashed SDK <https://github.com/sifive/freedom-u-sdk>`_.

How would the Unleashed SDK help on a later board or a board from a 
different vendor?

Why wouldn't an upstream kernel work?

I suggest to eliminate this misleading section.

> +
> +
> +Meson prerequisites
> +~~~~~~~~~~~~~~~~~~~
> +
> +Meson depends on pkgconfig to find the dependencies.
> +The package ``pkg-config-riscv64-linux-gnu`` is required for RISC-V.
> +To install it in Ubuntu::
> +
> +   sudo apt install pkg-config-riscv64-linux-gnu

This package does not exist in the current Ubuntu LTS (22.04, Jammy).

Setting environment variables PKG_CONFIG_LIBDIR, PKG_CONFIG_PATH, 
PKG_CONFIG_SYSROOT_DIR properly should do the job with the normal 
pkg-config.

> +
> +
> +GNU toolchain
> +-------------
> +
> +
> +Obtain the cross toolchain
> +~~~~~~~~~~~~~~~~~~~~~~~~~~
> +
> +The build process was tested using:
> +
> +* Ubuntu toolchain (the ``crossbuild-essential-riscv64`` package).
> +
> +* Latest `RISC-V GNU toolchain
> +  <https://github.com/riscv/riscv-gnu-toolchain/releases>`_ on Ubuntu or Arch
> +  Linux.
> +
> +Alternatively the toolchain may be built straight from the source, to do that
> +follow the instructions on the riscv-gnu-toolchain github page.
> +
> +
> +Unzip and add into the PATH
> +~~~~~~~~~~~~~~~~~~~~~~~~~~~
> +
> +This step is only required for the riscv-gnu-toolchain. The Ubuntu toolchain is
> +in the PATH already.
> +
> +.. code-block:: console
> +
> +   tar -xvf riscv64-glibc-ubuntu-20.04-<version>.tar.gz

You can install the glibc package with apt-get after adding the 
architecture with sudo dpkg --add-architecture riscv64. See 
https://wiki.debian.org/CrossCompiling.

> +   export PATH=$PATH:<cross_install_dir>/riscv/bin
> +
> +
> +Cross Compiling DPDK with GNU toolchain using Meson
> +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> +
> +To cross-compile DPDK for a desired target machine use the following command::
> +
> +   meson cross-build --cross-file <target_machine_configuration>
> +   ninja -C cross-build
> +
> +For example if the target machine is a generic rv64gc RISC-V, use the following
> +command::
> +
> +   meson riscv64-build-gcc --cross-file config/riscv/riscv64_linux_gcc
> +   ninja -C riscv64-build-gcc
> +
> +If riscv-gnu-toolchain is used, binary names should be updated to match. Update the following lines in the cross-file:
> +
> +.. code-block:: console
> +
> +   [binaries]
> +   c = 'riscv64-unknown-linux-gnu-gcc'
> +   cpp = 'riscv64-unknown-linux-gnu-g++'
> +   ar = 'riscv64-unknown-linux-gnu-ar'
> +   strip = 'riscv64-unknown-linux-gnu-strip'
> +   ...
> +
> +Some toolchains (such as freedom-u-sdk one) require also setting ``--sysroot``,
> +otherwise include paths might not be resolved. To do so, add the appropriate
> +paths to the cross-file:
> +
> +.. code-block:: console
> +
> +   [properties]
> +   ...
> +   c_args = ['--sysroot', '<path/to/toolchain/sysroot>']
> +   cpp_args = c_args
> +   c_link_args = ['--sysroot', '<path/to/toolchain/sysroot>']
> +   cpp_link_args = c_link_args
> +   ...
> +
> +
> +Supported cross-compilation targets
> +-----------------------------------
> +
> +Currently the following targets are supported:
> +
> +* Generic rv64gc ISA: ``config/riscv/riscv64_linux_gcc``
> +
> +* SiFive U740 SoC: ``config/riscv/riscv64_sifive_u740_linux_gcc``

Why do we need a special config for the Unmatched board that is not sold 
anymore? Doesn't the Unmatched board work with the genenric config?

I assume a single configuriation file for the generic target is enough.

Best regards

Heinrich

> +
> +To add a new target support, ``config/riscv/meson.build`` has to be modified by
> +adding a new vendor/architecture id and a corresponding cross-file has to be
> +added to ``config/riscv`` directory.
> diff --git a/doc/guides/linux_gsg/index.rst b/doc/guides/linux_gsg/index.rst
> index 16a9a67260..747552c385 100644
> --- a/doc/guides/linux_gsg/index.rst
> +++ b/doc/guides/linux_gsg/index.rst
> @@ -14,6 +14,7 @@ Getting Started Guide for Linux
>       sys_reqs
>       build_dpdk
>       cross_build_dpdk_for_arm64
> +    cross_build_dpdk_for_riscv
>       linux_drivers
>       build_sample_apps
>       linux_eal_parameters
> diff --git a/doc/guides/nics/features.rst b/doc/guides/nics/features.rst
> index 21bedb743f..6c4fa74bc7 100644
> --- a/doc/guides/nics/features.rst
> +++ b/doc/guides/nics/features.rst
> @@ -855,6 +855,11 @@ x86-64
>   
>   Support 64bits x86 architecture.
>   
> +rv64
> +----
> +
> +Support 64-bit RISC-V architecture.
> +
>   
>   .. _nic_features_usage_doc:
>   
> diff --git a/doc/guides/nics/features/default.ini b/doc/guides/nics/features/default.ini
> index b1d18ac62c..02198682c6 100644
> --- a/doc/guides/nics/features/default.ini
> +++ b/doc/guides/nics/features/default.ini
> @@ -74,6 +74,7 @@ ARMv8                =
>   Power8               =
>   x86-32               =
>   x86-64               =
> +rv64                 =
>   Usage doc            =
>   Design doc           =
>   Perf doc             =
> diff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst
> index 4ae91dd94d..e014247bc0 100644
> --- a/doc/guides/rel_notes/release_22_07.rst
> +++ b/doc/guides/rel_notes/release_22_07.rst
> @@ -55,6 +55,14 @@ New Features
>        Also, make sure to start the actual text at the margin.
>        =======================================================
>   
> +* **Added initial RISC-V architecture support.***
> +
> +  Added EAL implementation for RISC-V architecture. The initial device the
> +  porting was tested on is a HiFive Unmatched development board based on the
> +  SiFive Freedom U740 SoC. In theory this implementation should work with any
> +  ``rv64gc`` ISA compatible implementation with MMU supporting a reasonable
> +  address space size (U740 uses sv39 MMU).
> +
>   * **Updated Intel iavf driver.**
>   
>     * Added Tx QoS queue rate limitation support.
> diff --git a/drivers/net/i40e/meson.build b/drivers/net/i40e/meson.build
> index efc5f93e35..a4c1c9079a 100644
> --- a/drivers/net/i40e/meson.build
> +++ b/drivers/net/i40e/meson.build
> @@ -1,6 +1,12 @@
>   # SPDX-License-Identifier: BSD-3-Clause
>   # Copyright(c) 2017 Intel Corporation
>   
> +if arch_subdir == 'riscv'
> +		build = false
> +		reason = 'riscv arch not supported'
> +		subdir_done()
> +endif
> +
>   cflags += ['-DPF_DRIVER',
>       '-DVF_DRIVER',
>       '-DINTEGRATED_VF',
> diff --git a/drivers/net/ixgbe/meson.build b/drivers/net/ixgbe/meson.build
> index 162f8d5f46..88539e97d5 100644
> --- a/drivers/net/ixgbe/meson.build
> +++ b/drivers/net/ixgbe/meson.build
> @@ -1,6 +1,12 @@
>   # SPDX-License-Identifier: BSD-3-Clause
>   # Copyright(c) 2017 Intel Corporation
>   
> +if arch_subdir == 'riscv'
> +		build = false
> +		reason = 'riscv arch not supported'
> +		subdir_done()
> +endif
> +
>   cflags += ['-DRTE_LIBRTE_IXGBE_BYPASS']
>   
>   subdir('base')
> diff --git a/drivers/net/memif/meson.build b/drivers/net/memif/meson.build
> index 680bc8631c..9afb495953 100644
> --- a/drivers/net/memif/meson.build
> +++ b/drivers/net/memif/meson.build
> @@ -5,6 +5,11 @@ if not is_linux
>       build = false
>       reason = 'only supported on Linux'
>   endif
> +if arch_subdir == 'riscv'
> +		build = false
> +		reason = 'riscv arch not supported'
> +		subdir_done()
> +endif
>   
>   sources = files(
>           'memif_socket.c',
> diff --git a/drivers/net/tap/meson.build b/drivers/net/tap/meson.build
> index c09713a67b..3efac9ac07 100644
> --- a/drivers/net/tap/meson.build
> +++ b/drivers/net/tap/meson.build
> @@ -5,6 +5,11 @@ if not is_linux
>       build = false
>       reason = 'only supported on Linux'
>   endif
> +if arch_subdir == 'riscv'
> +		build = false
> +		reason = 'riscv arch not supported'
> +		subdir_done()
> +endif
>   sources = files(
>           'rte_eth_tap.c',
>           'tap_bpf_api.c',
> diff --git a/examples/l3fwd/meson.build b/examples/l3fwd/meson.build
> index 0830b3eb31..75fa19b7fe 100644
> --- a/examples/l3fwd/meson.build
> +++ b/examples/l3fwd/meson.build
> @@ -6,6 +6,12 @@
>   # To build this example as a standalone application with an already-installed
>   # DPDK instance, use 'make'
>   
> +if dpdk_conf.has('RTE_ARCH_RISCV')
> +		build = false
> +		reason = 'riscv arch not supported'
> +		subdir_done()
> +endif
> +
>   allow_experimental_apis = true
>   deps += ['hash', 'lpm', 'fib', 'eventdev']
>   sources = files(
> diff --git a/lib/eal/riscv/include/meson.build b/lib/eal/riscv/include/meson.build
> new file mode 100644
> index 0000000000..7f6e4a5b1e
> --- /dev/null
> +++ b/lib/eal/riscv/include/meson.build
> @@ -0,0 +1,23 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(c) 2022 StarFive
> +# Copyright(c) 2022 SiFive
> +# Copyright(c) 2022 Semihalf
> +
> +arch_headers = files(
> +        'rte_atomic.h',
> +        'rte_byteorder.h',
> +        'rte_cpuflags.h',
> +        'rte_cycles.h',
> +        'rte_io.h',
> +        'rte_mcslock.h',
> +        'rte_memcpy.h',
> +        'rte_pause.h',
> +        'rte_pflock.h',
> +        'rte_power_intrinsics.h',
> +        'rte_prefetch.h',
> +        'rte_rwlock.h',
> +        'rte_spinlock.h',
> +        'rte_ticketlock.h',
> +        'rte_vect.h',
> +)
> +install_headers(arch_headers, subdir: get_option('include_subdir_arch'))
> diff --git a/lib/eal/riscv/include/rte_atomic.h b/lib/eal/riscv/include/rte_atomic.h
> new file mode 100644
> index 0000000000..4b4633c914
> --- /dev/null
> +++ b/lib/eal/riscv/include/rte_atomic.h
> @@ -0,0 +1,52 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2022 StarFive
> + * Copyright(c) 2022 SiFive
> + * Copyright(c) 2022 Semihalf
> + * All rights reserved.
> + */
> +
> +#ifndef RTE_ATOMIC_RISCV_H
> +#define RTE_ATOMIC_RISCV_H
> +
> +#ifndef RTE_FORCE_INTRINSICS
> +#  error Platform must be built with RTE_FORCE_INTRINSICS
> +#endif
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#include <stdint.h>
> +#include <rte_common.h>
> +#include <rte_config.h>
> +#include "generic/rte_atomic.h"
> +
> +#define rte_mb()	asm volatile("fence rw, rw" : : : "memory")
> +
> +#define rte_wmb()	asm volatile("fence w, w" : : : "memory")
> +
> +#define rte_rmb()	asm volatile("fence r, r" : : : "memory")
> +
> +#define rte_smp_mb()	rte_mb()
> +
> +#define rte_smp_wmb()	rte_wmb()
> +
> +#define rte_smp_rmb()	rte_rmb()
> +
> +#define rte_io_mb()	asm volatile("fence iorw, iorw" : : : "memory")
> +
> +#define rte_io_wmb()	asm volatile("fence orw, ow" : : : "memory")
> +
> +#define rte_io_rmb()	asm volatile("fence ir, ir" : : : "memory")
> +
> +static __rte_always_inline void
> +rte_atomic_thread_fence(int memorder)
> +{
> +	__atomic_thread_fence(memorder);
> +}
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* RTE_ATOMIC_RISCV_H */
> diff --git a/lib/eal/riscv/include/rte_byteorder.h b/lib/eal/riscv/include/rte_byteorder.h
> new file mode 100644
> index 0000000000..21893505d6
> --- /dev/null
> +++ b/lib/eal/riscv/include/rte_byteorder.h
> @@ -0,0 +1,44 @@
> +/*
> + * SPDX-License-Identifier: BSD-3-Clause
> + * Inspired from FreeBSD src/sys/powerpc/include/endian.h
> + * Copyright(c) 1987, 1991, 1993
> + * The Regents of the University of California.  All rights reserved.
> + */
> +
> +#ifndef RTE_BYTEORDER_RISCV_H
> +#define RTE_BYTEORDER_RISCV_H
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#include <stdint.h>
> +#include <rte_common.h>
> +#include "generic/rte_byteorder.h"
> +
> +#ifndef RTE_BYTE_ORDER
> +#define RTE_BYTE_ORDER RTE_LITTLE_ENDIAN
> +#endif
> +
> +#define rte_cpu_to_le_16(x) (x)
> +#define rte_cpu_to_le_32(x) (x)
> +#define rte_cpu_to_le_64(x) (x)
> +
> +#define rte_cpu_to_be_16(x) rte_bswap16(x)
> +#define rte_cpu_to_be_32(x) rte_bswap32(x)
> +#define rte_cpu_to_be_64(x) rte_bswap64(x)
> +
> +#define rte_le_to_cpu_16(x) (x)
> +#define rte_le_to_cpu_32(x) (x)
> +#define rte_le_to_cpu_64(x) (x)
> +
> +#define rte_be_to_cpu_16(x) rte_bswap16(x)
> +#define rte_be_to_cpu_32(x) rte_bswap32(x)
> +#define rte_be_to_cpu_64(x) rte_bswap64(x)
> +
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* RTE_BYTEORDER_RISCV_H */
> diff --git a/lib/eal/riscv/include/rte_cpuflags.h b/lib/eal/riscv/include/rte_cpuflags.h
> new file mode 100644
> index 0000000000..66e787f898
> --- /dev/null
> +++ b/lib/eal/riscv/include/rte_cpuflags.h
> @@ -0,0 +1,55 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2014 IBM Corporation
> + * Copyright(c) 2022 StarFive
> + * Copyright(c) 2022 SiFive
> + * Copyright(c) 2022 Semihalf
> + */
> +
> +#ifndef RTE_CPUFLAGS_RISCV_H
> +#define RTE_CPUFLAGS_RISCV_H
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/**
> + * Enumeration of all CPU features supported
> + */
> +enum rte_cpu_flag_t {
> +	RTE_CPUFLAG_RISCV_ISA_A, /* Atomic */
> +	RTE_CPUFLAG_RISCV_ISA_B, /* Bit-Manipulation */
> +	RTE_CPUFLAG_RISCV_ISA_C, /* Compressed instruction */
> +	RTE_CPUFLAG_RISCV_ISA_D, /* Double precision floating-point  */
> +	RTE_CPUFLAG_RISCV_ISA_E, /* RV32E ISA */
> +	RTE_CPUFLAG_RISCV_ISA_F, /* Single precision floating-point */
> +	RTE_CPUFLAG_RISCV_ISA_G, /* Extension pack (IMAFD, Zicsr, Zifencei) */
> +	RTE_CPUFLAG_RISCV_ISA_H, /* Hypervisor */
> +	RTE_CPUFLAG_RISCV_ISA_I, /* RV32I/RV64I/IRV128I base ISA */
> +	RTE_CPUFLAG_RISCV_ISA_J, /* Dynamic Translation Language */
> +	RTE_CPUFLAG_RISCV_ISA_K, /* Reserved */
> +	RTE_CPUFLAG_RISCV_ISA_L, /* Decimal Floating-Point */
> +	RTE_CPUFLAG_RISCV_ISA_M, /* Integer Multiply/Divide */
> +	RTE_CPUFLAG_RISCV_ISA_N, /* User-level interrupts */
> +	RTE_CPUFLAG_RISCV_ISA_O, /* Reserved */
> +	RTE_CPUFLAG_RISCV_ISA_P, /* Packed-SIMD */
> +	RTE_CPUFLAG_RISCV_ISA_Q, /* Quad-precision floating-points */
> +	RTE_CPUFLAG_RISCV_ISA_R, /* Reserved */
> +	RTE_CPUFLAG_RISCV_ISA_S, /* Supervisor mode */
> +	RTE_CPUFLAG_RISCV_ISA_T, /* Transactional memory */
> +	RTE_CPUFLAG_RISCV_ISA_U, /* User mode */
> +	RTE_CPUFLAG_RISCV_ISA_V, /* Vector */
> +	RTE_CPUFLAG_RISCV_ISA_W, /* Reserved */
> +	RTE_CPUFLAG_RISCV_ISA_X, /* Non-standard extension present */
> +	RTE_CPUFLAG_RISCV_ISA_Y, /* Reserved */
> +	RTE_CPUFLAG_RISCV_ISA_Z, /* Reserved */
> +	/* The last item */
> +	RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */
> +};
> +
> +#include "generic/rte_cpuflags.h"
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* RTE_CPUFLAGS_RISCV_H */
> diff --git a/lib/eal/riscv/include/rte_cycles.h b/lib/eal/riscv/include/rte_cycles.h
> new file mode 100644
> index 0000000000..8353cea853
> --- /dev/null
> +++ b/lib/eal/riscv/include/rte_cycles.h
> @@ -0,0 +1,105 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2015 Cavium, Inc
> + * Copyright(c) 2022 StarFive
> + * Copyright(c) 2022 SiFive
> + * Copyright(c) 2022 Semihalf
> + */
> +
> +#ifndef RTE_CYCLES_RISCV_H
> +#define RTE_CYCLES_RISCV_H
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#include "generic/rte_cycles.h"
> +
> +#ifndef RTE_RISCV_RDTSC_USE_HPM
> +#define RTE_RISCV_RDTSC_USE_HPM 0
> +#endif
> +
> +#define RV64_CSRR(reg, value) \
> +	asm volatile("csrr %0, " #reg : "=r" (value) : : "memory")
> +
> +/** Read wall time counter */
> +static __rte_always_inline uint64_t
> +__rte_riscv_rdtime(void)
> +{
> +	uint64_t tsc;
> +	RV64_CSRR(time, tsc);
> +	return tsc;
> +}
> +
> +/** Read wall time counter ensuring no re-ordering */
> +static __rte_always_inline uint64_t
> +__rte_riscv_rdtime_precise(void)
> +{
> +#if !defined(RTE_RISCV_EMU_UTIME)
> +	asm volatile("fence" : : : "memory");
> +#endif
> +	return __rte_riscv_rdtime();
> +}
> +
> +/** Read hart cycle counter */
> +static __rte_always_inline uint64_t
> +__rte_riscv_rdcycle(void)
> +{
> +	uint64_t tsc;
> +	RV64_CSRR(cycle, tsc);
> +	return tsc;
> +}
> +
> +/** Read hart cycle counter ensuring no re-ordering */
> +static __rte_always_inline uint64_t
> +__rte_riscv_rdcycle_precise(void)
> +{
> +#if !defined(RTE_RISCV_EMU_UCYCLE)
> +	asm volatile("fence" : : : "memory");
> +#endif
> +	return __rte_riscv_rdcycle();
> +}
> +
> +/**
> + * Read the time base register.
> + *
> + * @return
> + *   The time base for this lcore.
> + */
> +static __rte_always_inline uint64_t
> +rte_rdtsc(void)
> +{
> +	/**
> +	 * By default TIME userspace counter is used. Although it's frequency
> +	 * may not be enough for all applications.
> +	 */
> +	if (!RTE_RISCV_RDTSC_USE_HPM)
> +		return __rte_riscv_rdtime();
> +	/**
> +	 * Alternatively HPM's CYCLE counter may be used. However this counter
> +	 * is not guaranteed by ISA to either be stable frequency or always
> +	 * enabled for userspace access (it may trap to kernel or firmware).
> +	 */
> +	return __rte_riscv_rdcycle();
> +}
> +
> +static inline uint64_t
> +rte_rdtsc_precise(void)
> +{
> +	if (!RTE_RISCV_RDTSC_USE_HPM)
> +		return __rte_riscv_rdtime_precise();
> +	return __rte_riscv_rdcycle_precise();
> +}
> +
> +static __rte_always_inline uint64_t
> +rte_get_tsc_cycles(void)
> +{
> +	return rte_rdtsc();
> +}
> +
> +#undef RV64_CSRR
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* RTE_CYCLES_RISCV_H */
> diff --git a/lib/eal/riscv/include/rte_io.h b/lib/eal/riscv/include/rte_io.h
> new file mode 100644
> index 0000000000..29659c9590
> --- /dev/null
> +++ b/lib/eal/riscv/include/rte_io.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2016 Cavium, Inc
> + * Copyright(c) 2022 StarFive
> + * Copyright(c) 2022 SiFive
> + * Copyright(c) 2022 Semihalf
> + */
> +
> +#ifndef RTE_IO_RISCV_H
> +#define RTE_IO_RISCV_H
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#include "generic/rte_io.h"
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* RTE_IO_RISCV_H */
> diff --git a/lib/eal/riscv/include/rte_mcslock.h b/lib/eal/riscv/include/rte_mcslock.h
> new file mode 100644
> index 0000000000..b517cd5fc5
> --- /dev/null
> +++ b/lib/eal/riscv/include/rte_mcslock.h
> @@ -0,0 +1,18 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2019 Arm Limited
> + */
> +
> +#ifndef RTE_MCSLOCK_RISCV_H
> +#define RTE_MCSLOCK_RISCV_H
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#include "generic/rte_mcslock.h"
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* RTE_MCSLOCK_RISCV_H */
> diff --git a/lib/eal/riscv/include/rte_memcpy.h b/lib/eal/riscv/include/rte_memcpy.h
> new file mode 100644
> index 0000000000..e34f19396e
> --- /dev/null
> +++ b/lib/eal/riscv/include/rte_memcpy.h
> @@ -0,0 +1,63 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2022 StarFive
> + * Copyright(c) 2022 SiFive
> + * Copyright(c) 2022 Semihalf
> + */
> +
> +#ifndef RTE_MEMCPY_RISCV_H
> +#define RTE_MEMCPY_RISCV_H
> +
> +#include <stdint.h>
> +#include <string.h>
> +
> +#include "rte_common.h"
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#include "generic/rte_memcpy.h"
> +
> +static inline void
> +rte_mov16(uint8_t *dst, const uint8_t *src)
> +{
> +	memcpy(dst, src, 16);
> +}
> +
> +static inline void
> +rte_mov32(uint8_t *dst, const uint8_t *src)
> +{
> +	memcpy(dst, src, 32);
> +}
> +
> +static inline void
> +rte_mov48(uint8_t *dst, const uint8_t *src)
> +{
> +	memcpy(dst, src, 48);
> +}
> +
> +static inline void
> +rte_mov64(uint8_t *dst, const uint8_t *src)
> +{
> +	memcpy(dst, src, 64);
> +}
> +
> +static inline void
> +rte_mov128(uint8_t *dst, const uint8_t *src)
> +{
> +	memcpy(dst, src, 128);
> +}
> +
> +static inline void
> +rte_mov256(uint8_t *dst, const uint8_t *src)
> +{
> +	memcpy(dst, src, 256);
> +}
> +
> +#define rte_memcpy(d, s, n)	memcpy((d), (s), (n))
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* RTE_MEMCPY_RISCV_H */
> diff --git a/lib/eal/riscv/include/rte_pause.h b/lib/eal/riscv/include/rte_pause.h
> new file mode 100644
> index 0000000000..c24c1f32e8
> --- /dev/null
> +++ b/lib/eal/riscv/include/rte_pause.h
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2022 StarFive
> + * Copyright(c) 2022 SiFive
> + * Copyright(c) 2022 Semihalf
> + */
> +
> +#ifndef RTE_PAUSE_RISCV_H
> +#define RTE_PAUSE_RISCV_H
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#include "rte_atomic.h"
> +
> +#include "generic/rte_pause.h"
> +
> +static inline void rte_pause(void)
> +{
> +	/* Insert pause hint directly to be compatible with old compilers.
> +	 * This will work even on platforms without Zihintpause extension
> +	 * because this is a FENCE hint instruction which evaluates to NOP then.
> +	 */
> +	asm volatile(".int 0x0100000F"::: "memory");
> +}
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* RTE_PAUSE_RISCV_H */
> diff --git a/lib/eal/riscv/include/rte_pflock.h b/lib/eal/riscv/include/rte_pflock.h
> new file mode 100644
> index 0000000000..ce6ca02aca
> --- /dev/null
> +++ b/lib/eal/riscv/include/rte_pflock.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2021 Microsoft Corporation
> + */
> +#ifndef RTE_PFLOCK_RISCV_H
> +#define RTE_PFLOCK_RISCV_H
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#include "generic/rte_pflock.h"
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* RTE_PFLOCK_RISCV_H */
> diff --git a/lib/eal/riscv/include/rte_power_intrinsics.h b/lib/eal/riscv/include/rte_power_intrinsics.h
> new file mode 100644
> index 0000000000..636e58e71f
> --- /dev/null
> +++ b/lib/eal/riscv/include/rte_power_intrinsics.h
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2022 StarFive
> + * Copyright(c) 2022 SiFive
> + * Copyright(c) 2022 Semihalf
> + */
> +
> +#ifndef RTE_POWER_INTRINSIC_RISCV_H
> +#define RTE_POWER_INTRINSIC_RISCV_H
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#include <rte_common.h>
> +
> +#include "generic/rte_power_intrinsics.h"
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* RTE_POWER_INTRINSIC_RISCV_H */
> diff --git a/lib/eal/riscv/include/rte_prefetch.h b/lib/eal/riscv/include/rte_prefetch.h
> new file mode 100644
> index 0000000000..966d9e2687
> --- /dev/null
> +++ b/lib/eal/riscv/include/rte_prefetch.h
> @@ -0,0 +1,50 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2014 IBM Corporation
> + * Copyright(c) 2022 StarFive
> + * Copyright(c) 2022 SiFive
> + * Copyright(c) 2022 Semihalf
> + */
> +
> +#ifndef RTE_PREFETCH_RISCV_H
> +#define RTE_PREFETCH_RISCV_H
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#include <rte_common.h>
> +#include "generic/rte_prefetch.h"
> +
> +static inline void rte_prefetch0(const volatile void *p)
> +{
> +	RTE_SET_USED(p);
> +}
> +
> +static inline void rte_prefetch1(const volatile void *p)
> +{
> +	RTE_SET_USED(p);
> +}
> +
> +static inline void rte_prefetch2(const volatile void *p)
> +{
> +	RTE_SET_USED(p);
> +}
> +
> +static inline void rte_prefetch_non_temporal(const volatile void *p)
> +{
> +	/* non-temporal version not available, fallback to rte_prefetch0 */
> +	rte_prefetch0(p);
> +}
> +
> +__rte_experimental
> +static inline void
> +rte_cldemote(const volatile void *p)
> +{
> +	RTE_SET_USED(p);
> +}
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* RTE_PREFETCH_RISCV_H */
> diff --git a/lib/eal/riscv/include/rte_rwlock.h b/lib/eal/riscv/include/rte_rwlock.h
> new file mode 100644
> index 0000000000..9cdaf1b0ef
> --- /dev/null
> +++ b/lib/eal/riscv/include/rte_rwlock.h
> @@ -0,0 +1,44 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2022 StarFive
> + * Copyright(c) 2022 SiFive
> + * Copyright(c) 2022 Semihalf
> + */
> +
> +#ifndef RTE_RWLOCK_RISCV_H
> +#define RTE_RWLOCK_RISCV_H
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#include "generic/rte_rwlock.h"
> +
> +static inline void
> +rte_rwlock_read_lock_tm(rte_rwlock_t *rwl)
> +{
> +	rte_rwlock_read_lock(rwl);
> +}
> +
> +static inline void
> +rte_rwlock_read_unlock_tm(rte_rwlock_t *rwl)
> +{
> +	rte_rwlock_read_unlock(rwl);
> +}
> +
> +static inline void
> +rte_rwlock_write_lock_tm(rte_rwlock_t *rwl)
> +{
> +	rte_rwlock_write_lock(rwl);
> +}
> +
> +static inline void
> +rte_rwlock_write_unlock_tm(rte_rwlock_t *rwl)
> +{
> +	rte_rwlock_write_unlock(rwl);
> +}
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* RTE_RWLOCK_RISCV_H */
> diff --git a/lib/eal/riscv/include/rte_spinlock.h b/lib/eal/riscv/include/rte_spinlock.h
> new file mode 100644
> index 0000000000..6af430735c
> --- /dev/null
> +++ b/lib/eal/riscv/include/rte_spinlock.h
> @@ -0,0 +1,67 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2015 RehiveTech. All rights reserved.
> + * Copyright(c) 2022 StarFive
> + * Copyright(c) 2022 SiFive
> + * Copyright(c) 2022 Semihalf
> + */
> +
> +#ifndef RTE_SPINLOCK_RISCV_H
> +#define RTE_SPINLOCK_RISCV_H
> +
> +#ifndef RTE_FORCE_INTRINSICS
> +#  error Platform must be built with RTE_FORCE_INTRINSICS
> +#endif
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#include <rte_common.h>
> +#include "generic/rte_spinlock.h"
> +
> +static inline int rte_tm_supported(void)
> +{
> +	return 0;
> +}
> +
> +static inline void
> +rte_spinlock_lock_tm(rte_spinlock_t *sl)
> +{
> +	rte_spinlock_lock(sl); /* fall-back */
> +}
> +
> +static inline int
> +rte_spinlock_trylock_tm(rte_spinlock_t *sl)
> +{
> +	return rte_spinlock_trylock(sl);
> +}
> +
> +static inline void
> +rte_spinlock_unlock_tm(rte_spinlock_t *sl)
> +{
> +	rte_spinlock_unlock(sl);
> +}
> +
> +static inline void
> +rte_spinlock_recursive_lock_tm(rte_spinlock_recursive_t *slr)
> +{
> +	rte_spinlock_recursive_lock(slr); /* fall-back */
> +}
> +
> +static inline void
> +rte_spinlock_recursive_unlock_tm(rte_spinlock_recursive_t *slr)
> +{
> +	rte_spinlock_recursive_unlock(slr);
> +}
> +
> +static inline int
> +rte_spinlock_recursive_trylock_tm(rte_spinlock_recursive_t *slr)
> +{
> +	return rte_spinlock_recursive_trylock(slr);
> +}
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* RTE_SPINLOCK_RISCV_H */
> diff --git a/lib/eal/riscv/include/rte_ticketlock.h b/lib/eal/riscv/include/rte_ticketlock.h
> new file mode 100644
> index 0000000000..b8d2a4f937
> --- /dev/null
> +++ b/lib/eal/riscv/include/rte_ticketlock.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2019 Arm Limited
> + * Copyright(c) 2022 StarFive
> + * Copyright(c) 2022 SiFive
> + * Copyright(c) 2022 Semihalf
> + */
> +
> +#ifndef RTE_TICKETLOCK_RISCV_H
> +#define RTE_TICKETLOCK_RISCV_H
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#include "generic/rte_ticketlock.h"
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* RTE_TICKETLOCK_RISCV_H */
> diff --git a/lib/eal/riscv/include/rte_vect.h b/lib/eal/riscv/include/rte_vect.h
> new file mode 100644
> index 0000000000..4600521c20
> --- /dev/null
> +++ b/lib/eal/riscv/include/rte_vect.h
> @@ -0,0 +1,55 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2022 StarFive
> + * Copyright(c) 2022 SiFive
> + * Copyright(c) 2022 Semihalf
> + */
> +
> +#ifndef RTE_VECT_RISCV_H
> +#define RTE_VECT_RISCV_H
> +
> +#include <stdint.h>
> +#include "generic/rte_vect.h"
> +#include "rte_common.h"
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#define RTE_VECT_DEFAULT_SIMD_BITWIDTH RTE_VECT_SIMD_DISABLED
> +
> +typedef int32_t		xmm_t __attribute__((vector_size(16)));
> +
> +#define XMM_SIZE	(sizeof(xmm_t))
> +#define XMM_MASK	(XMM_SIZE - 1)
> +
> +typedef union rte_xmm {
> +	xmm_t		x;
> +	uint8_t		u8[XMM_SIZE / sizeof(uint8_t)];
> +	uint16_t	u16[XMM_SIZE / sizeof(uint16_t)];
> +	uint32_t	u32[XMM_SIZE / sizeof(uint32_t)];
> +	uint64_t	u64[XMM_SIZE / sizeof(uint64_t)];
> +	double		pd[XMM_SIZE / sizeof(double)];
> +} __rte_aligned(8) rte_xmm_t;
> +
> +static inline xmm_t
> +vect_load_128(void *p)
> +{
> +	xmm_t ret = *((xmm_t *)p);
> +	return ret;
> +}
> +
> +static inline xmm_t
> +vect_and(xmm_t data, xmm_t mask)
> +{
> +	rte_xmm_t ret = (rte_xmm_t)data;
> +	rte_xmm_t m = (rte_xmm_t)mask;
> +	ret.u64[0] &= m.u64[0];
> +	ret.u64[1] &= m.u64[1];
> +	return ret.x;
> +}
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* RTE_VECT_RISCV_H */
> diff --git a/lib/eal/riscv/meson.build b/lib/eal/riscv/meson.build
> new file mode 100644
> index 0000000000..dca1106aae
> --- /dev/null
> +++ b/lib/eal/riscv/meson.build
> @@ -0,0 +1,11 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(c) 2017 Intel Corporation.
> +
> +subdir('include')
> +
> +sources += files(
> +        'rte_cpuflags.c',
> +        'rte_cycles.c',
> +        'rte_hypervisor.c',
> +        'rte_power_intrinsics.c',
> +)
> diff --git a/lib/eal/riscv/rte_cpuflags.c b/lib/eal/riscv/rte_cpuflags.c
> new file mode 100644
> index 0000000000..4f6d29b947
> --- /dev/null
> +++ b/lib/eal/riscv/rte_cpuflags.c
> @@ -0,0 +1,122 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2022 StarFive
> + * Copyright(c) 2022 SiFive
> + * Copyright(c) 2022 Semihalf
> + */
> +
> +#include "rte_cpuflags.h"
> +
> +#include <elf.h>
> +#include <fcntl.h>
> +#include <assert.h>
> +#include <unistd.h>
> +#include <string.h>
> +
> +#ifndef AT_HWCAP
> +#define AT_HWCAP 16
> +#endif
> +
> +#ifndef AT_HWCAP2
> +#define AT_HWCAP2 26
> +#endif
> +
> +#ifndef AT_PLATFORM
> +#define AT_PLATFORM 15
> +#endif
> +
> +enum cpu_register_t {
> +	REG_NONE = 0,
> +	REG_HWCAP,
> +	REG_HWCAP2,
> +	REG_PLATFORM,
> +	REG_MAX
> +};
> +
> +typedef uint32_t hwcap_registers_t[REG_MAX];
> +
> +/**
> + * Struct to hold a processor feature entry
> + */
> +struct feature_entry {
> +	uint32_t reg;
> +	uint32_t bit;
> +#define CPU_FLAG_NAME_MAX_LEN 64
> +	char name[CPU_FLAG_NAME_MAX_LEN];
> +};
> +
> +#define FEAT_DEF(name, reg, bit) \
> +	[RTE_CPUFLAG_##name] = {reg, bit, #name},
> +
> +typedef Elf64_auxv_t _Elfx_auxv_t;
> +
> +const struct feature_entry rte_cpu_feature_table[] = {
> +	FEAT_DEF(RISCV_ISA_A, REG_HWCAP,    0)
> +	FEAT_DEF(RISCV_ISA_B, REG_HWCAP,    1)
> +	FEAT_DEF(RISCV_ISA_C, REG_HWCAP,    2)
> +	FEAT_DEF(RISCV_ISA_D, REG_HWCAP,    3)
> +	FEAT_DEF(RISCV_ISA_E, REG_HWCAP,    4)
> +	FEAT_DEF(RISCV_ISA_F, REG_HWCAP,    5)
> +	FEAT_DEF(RISCV_ISA_G, REG_HWCAP,    6)
> +	FEAT_DEF(RISCV_ISA_H, REG_HWCAP,    7)
> +	FEAT_DEF(RISCV_ISA_I, REG_HWCAP,    8)
> +	FEAT_DEF(RISCV_ISA_J, REG_HWCAP,    9)
> +	FEAT_DEF(RISCV_ISA_K, REG_HWCAP,   10)
> +	FEAT_DEF(RISCV_ISA_L, REG_HWCAP,   11)
> +	FEAT_DEF(RISCV_ISA_M, REG_HWCAP,   12)
> +	FEAT_DEF(RISCV_ISA_N, REG_HWCAP,   13)
> +	FEAT_DEF(RISCV_ISA_O, REG_HWCAP,   14)
> +	FEAT_DEF(RISCV_ISA_P, REG_HWCAP,   15)
> +	FEAT_DEF(RISCV_ISA_Q, REG_HWCAP,   16)
> +	FEAT_DEF(RISCV_ISA_R, REG_HWCAP,   17)
> +	FEAT_DEF(RISCV_ISA_S, REG_HWCAP,   18)
> +	FEAT_DEF(RISCV_ISA_T, REG_HWCAP,   19)
> +	FEAT_DEF(RISCV_ISA_U, REG_HWCAP,   20)
> +	FEAT_DEF(RISCV_ISA_V, REG_HWCAP,   21)
> +	FEAT_DEF(RISCV_ISA_W, REG_HWCAP,   22)
> +	FEAT_DEF(RISCV_ISA_X, REG_HWCAP,   23)
> +	FEAT_DEF(RISCV_ISA_Y, REG_HWCAP,   24)
> +	FEAT_DEF(RISCV_ISA_Z, REG_HWCAP,   25)
> +};
> +/*
> + * Read AUXV software register and get cpu features for ARM
> + */
> +static void
> +rte_cpu_get_features(hwcap_registers_t out)
> +{
> +	out[REG_HWCAP] = rte_cpu_getauxval(AT_HWCAP);
> +	out[REG_HWCAP2] = rte_cpu_getauxval(AT_HWCAP2);
> +}
> +
> +/*
> + * Checks if a particular flag is available on current machine.
> + */
> +int
> +rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
> +{
> +	const struct feature_entry *feat;
> +	hwcap_registers_t regs = {0};
> +
> +	if (feature >= RTE_CPUFLAG_NUMFLAGS)
> +		return -ENOENT;
> +
> +	feat = &rte_cpu_feature_table[feature];
> +	if (feat->reg == REG_NONE)
> +		return -EFAULT;
> +
> +	rte_cpu_get_features(regs);
> +	return (regs[feat->reg] >> feat->bit) & 1;
> +}
> +
> +const char *
> +rte_cpu_get_flag_name(enum rte_cpu_flag_t feature)
> +{
> +	if (feature >= RTE_CPUFLAG_NUMFLAGS)
> +		return NULL;
> +	return rte_cpu_feature_table[feature].name;
> +}
> +
> +void
> +rte_cpu_get_intrinsics_support(struct rte_cpu_intrinsics *intrinsics)
> +{
> +	memset(intrinsics, 0, sizeof(*intrinsics));
> +}
> diff --git a/lib/eal/riscv/rte_cycles.c b/lib/eal/riscv/rte_cycles.c
> new file mode 100644
> index 0000000000..358f271311
> --- /dev/null
> +++ b/lib/eal/riscv/rte_cycles.c
> @@ -0,0 +1,77 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2015 Cavium, Inc
> + * Copyright(c) 2022 StarFive
> + * Copyright(c) 2022 SiFive
> + * Copyright(c) 2022 Semihalf
> + */
> +
> +#include <stdio.h>
> +
> +#include "eal_private.h"
> +#include "rte_byteorder.h"
> +#include "rte_cycles.h"
> +#include "rte_log.h"
> +
> +/** Read generic counter frequency */
> +static uint64_t
> +__rte_riscv_timefrq(void)
> +{
> +#define TIMEBASE_FREQ_SIZE	8
> +	if (RTE_RISCV_TIME_FREQ > 0)
> +		return RTE_RISCV_TIME_FREQ;
> +	uint8_t buf[TIMEBASE_FREQ_SIZE];
> +	ssize_t cnt;
> +	FILE *file;
> +
> +	file = fopen("/proc/device-tree/cpus/timebase-frequency", "rb");
> +	if (!file)
> +		goto fail;
> +
> +	cnt = fread(buf, 1, TIMEBASE_FREQ_SIZE, file);
> +	fclose(file);
> +	switch (cnt) {
> +	case 8:
> +		return rte_be_to_cpu_64(*(uint64_t *)buf);
> +	case 4:
> +		return rte_be_to_cpu_32(*(uint32_t *)buf);
> +	default:
> +		break;
> +	}
> +fail:
> +	RTE_LOG(WARNING, EAL, "Unable to read timebase-frequency from FDT.\n");
> +	return 0;
> +}
> +
> +uint64_t
> +get_tsc_freq_arch(void)
> +{
> +	RTE_LOG(NOTICE, EAL, "TSC using RISC-V %s.\n",
> +		RTE_RISCV_RDTSC_USE_HPM ? "rdcycle" : "rdtime");
> +	if (!RTE_RISCV_RDTSC_USE_HPM)
> +		return __rte_riscv_timefrq();
> +#define CYC_PER_1MHZ 1E6
> +	/*
> +	 * Use real time clock to estimate current cycle frequency
> +	 */
> +	uint64_t ticks, frq;
> +	uint64_t start_ticks, cur_ticks;
> +	uint64_t start_cycle, end_cycle;
> +
> +	/* Do not proceed unless clock frequency can be obtained. */
> +	frq = __rte_riscv_timefrq();
> +	if (!frq)
> +		return 0;
> +
> +	/* Number of ticks for 1/10 second */
> +	ticks = frq / 10;
> +
> +	start_ticks = __rte_riscv_rdtime_precise();
> +	start_cycle = rte_rdtsc_precise();
> +	do {
> +		cur_ticks = __rte_riscv_rdtime();
> +	} while ((cur_ticks - start_ticks) < ticks);
> +	end_cycle = rte_rdtsc_precise();
> +
> +	/* Adjust the cycles to next 1Mhz */
> +	return RTE_ALIGN_MUL_CEIL((end_cycle - start_cycle) * 10, CYC_PER_1MHZ);
> +}
> diff --git a/lib/eal/riscv/rte_hypervisor.c b/lib/eal/riscv/rte_hypervisor.c
> new file mode 100644
> index 0000000000..92b5435993
> --- /dev/null
> +++ b/lib/eal/riscv/rte_hypervisor.c
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2022 StarFive
> + * Copyright(c) 2022 SiFive
> + * Copyright(c) 2022 Semihalf
> + */
> +
> +#include "rte_hypervisor.h"
> +
> +enum rte_hypervisor
> +rte_hypervisor_get(void)
> +{
> +	return RTE_HYPERVISOR_UNKNOWN;
> +}
> diff --git a/lib/eal/riscv/rte_power_intrinsics.c b/lib/eal/riscv/rte_power_intrinsics.c
> new file mode 100644
> index 0000000000..240e7b6b87
> --- /dev/null
> +++ b/lib/eal/riscv/rte_power_intrinsics.c
> @@ -0,0 +1,56 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2022 StarFive
> + * Copyright(c) 2022 SiFive
> + * Copyright(c) 2022 Semihalf
> + */
> +
> +#include "rte_power_intrinsics.h"
> +
> +/**
> + * This function is not supported on RISC-V 64
> + */
> +int
> +rte_power_monitor(const struct rte_power_monitor_cond *pmc,
> +		  const uint64_t tsc_timestamp)
> +{
> +	RTE_SET_USED(pmc);
> +	RTE_SET_USED(tsc_timestamp);
> +
> +	return -ENOTSUP;
> +}
> +
> +/**
> + * This function is not supported on RISC-V 64
> + */
> +int
> +rte_power_pause(const uint64_t tsc_timestamp)
> +{
> +	RTE_SET_USED(tsc_timestamp);
> +
> +	return -ENOTSUP;
> +}
> +
> +/**
> + * This function is not supported on RISC-V 64
> + */
> +int
> +rte_power_monitor_wakeup(const unsigned int lcore_id)
> +{
> +	RTE_SET_USED(lcore_id);
> +
> +	return -ENOTSUP;
> +}
> +
> +/**
> + * This function is not supported on RISC-V 64
> + */
> +int
> +rte_power_monitor_multi(const struct rte_power_monitor_cond pmc[],
> +			const uint32_t num, const uint64_t tsc_timestamp)
> +{
> +	RTE_SET_USED(pmc);
> +	RTE_SET_USED(num);
> +	RTE_SET_USED(tsc_timestamp);
> +
> +	return -ENOTSUP;
> +}
> diff --git a/meson.build b/meson.build
> index 937f6110c0..a8db04a1ee 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -50,6 +50,8 @@ elif host_machine.cpu_family().startswith('arm') or host_machine.cpu_family().st
>       arch_subdir = 'arm'
>   elif host_machine.cpu_family().startswith('ppc')
>       arch_subdir = 'ppc'
> +elif host_machine.cpu_family().startswith('riscv')
> +    arch_subdir = 'riscv'
>   endif
>   
>   # configure the build, and make sure configs here and in config folder are

Re: [PATCH v3 1/8] eal: add initial support for RISC-V architecture

[Stanisław Kardach]

On Fri, May 13, 2022 at 8:50 AM Heinrich Schuchardt
<heinrich.schuchardt@canonical.com> wrote:
<snip>
> > +Linux kernel
> > +~~~~~~~~~~~~
> > +
> > +It is recommended to use Linux kernel built from
> > +`SiFive Freedom Unleashed SDK <https://github.com/sifive/freedom-u-sdk>`_.
>
> How would the Unleashed SDK help on a later board or a board from a
> different vendor?
This SDK is for both Unleashed and Unmatched. The naming is a bit misleading.
>
> Why wouldn't an upstream kernel work?
At the point of writing it was missing patches related to PCI resource
mapping exposure to userspace. Right now it's there.
>
> I suggest to eliminate this misleading section.
I'll re-test with the latest upstream kernel and rephrase that this
should work with Linux kernel >= x.y.z.
>
> > +
> > +
> > +Meson prerequisites
> > +~~~~~~~~~~~~~~~~~~~
> > +
> > +Meson depends on pkgconfig to find the dependencies.
> > +The package ``pkg-config-riscv64-linux-gnu`` is required for RISC-V.
> > +To install it in Ubuntu::
> > +
> > +   sudo apt install pkg-config-riscv64-linux-gnu
>
> This package does not exist in the current Ubuntu LTS (22.04, Jammy).
>
> Setting environment variables PKG_CONFIG_LIBDIR, PKG_CONFIG_PATH,
> PKG_CONFIG_SYSROOT_DIR properly should do the job with the normal
> pkg-config.
Do you happen to know why was this package removed?
Given that, is there a Ubuntu manual page or tool somewhere specifying
the correct values to obtain for a given arch?

>
> > +
> > +
> > +GNU toolchain
> > +-------------
> > +
> > +
> > +Obtain the cross toolchain
> > +~~~~~~~~~~~~~~~~~~~~~~~~~~
> > +
> > +The build process was tested using:
> > +
> > +* Ubuntu toolchain (the ``crossbuild-essential-riscv64`` package).
> > +
> > +* Latest `RISC-V GNU toolchain
> > +  <https://github.com/riscv/riscv-gnu-toolchain/releases>`_ on Ubuntu or Arch
> > +  Linux.
> > +
> > +Alternatively the toolchain may be built straight from the source, to do that
> > +follow the instructions on the riscv-gnu-toolchain github page.
> > +
> > +
> > +Unzip and add into the PATH
> > +~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > +
> > +This step is only required for the riscv-gnu-toolchain. The Ubuntu toolchain is
> > +in the PATH already.
> > +
> > +.. code-block:: console
> > +
> > +   tar -xvf riscv64-glibc-ubuntu-20.04-<version>.tar.gz
>
> You can install the glibc package with apt-get after adding the
> architecture with sudo dpkg --add-architecture riscv64. See
> https://wiki.debian.org/CrossCompiling.
>
This guide is supposed to target also Arch where this toolchain should
work properly. That's why in previous section I'm mentioning
crossbuild-essential-riscv64 and RISC-V GNU toolchain from github
separately.
> > +   export PATH=$PATH:<cross_install_dir>/riscv/bin
> > +
> > +
> > +Cross Compiling DPDK with GNU toolchain using Meson
> > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > +
> > +To cross-compile DPDK for a desired target machine use the following command::
> > +
> > +   meson cross-build --cross-file <target_machine_configuration>
> > +   ninja -C cross-build
> > +
> > +For example if the target machine is a generic rv64gc RISC-V, use the following
> > +command::
> > +
> > +   meson riscv64-build-gcc --cross-file config/riscv/riscv64_linux_gcc
> > +   ninja -C riscv64-build-gcc
> > +
> > +If riscv-gnu-toolchain is used, binary names should be updated to match. Update the following lines in the cross-file:
> > +
> > +.. code-block:: console
> > +
> > +   [binaries]
> > +   c = 'riscv64-unknown-linux-gnu-gcc'
> > +   cpp = 'riscv64-unknown-linux-gnu-g++'
> > +   ar = 'riscv64-unknown-linux-gnu-ar'
> > +   strip = 'riscv64-unknown-linux-gnu-strip'
> > +   ...
> > +
> > +Some toolchains (such as freedom-u-sdk one) require also setting ``--sysroot``,
> > +otherwise include paths might not be resolved. To do so, add the appropriate
> > +paths to the cross-file:
> > +
> > +.. code-block:: console
> > +
> > +   [properties]
> > +   ...
> > +   c_args = ['--sysroot', '<path/to/toolchain/sysroot>']
> > +   cpp_args = c_args
> > +   c_link_args = ['--sysroot', '<path/to/toolchain/sysroot>']
> > +   cpp_link_args = c_link_args
> > +   ...
> > +
> > +
> > +Supported cross-compilation targets
> > +-----------------------------------
> > +
> > +Currently the following targets are supported:
> > +
> > +* Generic rv64gc ISA: ``config/riscv/riscv64_linux_gcc``
> > +
> > +* SiFive U740 SoC: ``config/riscv/riscv64_sifive_u740_linux_gcc``
>
> Why do we need a special config for the Unmatched board that is not sold
> anymore? Doesn't the Unmatched board work with the genenric config?
I wasn't aware that they did discontinue it. As far as I can see it's
due to supply chain issues, maybe that means it'll get back? Generic
config works just fine for the Unmatched. However config for Unmatched
enables certain optimizations that are valid there. I.e. when reading
RIME or CYCLE registers in a precise way, normally a fence should be
inserted before reading it. However on Unmatched read to both counters
is emulated through a call to firmware (SBI) in userspace, eliminating
the need for the fence.
>
> I assume a single configuriation file for the generic target is enough.
>
> Best regards
>
> Heinrich
>

Re: [PATCH v3 1/8] eal: add initial support for RISC-V architecture

[Heinrich Schuchardt]

On 5/13/22 10:42, Stanisław Kardach wrote:
> On Fri, May 13, 2022 at 8:50 AM Heinrich Schuchardt
> <heinrich.schuchardt@canonical.com> wrote:
> <snip>
>>> +Linux kernel
>>> +~~~~~~~~~~~~
>>> +
>>> +It is recommended to use Linux kernel built from
>>> +`SiFive Freedom Unleashed SDK <https://github.com/sifive/freedom-u-sdk>`_.
>>
>> How would the Unleashed SDK help on a later board or a board from a
>> different vendor?
> This SDK is for both Unleashed and Unmatched. The naming is a bit misleading.
>>
>> Why wouldn't an upstream kernel work?
> At the point of writing it was missing patches related to PCI resource
> mapping exposure to userspace. Right now it's there.
>>
>> I suggest to eliminate this misleading section.
> I'll re-test with the latest upstream kernel and rephrase that this
> should work with Linux kernel >= x.y.z.
>>
>>> +
>>> +
>>> +Meson prerequisites
>>> +~~~~~~~~~~~~~~~~~~~
>>> +
>>> +Meson depends on pkgconfig to find the dependencies.
>>> +The package ``pkg-config-riscv64-linux-gnu`` is required for RISC-V.
>>> +To install it in Ubuntu::
>>> +
>>> +   sudo apt install pkg-config-riscv64-linux-gnu
>>
>> This package does not exist in the current Ubuntu LTS (22.04, Jammy).
>>
>> Setting environment variables PKG_CONFIG_LIBDIR, PKG_CONFIG_PATH,
>> PKG_CONFIG_SYSROOT_DIR properly should do the job with the normal
>> pkg-config.
> Do you happen to know why was this package removed?

The Debian maintainer introduced this change in package 
gcc-defaults-ports. The change log does not give a reason.

> Given that, is there a Ubuntu manual page or tool somewhere specifying
> the correct values to obtain for a given arch?

The values might depend on the Linux distribution.

In Ubuntu the .pc files are in

/usr/lib/riscv64-linux-gnu/pkgconfig
/usr/lib/pkgconfig
/usr/share/pkgconfig

> 
>>
>>> +
>>> +
>>> +GNU toolchain
>>> +-------------
>>> +
>>> +
>>> +Obtain the cross toolchain
>>> +~~~~~~~~~~~~~~~~~~~~~~~~~~
>>> +
>>> +The build process was tested using:
>>> +
>>> +* Ubuntu toolchain (the ``crossbuild-essential-riscv64`` package).
>>> +
>>> +* Latest `RISC-V GNU toolchain
>>> +  <https://github.com/riscv/riscv-gnu-toolchain/releases>`_ on Ubuntu or Arch
>>> +  Linux.
>>> +
>>> +Alternatively the toolchain may be built straight from the source, to do that
>>> +follow the instructions on the riscv-gnu-toolchain github page.
>>> +
>>> +
>>> +Unzip and add into the PATH
>>> +~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>> +
>>> +This step is only required for the riscv-gnu-toolchain. The Ubuntu toolchain is
>>> +in the PATH already.
>>> +
>>> +.. code-block:: console
>>> +
>>> +   tar -xvf riscv64-glibc-ubuntu-20.04-<version>.tar.gz
>>
>> You can install the glibc package with apt-get after adding the
>> architecture with sudo dpkg --add-architecture riscv64. See
>> https://wiki.debian.org/CrossCompiling.
>>
> This guide is supposed to target also Arch where this toolchain should
> work properly. That's why in previous section I'm mentioning
> crossbuild-essential-riscv64 and RISC-V GNU toolchain from github
> separately.
>>> +   export PATH=$PATH:<cross_install_dir>/riscv/bin
>>> +
>>> +
>>> +Cross Compiling DPDK with GNU toolchain using Meson
>>> +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>> +
>>> +To cross-compile DPDK for a desired target machine use the following command::
>>> +
>>> +   meson cross-build --cross-file <target_machine_configuration>
>>> +   ninja -C cross-build
>>> +
>>> +For example if the target machine is a generic rv64gc RISC-V, use the following
>>> +command::
>>> +
>>> +   meson riscv64-build-gcc --cross-file config/riscv/riscv64_linux_gcc
>>> +   ninja -C riscv64-build-gcc
>>> +
>>> +If riscv-gnu-toolchain is used, binary names should be updated to match. Update the following lines in the cross-file:
>>> +
>>> +.. code-block:: console
>>> +
>>> +   [binaries]
>>> +   c = 'riscv64-unknown-linux-gnu-gcc'
>>> +   cpp = 'riscv64-unknown-linux-gnu-g++'
>>> +   ar = 'riscv64-unknown-linux-gnu-ar'
>>> +   strip = 'riscv64-unknown-linux-gnu-strip'
>>> +   ...
>>> +
>>> +Some toolchains (such as freedom-u-sdk one) require also setting ``--sysroot``,
>>> +otherwise include paths might not be resolved. To do so, add the appropriate
>>> +paths to the cross-file:
>>> +
>>> +.. code-block:: console
>>> +
>>> +   [properties]
>>> +   ...
>>> +   c_args = ['--sysroot', '<path/to/toolchain/sysroot>']
>>> +   cpp_args = c_args
>>> +   c_link_args = ['--sysroot', '<path/to/toolchain/sysroot>']
>>> +   cpp_link_args = c_link_args
>>> +   ...
>>> +
>>> +
>>> +Supported cross-compilation targets
>>> +-----------------------------------
>>> +
>>> +Currently the following targets are supported:
>>> +
>>> +* Generic rv64gc ISA: ``config/riscv/riscv64_linux_gcc``
>>> +
>>> +* SiFive U740 SoC: ``config/riscv/riscv64_sifive_u740_linux_gcc``
>>
>> Why do we need a special config for the Unmatched board that is not sold
>> anymore? Doesn't the Unmatched board work with the genenric config?
> I wasn't aware that they did discontinue it. As far as I can see it's
> due to supply chain issues, maybe that means it'll get back? Generic

https://forums.sifive.com/t/sifive-update-on-hifive-unmatched-boards-in-2022/5569?s=09 
:

"we’ve decided to focus on the next generation SiFive HiFive development 
systems rather than trying to put together another build of the HiFive 
Unmatched platform in 2022."

> config works just fine for the Unmatched. However config for Unmatched
> enables certain optimizations that are valid there. I.e. when reading
> RIME or CYCLE registers in a precise way, normally a fence should be
> inserted before reading it. However on Unmatched read to both counters
> is emulated through a call to firmware (SBI) in userspace, eliminating
> the need for the fence.

Distributions like Ubuntu will only build a single configuration. It is 
preferable to read vendor_id and arch_id via an SBI call at runtime to 
switch code paths.

Isn't the saving gained by removing the fence irrelevant compared to the 
duration of an SBI call?

Best regards

Heinrich

>>
>> I assume a single configuration file for the generic target is enough.
>>
>> Best regards
>>
>> Heinrich
>>

Re: [PATCH v3 1/8] eal: add initial support for RISC-V architecture

[Stanisław Kardach]

On Fri, May 13, 2022 at 12:52 PM Heinrich Schuchardt
<heinrich.schuchardt@canonical.com> wrote:
>
> On 5/13/22 10:42, Stanisław Kardach wrote:
> > On Fri, May 13, 2022 at 8:50 AM Heinrich Schuchardt
> > <heinrich.schuchardt@canonical.com> wrote:
> > <snip>
> >>> +Linux kernel
> >>> +~~~~~~~~~~~~
> >>> +
> >>> +It is recommended to use Linux kernel built from
> >>> +`SiFive Freedom Unleashed SDK <https://github.com/sifive/freedom-u-sdk>`_.
> >>
> >> How would the Unleashed SDK help on a later board or a board from a
> >> different vendor?
> > This SDK is for both Unleashed and Unmatched. The naming is a bit misleading.
> >>
> >> Why wouldn't an upstream kernel work?
> > At the point of writing it was missing patches related to PCI resource
> > mapping exposure to userspace. Right now it's there.
> >>
> >> I suggest to eliminate this misleading section.
> > I'll re-test with the latest upstream kernel and rephrase that this
> > should work with Linux kernel >= x.y.z.
> >>
> >>> +
> >>> +
> >>> +Meson prerequisites
> >>> +~~~~~~~~~~~~~~~~~~~
> >>> +
> >>> +Meson depends on pkgconfig to find the dependencies.
> >>> +The package ``pkg-config-riscv64-linux-gnu`` is required for RISC-V.
> >>> +To install it in Ubuntu::
> >>> +
> >>> +   sudo apt install pkg-config-riscv64-linux-gnu
> >>
> >> This package does not exist in the current Ubuntu LTS (22.04, Jammy).
> >>
> >> Setting environment variables PKG_CONFIG_LIBDIR, PKG_CONFIG_PATH,
> >> PKG_CONFIG_SYSROOT_DIR properly should do the job with the normal
> >> pkg-config.
> > Do you happen to know why was this package removed?
>
> The Debian maintainer introduced this change in package
> gcc-defaults-ports. The change log does not give a reason.
>
> > Given that, is there a Ubuntu manual page or tool somewhere specifying
> > the correct values to obtain for a given arch?
>
> The values might depend on the Linux distribution.
>
> In Ubuntu the .pc files are in
>
> /usr/lib/riscv64-linux-gnu/pkgconfig
> /usr/lib/pkgconfig
> /usr/share/pkgconfig
OK, I'll describe those for Ubuntu path.
>
> >
> >>
> >>> +
> >>> +
> >>> +GNU toolchain
> >>> +-------------
> >>> +
> >>> +
> >>> +Obtain the cross toolchain
> >>> +~~~~~~~~~~~~~~~~~~~~~~~~~~
> >>> +
> >>> +The build process was tested using:
> >>> +
> >>> +* Ubuntu toolchain (the ``crossbuild-essential-riscv64`` package).
> >>> +
> >>> +* Latest `RISC-V GNU toolchain
> >>> +  <https://github.com/riscv/riscv-gnu-toolchain/releases>`_ on Ubuntu or Arch
> >>> +  Linux.
> >>> +
> >>> +Alternatively the toolchain may be built straight from the source, to do that
> >>> +follow the instructions on the riscv-gnu-toolchain github page.
> >>> +
> >>> +
> >>> +Unzip and add into the PATH
> >>> +~~~~~~~~~~~~~~~~~~~~~~~~~~~
> >>> +
> >>> +This step is only required for the riscv-gnu-toolchain. The Ubuntu toolchain is
> >>> +in the PATH already.
> >>> +
> >>> +.. code-block:: console
> >>> +
> >>> +   tar -xvf riscv64-glibc-ubuntu-20.04-<version>.tar.gz
> >>
> >> You can install the glibc package with apt-get after adding the
> >> architecture with sudo dpkg --add-architecture riscv64. See
> >> https://wiki.debian.org/CrossCompiling.
> >>
> > This guide is supposed to target also Arch where this toolchain should
> > work properly. That's why in previous section I'm mentioning
> > crossbuild-essential-riscv64 and RISC-V GNU toolchain from github
> > separately.
> >>> +   export PATH=$PATH:<cross_install_dir>/riscv/bin
> >>> +
> >>> +
> >>> +Cross Compiling DPDK with GNU toolchain using Meson
> >>> +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> >>> +
> >>> +To cross-compile DPDK for a desired target machine use the following command::
> >>> +
> >>> +   meson cross-build --cross-file <target_machine_configuration>
> >>> +   ninja -C cross-build
> >>> +
> >>> +For example if the target machine is a generic rv64gc RISC-V, use the following
> >>> +command::
> >>> +
> >>> +   meson riscv64-build-gcc --cross-file config/riscv/riscv64_linux_gcc
> >>> +   ninja -C riscv64-build-gcc
> >>> +
> >>> +If riscv-gnu-toolchain is used, binary names should be updated to match. Update the following lines in the cross-file:
> >>> +
> >>> +.. code-block:: console
> >>> +
> >>> +   [binaries]
> >>> +   c = 'riscv64-unknown-linux-gnu-gcc'
> >>> +   cpp = 'riscv64-unknown-linux-gnu-g++'
> >>> +   ar = 'riscv64-unknown-linux-gnu-ar'
> >>> +   strip = 'riscv64-unknown-linux-gnu-strip'
> >>> +   ...
> >>> +
> >>> +Some toolchains (such as freedom-u-sdk one) require also setting ``--sysroot``,
> >>> +otherwise include paths might not be resolved. To do so, add the appropriate
> >>> +paths to the cross-file:
> >>> +
> >>> +.. code-block:: console
> >>> +
> >>> +   [properties]
> >>> +   ...
> >>> +   c_args = ['--sysroot', '<path/to/toolchain/sysroot>']
> >>> +   cpp_args = c_args
> >>> +   c_link_args = ['--sysroot', '<path/to/toolchain/sysroot>']
> >>> +   cpp_link_args = c_link_args
> >>> +   ...
> >>> +
> >>> +
> >>> +Supported cross-compilation targets
> >>> +-----------------------------------
> >>> +
> >>> +Currently the following targets are supported:
> >>> +
> >>> +* Generic rv64gc ISA: ``config/riscv/riscv64_linux_gcc``
> >>> +
> >>> +* SiFive U740 SoC: ``config/riscv/riscv64_sifive_u740_linux_gcc``
> >>
> >> Why do we need a special config for the Unmatched board that is not sold
> >> anymore? Doesn't the Unmatched board work with the genenric config?
> > I wasn't aware that they did discontinue it. As far as I can see it's
> > due to supply chain issues, maybe that means it'll get back? Generic
>
> https://forums.sifive.com/t/sifive-update-on-hifive-unmatched-boards-in-2022/5569?s=09
> :
>
> "we’ve decided to focus on the next generation SiFive HiFive development
> systems rather than trying to put together another build of the HiFive
> Unmatched platform in 2022."
I did not know that, thank you.
>
> > config works just fine for the Unmatched. However config for Unmatched
> > enables certain optimizations that are valid there. I.e. when reading
> > RIME or CYCLE registers in a precise way, normally a fence should be
> > inserted before reading it. However on Unmatched read to both counters
> > is emulated through a call to firmware (SBI) in userspace, eliminating
> > the need for the fence.
>
> Distributions like Ubuntu will only build a single configuration.
I understand however there are also platform specific configs for
Aarch64 here (Graviton, ThunderX, CnXk to name a few) so it's not that
uncommon. Plus distro packages although useful for orchestration
environments such as accelerating OpenStack Neutron (or other
orchestrated networking packages), there will still be people
compiling DPDK locally, be it via company-wide Yocto server to package
for specific HW or just integrating DPDK statically in their projects
(to not pay the cost of a dynamic lib call).
> It is preferable to read vendor_id and arch_id via an SBI call at runtime
> to switch code paths.
Right, but SBI call can only be made from S-mode (so kernel), right?
Issuing "ecall" from U-mode (userspace) will transfer control to
kernel. AFAIK it is KVM that emulates or forwards SBI calls further
but that's in qemu scope.
I was trying to figure out how to get this data from Linux to decide
at build time but it's not in the /proc/cpuinfo (it only prints DTS's
"compatible" for the CPU). Deciding at runtime is costly because you
either need a functor call or self-modifying code (similar to how
Linux handles Compare-And-Swap on Aarch64).
>
> Isn't the saving gained by removing the fence irrelevant compared to the
> duration of an SBI call?
Yes, that is most likely but I was not able to measure it, because the
access to the time source on Unmatched is emulated, so it's hard to
reason.
Other thing that this config triggers (or more precisely the vendor_id
and arch_id) is "-mtune" value which I believe still contains some
compiler tweaks for the platform.

Given all that I can remove the current infrastructure in
config/riscv/meson.build and the related sifive config but I'd prefer
not to. I'm pretty sure it'll come in handy when a new RISC-V platform
comes in (and serve as a reference for new developers). There is a
warning in meson.build noting the lack of ability to detect the
current platform. When someone implements it in Linux, that'll be a
single place to change. Even then the configs won't become useless due
to cross-compiling for a specific target.

Best Regards,
Stanislaw Kardach

Re: [PATCH v3 1/8] eal: add initial support for RISC-V architecture

[Stephen Hemminger]

On Fri, 13 May 2022 08:50:34 +0200
Heinrich Schuchardt <heinrich.schuchardt@canonical.com> wrote:

> On 5/10/22 17:48, Stanislaw Kardach wrote:
> > From: Michal Mazurek <maz@semihalf.com>
> > 
> > Add all necessary elements for DPDK to compile and run EAL on SiFive
> > Freedom U740 SoC which is based on SiFive U74-MC (ISA: rv64imafdc)
> > core complex.
> > 
> > This includes:
> > 
> > - EAL library implementation for rv64imafdc ISA.
> > - meson build structure for 'riscv' architecture. RTE_ARCH_RISCV define
> >    is added for architecture identification.
> > - xmm_t structure operation stubs as there is no vector support in the
> >    U74 core.
> > 
> > Compilation was tested on Ubuntu and Arch Linux using riscv64 toolchain.
> > Clang compilation currently not supported due to issues with missing
> > relocation relaxation.
> > 
> > Two rte_rdtsc() schemes are provided: stable low-resolution using rdtime
> > (default) and unstable high-resolution using rdcycle. User can override
> > the scheme by defining RTE_RISCV_RDTSC_USE_HPM=1 during compile time of
> > both DPDK and the application. The reasoning for this is as follows.
> > The RISC-V ISA mandates that clock read by rdtime has to be of constant
> > period and synchronized between all hardware threads within 1 tick
> > (chapter 10.1 in version 20191213 of RISC-V spec).
> > However this clock may not be of high-enough frequency for dataplane
> > uses. I.e. on HiFive Unmatched (FU740) it is 1MHz.
> > There is a high-resolution alternative in form of rdcycle which is
> > clocked at the core clock frequency. The drawbacks are that it may be
> > disabled during sleep (WFI) and its frequency might change due to DVFS.

Choosing at compile time is ok for embedded but is undesireable for DPDK
in a distribution.  It sounds like the low-res is equivalent to hpet
and the unstable is same as x86 TSC. Therefore why not follow that
precedent and do the same thing?

Re: [PATCH v3 1/8] eal: add initial support for RISC-V architecture

[Stanisław Kardach]

On Fri, May 13, 2022 at 5:37 PM Stephen Hemminger
<stephen@networkplumber.org> wrote:
>
> On Fri, 13 May 2022 08:50:34 +0200
> Heinrich Schuchardt <heinrich.schuchardt@canonical.com> wrote:
>
> > On 5/10/22 17:48, Stanislaw Kardach wrote:
> > > From: Michal Mazurek <maz@semihalf.com>
> > >
> > > Add all necessary elements for DPDK to compile and run EAL on SiFive
> > > Freedom U740 SoC which is based on SiFive U74-MC (ISA: rv64imafdc)
> > > core complex.
> > >
> > > This includes:
> > >
> > > - EAL library implementation for rv64imafdc ISA.
> > > - meson build structure for 'riscv' architecture. RTE_ARCH_RISCV define
> > >    is added for architecture identification.
> > > - xmm_t structure operation stubs as there is no vector support in the
> > >    U74 core.
> > >
> > > Compilation was tested on Ubuntu and Arch Linux using riscv64 toolchain.
> > > Clang compilation currently not supported due to issues with missing
> > > relocation relaxation.
> > >
> > > Two rte_rdtsc() schemes are provided: stable low-resolution using rdtime
> > > (default) and unstable high-resolution using rdcycle. User can override
> > > the scheme by defining RTE_RISCV_RDTSC_USE_HPM=1 during compile time of
> > > both DPDK and the application. The reasoning for this is as follows.
> > > The RISC-V ISA mandates that clock read by rdtime has to be of constant
> > > period and synchronized between all hardware threads within 1 tick
> > > (chapter 10.1 in version 20191213 of RISC-V spec).
> > > However this clock may not be of high-enough frequency for dataplane
> > > uses. I.e. on HiFive Unmatched (FU740) it is 1MHz.
> > > There is a high-resolution alternative in form of rdcycle which is
> > > clocked at the core clock frequency. The drawbacks are that it may be
> > > disabled during sleep (WFI) and its frequency might change due to DVFS.
>
> Choosing at compile time is ok for embedded but is undesireable for DPDK
> in a distribution. It sounds like the low-res is equivalent to hpet
> and the unstable is same as x86 TSC.
AFAIK, TSC has constant frequency on newer processors (see [1] for a
somewhat related Linux patch). To quote Intel
Software Developer’s Manual Volume 3, pt. 17.17.1:
  The invariant TSC will run at a constant rate in all ACPI
  P-, C-. and T-states. This is the architectural behavior moving
  forward.

> Therefore why not follow that
> precedent and do the same thing?
>
Here the situation is more akin to ARMv8 with it's low-resolution
CNTVCT and PMU based PMCCNTR. The former is always available in
userspace (EL0) while access to the latter needs to be enabled via
CSRs in kernel.
RDCYCLE on RISC-V is essentially the same as PMCCNTR, except that by
default it's enabled (governed by OpenSBI firmware - see [2]). However
it does not have the stable nature of TSC in RISC-V spec. AFAIK on ARM
this has been dealt with similarly to x86, ARMv8.6-a forces a 1GHz
frequency for CNTVCT.

So I based my implementation on the current ARM platform approach.
Given that it seems RDCYCLE will remain enabled in userspace (see
[2]), I can simplify this to use RDCYCLE if current ARM approach is
not preferred.

[1] https://patchwork.kernel.org/project/kvm/patch/20140422191200.328459410@amt.cnet/
[2] http://lists.infradead.org/pipermail/opensbi/2021-June/001219.html

[PATCH v3 2/8] net/ixgbe: enable vector stubs for RISC-V

[Stanislaw Kardach]

Re-use vector processing stubs in ixgbe PMD defined for PPC for RISC-V.
This enables ixgbe PMD usage in scalar mode on this architecture.

The ixgbe PMD driver was validated with Intel X520-DA2 NIC and the
test-pmd application. Packet transfer checked using all UIO drivers
available for non-IOMMU platforms: uio_pci_generic, vfio-pci noiommu and
igb_uio.

Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
---
 doc/guides/nics/features/ixgbe.ini | 1 +
 drivers/net/ixgbe/ixgbe_rxtx.c     | 4 ++--
 drivers/net/ixgbe/meson.build      | 6 ------
 3 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/doc/guides/nics/features/ixgbe.ini b/doc/guides/nics/features/ixgbe.ini
index c5333d1142..b776ca1cf1 100644
--- a/doc/guides/nics/features/ixgbe.ini
+++ b/doc/guides/nics/features/ixgbe.ini
@@ -54,6 +54,7 @@ Windows              = Y
 ARMv8                = Y
 x86-32               = Y
 x86-64               = Y
+rv64                 = Y
 
 [rte_flow items]
 eth                  = Y
diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c
index 9e8ea366a5..009d9b624a 100644
--- a/drivers/net/ixgbe/ixgbe_rxtx.c
+++ b/drivers/net/ixgbe/ixgbe_rxtx.c
@@ -5957,8 +5957,8 @@ ixgbe_config_rss_filter(struct rte_eth_dev *dev,
 	return 0;
 }
 
-/* Stubs needed for linkage when RTE_ARCH_PPC_64 is set */
-#if defined(RTE_ARCH_PPC_64)
+/* Stubs needed for linkage when RTE_ARCH_PPC_64 or RTE_ARCH_RISCV is set */
+#if defined(RTE_ARCH_PPC_64) || defined(RTE_ARCH_RISCV)
 int
 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
 {
diff --git a/drivers/net/ixgbe/meson.build b/drivers/net/ixgbe/meson.build
index 88539e97d5..162f8d5f46 100644
--- a/drivers/net/ixgbe/meson.build
+++ b/drivers/net/ixgbe/meson.build
@@ -1,12 +1,6 @@
 # SPDX-License-Identifier: BSD-3-Clause
 # Copyright(c) 2017 Intel Corporation
 
-if arch_subdir == 'riscv'
-		build = false
-		reason = 'riscv arch not supported'
-		subdir_done()
-endif
-
 cflags += ['-DRTE_LIBRTE_IXGBE_BYPASS']
 
 subdir('base')
-- 
2.30.2

[PATCH v3 3/8] net/memif: set memfd syscall ID on RISC-V

[Stanislaw Kardach]

Define the missing __NR_memfd_create syscall id to enable the memif PMD.

Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
---
 drivers/net/memif/meson.build     | 5 -----
 drivers/net/memif/rte_eth_memif.h | 2 ++
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/net/memif/meson.build b/drivers/net/memif/meson.build
index 9afb495953..680bc8631c 100644
--- a/drivers/net/memif/meson.build
+++ b/drivers/net/memif/meson.build
@@ -5,11 +5,6 @@ if not is_linux
     build = false
     reason = 'only supported on Linux'
 endif
-if arch_subdir == 'riscv'
-		build = false
-		reason = 'riscv arch not supported'
-		subdir_done()
-endif
 
 sources = files(
         'memif_socket.c',
diff --git a/drivers/net/memif/rte_eth_memif.h b/drivers/net/memif/rte_eth_memif.h
index a5ee23d42e..81e7dceae0 100644
--- a/drivers/net/memif/rte_eth_memif.h
+++ b/drivers/net/memif/rte_eth_memif.h
@@ -180,6 +180,8 @@ const char *memif_version(void);
 #define __NR_memfd_create 360
 #elif defined __i386__
 #define __NR_memfd_create 356
+#elif defined __riscv
+#define __NR_memfd_create 279
 #else
 #error "__NR_memfd_create unknown for this architecture"
 #endif
-- 
2.30.2

[PATCH v3 4/8] net/tap: set BPF syscall ID for RISC-V

[Stanislaw Kardach]

Define the missing __NR_bpf syscall id to enable the tap PMD.

Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
---
 drivers/net/tap/meson.build | 5 -----
 drivers/net/tap/tap_bpf.h   | 2 ++
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/net/tap/meson.build b/drivers/net/tap/meson.build
index 3efac9ac07..c09713a67b 100644
--- a/drivers/net/tap/meson.build
+++ b/drivers/net/tap/meson.build
@@ -5,11 +5,6 @@ if not is_linux
     build = false
     reason = 'only supported on Linux'
 endif
-if arch_subdir == 'riscv'
-		build = false
-		reason = 'riscv arch not supported'
-		subdir_done()
-endif
 sources = files(
         'rte_eth_tap.c',
         'tap_bpf_api.c',
diff --git a/drivers/net/tap/tap_bpf.h b/drivers/net/tap/tap_bpf.h
index f0b9fc7a2c..639bdf3a79 100644
--- a/drivers/net/tap/tap_bpf.h
+++ b/drivers/net/tap/tap_bpf.h
@@ -101,6 +101,8 @@ union bpf_attr {
 #  define __NR_bpf 351
 # elif defined(__powerpc__)
 #  define __NR_bpf 361
+# elif defined(__riscv)
+#  define __NR_bpf 280
 # else
 #  error __NR_bpf not defined
 # endif
-- 
2.30.2

[PATCH v3 5/8] examples/l3fwd: enable RISC-V operation

[Stanislaw Kardach]

Add missing em_mask_key() implementation and fix l3fwd_common.h
inclusion in FIB lookup functions to enable the l3fwd to be run on
RISC-V.

Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
---
 examples/l3fwd/l3fwd_em.c  | 8 ++++++++
 examples/l3fwd/l3fwd_fib.c | 2 ++
 examples/l3fwd/meson.build | 6 ------
 3 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
index 24d0910fe0..bbd3452546 100644
--- a/examples/l3fwd/l3fwd_em.c
+++ b/examples/l3fwd/l3fwd_em.c
@@ -239,6 +239,14 @@ em_mask_key(void *key, xmm_t mask)
 
 	return vec_and(data, mask);
 }
+#elif defined(RTE_ARCH_RISCV)
+static inline xmm_t
+em_mask_key(void *key, xmm_t mask)
+{
+	xmm_t data = vect_load_128(key);
+
+	return vect_and(data, mask);
+}
 #else
 #error No vector engine (SSE, NEON, ALTIVEC) available, check your toolchain
 #endif
diff --git a/examples/l3fwd/l3fwd_fib.c b/examples/l3fwd/l3fwd_fib.c
index 6e0054b4cb..bdb7d7535d 100644
--- a/examples/l3fwd/l3fwd_fib.c
+++ b/examples/l3fwd/l3fwd_fib.c
@@ -18,6 +18,8 @@
 #include "l3fwd_neon.h"
 #elif defined RTE_ARCH_PPC_64
 #include "l3fwd_altivec.h"
+#else
+#include "l3fwd_common.h"
 #endif
 #include "l3fwd_event.h"
 #include "l3fwd_route.h"
diff --git a/examples/l3fwd/meson.build b/examples/l3fwd/meson.build
index 75fa19b7fe..0830b3eb31 100644
--- a/examples/l3fwd/meson.build
+++ b/examples/l3fwd/meson.build
@@ -6,12 +6,6 @@
 # To build this example as a standalone application with an already-installed
 # DPDK instance, use 'make'
 
-if dpdk_conf.has('RTE_ARCH_RISCV')
-		build = false
-		reason = 'riscv arch not supported'
-		subdir_done()
-endif
-
 allow_experimental_apis = true
 deps += ['hash', 'lpm', 'fib', 'eventdev']
 sources = files(
-- 
2.30.2

[PATCH v3 6/8] test/cpuflags: add test for RISC-V cpu flag

[Stanislaw Kardach]

From: Michal Mazurek <maz@semihalf.com>

Add checks for all flag values defined in the RISC-V misa CSR register.

Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
Signed-off-by: Michal Mazurek <maz@semihalf.com>
Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
---
 app/test/test_cpuflags.c | 81 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 81 insertions(+)

diff --git a/app/test/test_cpuflags.c b/app/test/test_cpuflags.c
index 40f6ac7fca..98a99c2c7d 100644
--- a/app/test/test_cpuflags.c
+++ b/app/test/test_cpuflags.c
@@ -200,6 +200,87 @@ test_cpuflags(void)
 	CHECK_FOR_FLAG(RTE_CPUFLAG_INVTSC);
 #endif
 
+#if defined(RTE_ARCH_RISCV)
+
+	printf("Check for RISCV_ISA_A:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_A);
+
+	printf("Check for RISCV_ISA_B:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_B);
+
+	printf("Check for RISCV_ISA_C:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_C);
+
+	printf("Check for RISCV_ISA_D:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_D);
+
+	printf("Check for RISCV_ISA_E:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_E);
+
+	printf("Check for RISCV_ISA_F:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_F);
+
+	printf("Check for RISCV_ISA_G:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_G);
+
+	printf("Check for RISCV_ISA_H:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_H);
+
+	printf("Check for RISCV_ISA_I:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_I);
+
+	printf("Check for RISCV_ISA_J:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_J);
+
+	printf("Check for RISCV_ISA_K:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_K);
+
+	printf("Check for RISCV_ISA_L:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_L);
+
+	printf("Check for RISCV_ISA_M:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_M);
+
+	printf("Check for RISCV_ISA_N:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_N);
+
+	printf("Check for RISCV_ISA_O:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_O);
+
+	printf("Check for RISCV_ISA_P:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_P);
+
+	printf("Check for RISCV_ISA_Q:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Q);
+
+	printf("Check for RISCV_ISA_R:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_R);
+
+	printf("Check for RISCV_ISA_S:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_S);
+
+	printf("Check for RISCV_ISA_T:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_T);
+
+	printf("Check for RISCV_ISA_U:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_U);
+
+	printf("Check for RISCV_ISA_V:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_V);
+
+	printf("Check for RISCV_ISA_W:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_W);
+
+	printf("Check for RISCV_ISA_X:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_X);
+
+	printf("Check for RISCV_ISA_Y:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Y);
+
+	printf("Check for RISCV_ISA_Z:\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Z);
+#endif
+
 	/*
 	 * Check if invalid data is handled properly
 	 */
-- 
2.30.2

[PATCH v3 7/8] devtools: add RISC-V to test-meson-builds.sh

[Stanislaw Kardach]

Validate RISC-V compilation when test-meson-builds.sh is called. The
check will be only performed if appropriate toolchain is present on the
system (same as with other architectures).

Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
---
 devtools/test-meson-builds.sh | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/devtools/test-meson-builds.sh b/devtools/test-meson-builds.sh
index a653b253cb..f732dccf6c 100755
--- a/devtools/test-meson-builds.sh
+++ b/devtools/test-meson-builds.sh
@@ -275,6 +275,10 @@ for f in $srcdir/config/ppc/ppc* ; do
 	build $targetdir $f ABI $use_shared
 done
 
+# RISC-V configuration
+build build-riscv64-linux-gcc $srcdir/config/riscv/riscv64_linux_gcc ABI \
+	$use_shared
+
 # Test installation of the x86-generic target, to be used for checking
 # the sample apps build using the pkg-config file for cflags and libs
 load_env cc
-- 
2.30.2

[PATCH v3 8/8] ci: add RISCV64 cross compilation job

[Stanislaw Kardach]

Checks cross-compilation using Ubuntu 20.04 x86.

Signed-off-by: David Marchand <david.marchand@redhat.com>
Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
---
 .ci/linux-build.sh          |  4 ++++
 .github/workflows/build.yml | 11 ++++++++++-
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/.ci/linux-build.sh b/.ci/linux-build.sh
index 877243c9c8..aa5e9ec114 100755
--- a/.ci/linux-build.sh
+++ b/.ci/linux-build.sh
@@ -74,6 +74,10 @@ if [ "$PPC64LE" = "true" ]; then
     cross_file=config/ppc/ppc64le-power8-linux-gcc-ubuntu
 fi
 
+if [ "$RISCV64" = "true" ]; then
+    cross_file=config/riscv/riscv64_linux_gcc
+fi
+
 if [ -n "$cross_file" ]; then
     OPTS="$OPTS --cross-file $cross_file"
 fi
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index e2f94d786b..ca468da8fa 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -25,6 +25,7 @@ jobs:
       MINI: ${{ matrix.config.mini != '' }}
       PPC64LE: ${{ matrix.config.cross == 'ppc64le' }}
       REF_GIT_TAG: v22.03
+      RISCV64: ${{ matrix.config.cross == 'riscv64' }}
       RUN_TESTS: ${{ contains(matrix.config.checks, 'tests') }}
 
     strategy:
@@ -73,6 +74,10 @@ jobs:
             compiler: gcc
             library: shared
             cross: ppc64le
+          - os: ubuntu-20.04
+            compiler: gcc
+            library: shared
+            cross: riscv64
 
     steps:
     - name: Checkout sources
@@ -131,8 +136,12 @@ jobs:
       if: env.PPC64LE == 'true'
       run: sudo apt install -y gcc-powerpc64le-linux-gnu libc6-dev-ppc64el-cross
         pkg-config-powerpc-linux-gnu
+    - name: Install riscv64 cross compiling packages
+      if: env.RISCV64 == 'true'
+      run: sudo apt install -y gcc-riscv64-linux-gnu libc6-dev-riscv64-cross
+        pkg-config-riscv64-linux-gnu
     - name: Install test tools packages
-      if: env.AARCH64 != 'true' || env.PPC64LE != 'true' || env.RUN_TESTS == 'true'
+      if: env.AARCH64 != 'true' || env.PPC64LE != 'true' || env.RISCV64 != 'true' || env.RUN_TESTS == 'true'
       run: sudo apt install -y gdb
     - name: Install doc generation packages
       if: env.BUILD_DOCS == 'true'
-- 
2.30.2

Re: [PATCH v3 8/8] ci: add RISCV64 cross compilation job

[Aaron Conole]

Stanislaw Kardach <kda@semihalf.com> writes:

> Checks cross-compilation using Ubuntu 20.04 x86.
>
> Signed-off-by: David Marchand <david.marchand@redhat.com>
> Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
> ---
>  .ci/linux-build.sh          |  4 ++++
>  .github/workflows/build.yml | 11 ++++++++++-
>  2 files changed, 14 insertions(+), 1 deletion(-)

Seems there is still a failure in this series - once that is resolved I
think this can go in.

> diff --git a/.ci/linux-build.sh b/.ci/linux-build.sh
> index 877243c9c8..aa5e9ec114 100755
> --- a/.ci/linux-build.sh
> +++ b/.ci/linux-build.sh
> @@ -74,6 +74,10 @@ if [ "$PPC64LE" = "true" ]; then
>      cross_file=config/ppc/ppc64le-power8-linux-gcc-ubuntu
>  fi
>  
> +if [ "$RISCV64" = "true" ]; then
> +    cross_file=config/riscv/riscv64_linux_gcc
> +fi
> +
>  if [ -n "$cross_file" ]; then
>      OPTS="$OPTS --cross-file $cross_file"
>  fi
> diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
> index e2f94d786b..ca468da8fa 100644
> --- a/.github/workflows/build.yml
> +++ b/.github/workflows/build.yml
> @@ -25,6 +25,7 @@ jobs:
>        MINI: ${{ matrix.config.mini != '' }}
>        PPC64LE: ${{ matrix.config.cross == 'ppc64le' }}
>        REF_GIT_TAG: v22.03
> +      RISCV64: ${{ matrix.config.cross == 'riscv64' }}
>        RUN_TESTS: ${{ contains(matrix.config.checks, 'tests') }}
>  
>      strategy:
> @@ -73,6 +74,10 @@ jobs:
>              compiler: gcc
>              library: shared
>              cross: ppc64le
> +          - os: ubuntu-20.04
> +            compiler: gcc
> +            library: shared
> +            cross: riscv64
>  
>      steps:
>      - name: Checkout sources
> @@ -131,8 +136,12 @@ jobs:
>        if: env.PPC64LE == 'true'
>        run: sudo apt install -y gcc-powerpc64le-linux-gnu libc6-dev-ppc64el-cross
>          pkg-config-powerpc-linux-gnu
> +    - name: Install riscv64 cross compiling packages
> +      if: env.RISCV64 == 'true'
> +      run: sudo apt install -y gcc-riscv64-linux-gnu libc6-dev-riscv64-cross
> +        pkg-config-riscv64-linux-gnu
>      - name: Install test tools packages
> -      if: env.AARCH64 != 'true' || env.PPC64LE != 'true' || env.RUN_TESTS == 'true'
> +      if: env.AARCH64 != 'true' || env.PPC64LE != 'true' || env.RISCV64 != 'true' || env.RUN_TESTS == 'true'
>        run: sudo apt install -y gdb
>      - name: Install doc generation packages
>        if: env.BUILD_DOCS == 'true'

Re: [PATCH v3 8/8] ci: add RISCV64 cross compilation job

[Stanisław Kardach]

[-- Attachment #1: Type: text/plain, Size: 2888 bytes --]

On Thu, 12 May 2022, 17:47 Aaron Conole, <aconole@redhat.com> wrote:

> Stanislaw Kardach <kda@semihalf.com> writes:
>
> > Checks cross-compilation using Ubuntu 20.04 x86.
> >
> > Signed-off-by: David Marchand <david.marchand@redhat.com>
> > Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
> > ---
> >  .ci/linux-build.sh          |  4 ++++
> >  .github/workflows/build.yml | 11 ++++++++++-
> >  2 files changed, 14 insertions(+), 1 deletion(-)
>
> Seems there is still a failure in this series - once that is resolved I
> think this can go in.
>
I suspect the failure is due to this series depending on 3 other patches
which I've marked with Depends-on in the offending patch. Is CI utilizing
those tags? If not, is there a way to relaunch it once dependencies are
integrated?

>
> > diff --git a/.ci/linux-build.sh b/.ci/linux-build.sh
> > index 877243c9c8..aa5e9ec114 100755
> > --- a/.ci/linux-build.sh
> > +++ b/.ci/linux-build.sh
> > @@ -74,6 +74,10 @@ if [ "$PPC64LE" = "true" ]; then
> >      cross_file=config/ppc/ppc64le-power8-linux-gcc-ubuntu
> >  fi
> >
> > +if [ "$RISCV64" = "true" ]; then
> > +    cross_file=config/riscv/riscv64_linux_gcc
> > +fi
> > +
> >  if [ -n "$cross_file" ]; then
> >      OPTS="$OPTS --cross-file $cross_file"
> >  fi
> > diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
> > index e2f94d786b..ca468da8fa 100644
> > --- a/.github/workflows/build.yml
> > +++ b/.github/workflows/build.yml
> > @@ -25,6 +25,7 @@ jobs:
> >        MINI: ${{ matrix.config.mini != '' }}
> >        PPC64LE: ${{ matrix.config.cross == 'ppc64le' }}
> >        REF_GIT_TAG: v22.03
> > +      RISCV64: ${{ matrix.config.cross == 'riscv64' }}
> >        RUN_TESTS: ${{ contains(matrix.config.checks, 'tests') }}
> >
> >      strategy:
> > @@ -73,6 +74,10 @@ jobs:
> >              compiler: gcc
> >              library: shared
> >              cross: ppc64le
> > +          - os: ubuntu-20.04
> > +            compiler: gcc
> > +            library: shared
> > +            cross: riscv64
> >
> >      steps:
> >      - name: Checkout sources
> > @@ -131,8 +136,12 @@ jobs:
> >        if: env.PPC64LE == 'true'
> >        run: sudo apt install -y gcc-powerpc64le-linux-gnu
> libc6-dev-ppc64el-cross
> >          pkg-config-powerpc-linux-gnu
> > +    - name: Install riscv64 cross compiling packages
> > +      if: env.RISCV64 == 'true'
> > +      run: sudo apt install -y gcc-riscv64-linux-gnu
> libc6-dev-riscv64-cross
> > +        pkg-config-riscv64-linux-gnu
> >      - name: Install test tools packages
> > -      if: env.AARCH64 != 'true' || env.PPC64LE != 'true' ||
> env.RUN_TESTS == 'true'
> > +      if: env.AARCH64 != 'true' || env.PPC64LE != 'true' || env.RISCV64
> != 'true' || env.RUN_TESTS == 'true'
> >        run: sudo apt install -y gdb
> >      - name: Install doc generation packages
> >        if: env.BUILD_DOCS == 'true'
>
>

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Re: [PATCH v3 8/8] ci: add RISCV64 cross compilation job

[Aaron Conole]

Stanisław Kardach <kda@semihalf.com> writes:

> On Thu, 12 May 2022, 17:47 Aaron Conole, <aconole@redhat.com> wrote:
>
>  Stanislaw Kardach <kda@semihalf.com> writes:
>
>  > Checks cross-compilation using Ubuntu 20.04 x86.
>  >
>  > Signed-off-by: David Marchand <david.marchand@redhat.com>
>  > Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
>  > ---
>  >  .ci/linux-build.sh          |  4 ++++
>  >  .github/workflows/build.yml | 11 ++++++++++-
>  >  2 files changed, 14 insertions(+), 1 deletion(-)
>
>  Seems there is still a failure in this series - once that is resolved I
>  think this can go in.
>
> I suspect the failure is due to this series depending on 3 other patches which I've marked with Depends-on in the
> offending patch. Is CI utilizing those tags? If not, is there a way to relaunch it once dependencies are integrated?

Ahh okay - yes 0day bot doesn't currently use that.  It's planned for
after the system upgrade (date on that is pending).

>  > diff --git a/.ci/linux-build.sh b/.ci/linux-build.sh
>  > index 877243c9c8..aa5e9ec114 100755
>  > --- a/.ci/linux-build.sh
>  > +++ b/.ci/linux-build.sh
>  > @@ -74,6 +74,10 @@ if [ "$PPC64LE" = "true" ]; then
>  >      cross_file=config/ppc/ppc64le-power8-linux-gcc-ubuntu
>  >  fi
>  >  
>  > +if [ "$RISCV64" = "true" ]; then
>  > +    cross_file=config/riscv/riscv64_linux_gcc
>  > +fi
>  > +
>  >  if [ -n "$cross_file" ]; then
>  >      OPTS="$OPTS --cross-file $cross_file"
>  >  fi
>  > diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
>  > index e2f94d786b..ca468da8fa 100644
>  > --- a/.github/workflows/build.yml
>  > +++ b/.github/workflows/build.yml
>  > @@ -25,6 +25,7 @@ jobs:
>  >        MINI: ${{ matrix.config.mini != '' }}
>  >        PPC64LE: ${{ matrix.config.cross == 'ppc64le' }}
>  >        REF_GIT_TAG: v22.03
>  > +      RISCV64: ${{ matrix.config.cross == 'riscv64' }}
>  >        RUN_TESTS: ${{ contains(matrix.config.checks, 'tests') }}
>  >  
>  >      strategy:
>  > @@ -73,6 +74,10 @@ jobs:
>  >              compiler: gcc
>  >              library: shared
>  >              cross: ppc64le
>  > +          - os: ubuntu-20.04
>  > +            compiler: gcc
>  > +            library: shared
>  > +            cross: riscv64
>  >  
>  >      steps:
>  >      - name: Checkout sources
>  > @@ -131,8 +136,12 @@ jobs:
>  >        if: env.PPC64LE == 'true'
>  >        run: sudo apt install -y gcc-powerpc64le-linux-gnu libc6-dev-ppc64el-cross
>  >          pkg-config-powerpc-linux-gnu
>  > +    - name: Install riscv64 cross compiling packages
>  > +      if: env.RISCV64 == 'true'
>  > +      run: sudo apt install -y gcc-riscv64-linux-gnu libc6-dev-riscv64-cross
>  > +        pkg-config-riscv64-linux-gnu
>  >      - name: Install test tools packages
>  > -      if: env.AARCH64 != 'true' || env.PPC64LE != 'true' || env.RUN_TESTS == 'true'
>  > +      if: env.AARCH64 != 'true' || env.PPC64LE != 'true' || env.RISCV64 != 'true' || env.RUN_TESTS == 'true'
>  >        run: sudo apt install -y gdb
>  >      - name: Install doc generation packages
>  >        if: env.BUILD_DOCS == 'true'

Re: [PATCH 00/11] Introduce support for RISC-V architecture

[Heinrich Schuchardt]

On 5/5/22 19:29, Stanislaw Kardach wrote:
> This patchset adds support for building and running DPDK on 64bit RISC-V
> architecture. The initial support targets rv64gc (rv64imafdc) ISA and
> was tested on SiFive Unmatched development board with the Freedom U740
> SoC running Linux (freedom-u-sdk based kernel).
> I have tested this codebase using DPDK unit and perf tests as well as
> test-pmd, l2fwd and l3fwd examples.
> The NIC attached to the DUT was Intel X520-DA2 which uses ixgbe PMD.
> On the UIO side, since U740 does not have an IOMMU, I've used igb_uio,
> uio_pci_generic and vfio-pci noiommu drivers.
> 
> Commits 1-2 fix small issues which are encountered if a given platform
>     does not support any vector operations (which is the case with U740).
> Commit 3 introduces EAL and build system support for RISC-V architecture
>     as well as documentation updates.
> Commits 4-7 add missing defines and stubs to enable RISC-V operation in
>     non-EAL parts.
> Commit 8 adds RISC-V specific cpuflags test.
> Commit 9 works around a bug in the current GCC in test_ring compiled
>     with -O0 or -Og.
> Commit 10 adds RISC-V testing to test-meson-builds.sh automatically
>     iterating over cross-compile config files (currently present for
>     generic rv64gc and SiFive U740).
> Commit 11 extends hash r/w perf test by displaying both HTM and non-HTM
>     measurements. This is an extraneous commit which is not directly
>     needed for RISC-V support but was noticed when we have started
>     gathering test results. If needed, I can submit it separately.
> 
> I appreciate Your comments and feedback.
> 
> Best Regards,
> Stanislaw Kardach

On an SiFive Unmatched board with Ubuntu Jammy I have been compiling 
DPDK origin/main (36db4a1ad464) with this series and the test patches 
that you split off.

The fast tests are either skipped or succeed. But I have seen errors for 
the performance tests:

4 1GiB hugepages defined
no network devices bound
vfio_pci loaded (no IOMMU)

sudo meson -t 30

129/173 DPDK:perf-tests / pmd_perf_autotest FAIL 7.85s (exit status 255 
or signal 127 SIGinvalid)
 >>> DPDK_TEST=pmd_perf_autotest MALLOC_PERTURB_=135 
build/app/test/dpdk-test
136/173 DPDK:perf-tests / ipsec_perf_autotest FAIL 4.47s (exit status 
255 or signal 127 SIGinvalid)
 >>> MALLOC_PERTURB_=181 DPDK_TEST=ipsec_perf_autotest 
build/app/test/dpdk-test
160/173 DPDK:driver-tests / link_bonding_mode4_autotest FAIL 31.80s 
killed by signal 11 SIGSEGV
 >>> MALLOC_PERTURB_=62 DPDK_TEST=link_bonding_mode4_autotest 
build/app/test/dpdk-test

These are the patches used:

# [PATCH 1/1] lpm: add a scalar version of lookupx4 function
   https://inbox.dpdk.org/dev/20220510115824.457885-1-kda@semihalf.com/
# [PATCH 1/1] examples/l3fwd: fix scalar LPM compilation
   https://inbox.dpdk.org/dev/20220510115844.458009-1-kda@semihalf.com/
# [PATCH 1/1] test/hash: report non HTM numbers for single r/w
   https://inbox.dpdk.org/dev/20220510115734.457718-1-kda@semihalf.com/
# [PATCH 1/1] test/ring: remove excessive inlining
   https://inbox.dpdk.org/dev/20220510115758.457794-1-kda@semihalf.com/
# [PATCH v3 0/8] Introduce support for RISC-V architecture
   https://inbox.dpdk.org/dev/20220510154849.530872-1-kda@semihalf.com/
# [PATCH 1/1] drivers: define OPENSSL_API_COMPAT
 
https://inbox.dpdk.org/dev/20220510150635.61975-1-heinrich.schuchardt@canonical.com/

Running sudo app/test/dpdk-test does not show the errors:

RTE>>pmd_perf_autotest
Start PMD RXTX cycles cost test.
At least 1 port(s) used for perf. test
Test Failed
RTE>>ipsec_perf_autotest
USER1: rte_ipsec_pkt_crypto_prepare fail
Test Failed
RTE>>link_bonding_mode4_autotest
...
Test OK
RTE>

Best regards

Heinrich

> 
> NOTE: This work was sponsored by StarFive and SiFive which is signified by
>     "Sponsored-by:" sign-offs in each commit message. After discussing it
>     with Thomas Monjalon it seemed a better choice than "Suggested-by" which
>     does not fully convey the nature of involvement. However it makes
>     Linux checkpatch unhappy so I'm not sure if I shouldn't change the
>     sign-offs.
> 
> NOTE2: I have added maintainers for each commit based on MAINTAINERS file.
>     However some modules (l3fwd, net/tap and cpuflags unit tests) do not have
>     any maintainers assigned, hence I've targeted dev@dpdk.org mailing list as
>     if it was a commit adding new files.
> 
> Michal Mazurek (3):
>    lpm: add a scalar version of lookupx4 function
>    eal: add initial support for RISC-V architecture
>    test/cpuflags: add test for RISC-V cpu flag
> 
> Stanislaw Kardach (8):
>    examples/l3fwd: fix scalar LPM compilation
>    net/ixgbe: enable vector stubs for RISC-V
>    net/memif: set memfd syscall ID on RISC-V
>    net/tap: set BPF syscall ID for RISC-V
>    examples/l3fwd: enable RISC-V operation
>    test/ring: disable problematic tests for RISC-V
>    devtools: add RISC-V to test-meson-builds.sh
>    test/hash: report non HTM numbers for single r/w
> 
>   MAINTAINERS                                   |   6 +
>   app/test/test_cpuflags.c                      |  81 ++++++++++
>   app/test/test_hash_readwrite.c                |   8 +-
>   app/test/test_ring.c                          |   8 +
>   app/test/test_xmmt_ops.h                      |  16 ++
>   config/meson.build                            |   2 +
>   config/riscv/meson.build                      | 148 ++++++++++++++++++
>   config/riscv/riscv64_linux_gcc                |  17 ++
>   config/riscv/riscv64_sifive_u740_linux_gcc    |  19 +++
>   devtools/test-meson-builds.sh                 |   6 +
>   doc/guides/contributing/design.rst            |   2 +-
>   .../linux_gsg/cross_build_dpdk_for_riscv.rst  | 125 +++++++++++++++
>   doc/guides/linux_gsg/index.rst                |   1 +
>   doc/guides/nics/features.rst                  |   5 +
>   doc/guides/nics/features/default.ini          |   1 +
>   doc/guides/nics/features/ixgbe.ini            |   1 +
>   doc/guides/rel_notes/release_22_07.rst        |  29 ++++
>   drivers/net/i40e/meson.build                  |   6 +
>   drivers/net/ixgbe/ixgbe_rxtx.c                |   4 +-
>   drivers/net/memif/rte_eth_memif.h             |   2 +
>   drivers/net/tap/tap_bpf.h                     |   2 +
>   examples/l3fwd/l3fwd_em.c                     |   8 +
>   examples/l3fwd/l3fwd_fib.c                    |   2 +
>   examples/l3fwd/l3fwd_lpm.c                    |   2 +-
>   lib/eal/riscv/include/meson.build             |  23 +++
>   lib/eal/riscv/include/rte_atomic.h            |  52 ++++++
>   lib/eal/riscv/include/rte_byteorder.h         |  44 ++++++
>   lib/eal/riscv/include/rte_cpuflags.h          |  55 +++++++
>   lib/eal/riscv/include/rte_cycles.h            | 103 ++++++++++++
>   lib/eal/riscv/include/rte_io.h                |  21 +++
>   lib/eal/riscv/include/rte_mcslock.h           |  18 +++
>   lib/eal/riscv/include/rte_memcpy.h            |  63 ++++++++
>   lib/eal/riscv/include/rte_pause.h             |  31 ++++
>   lib/eal/riscv/include/rte_pflock.h            |  17 ++
>   lib/eal/riscv/include/rte_power_intrinsics.h  |  22 +++
>   lib/eal/riscv/include/rte_prefetch.h          |  50 ++++++
>   lib/eal/riscv/include/rte_rwlock.h            |  44 ++++++
>   lib/eal/riscv/include/rte_spinlock.h          |  67 ++++++++
>   lib/eal/riscv/include/rte_ticketlock.h        |  21 +++
>   lib/eal/riscv/include/rte_vect.h              |  55 +++++++
>   lib/eal/riscv/meson.build                     |  11 ++
>   lib/eal/riscv/rte_cpuflags.c                  | 122 +++++++++++++++
>   lib/eal/riscv/rte_cycles.c                    |  77 +++++++++
>   lib/eal/riscv/rte_hypervisor.c                |  13 ++
>   lib/eal/riscv/rte_power_intrinsics.c          |  56 +++++++
>   lib/lpm/meson.build                           |   1 +
>   lib/lpm/rte_lpm.h                             |   4 +-
>   lib/lpm/rte_lpm_scalar.h                      | 122 +++++++++++++++
>   meson.build                                   |   2 +
>   49 files changed, 1588 insertions(+), 7 deletions(-)
>   create mode 100644 config/riscv/meson.build
>   create mode 100644 config/riscv/riscv64_linux_gcc
>   create mode 100644 config/riscv/riscv64_sifive_u740_linux_gcc
>   create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
>   create mode 100644 lib/eal/riscv/include/meson.build
>   create mode 100644 lib/eal/riscv/include/rte_atomic.h
>   create mode 100644 lib/eal/riscv/include/rte_byteorder.h
>   create mode 100644 lib/eal/riscv/include/rte_cpuflags.h
>   create mode 100644 lib/eal/riscv/include/rte_cycles.h
>   create mode 100644 lib/eal/riscv/include/rte_io.h
>   create mode 100644 lib/eal/riscv/include/rte_mcslock.h
>   create mode 100644 lib/eal/riscv/include/rte_memcpy.h
>   create mode 100644 lib/eal/riscv/include/rte_pause.h
>   create mode 100644 lib/eal/riscv/include/rte_pflock.h
>   create mode 100644 lib/eal/riscv/include/rte_power_intrinsics.h
>   create mode 100644 lib/eal/riscv/include/rte_prefetch.h
>   create mode 100644 lib/eal/riscv/include/rte_rwlock.h
>   create mode 100644 lib/eal/riscv/include/rte_spinlock.h
>   create mode 100644 lib/eal/riscv/include/rte_ticketlock.h
>   create mode 100644 lib/eal/riscv/include/rte_vect.h
>   create mode 100644 lib/eal/riscv/meson.build
>   create mode 100644 lib/eal/riscv/rte_cpuflags.c
>   create mode 100644 lib/eal/riscv/rte_cycles.c
>   create mode 100644 lib/eal/riscv/rte_hypervisor.c
>   create mode 100644 lib/eal/riscv/rte_power_intrinsics.c
>   create mode 100644 lib/lpm/rte_lpm_scalar.h
> 

Re: [PATCH 00/11] Introduce support for RISC-V architecture

[Stanisław Kardach]

On Thu, May 12, 2022 at 10:04 AM Heinrich Schuchardt
<heinrich.schuchardt@canonical.com> wrote:
>
> On 5/5/22 19:29, Stanislaw Kardach wrote:
> > This patchset adds support for building and running DPDK on 64bit RISC-V
> > architecture. The initial support targets rv64gc (rv64imafdc) ISA and
> > was tested on SiFive Unmatched development board with the Freedom U740
> > SoC running Linux (freedom-u-sdk based kernel).
> > I have tested this codebase using DPDK unit and perf tests as well as
> > test-pmd, l2fwd and l3fwd examples.
> > The NIC attached to the DUT was Intel X520-DA2 which uses ixgbe PMD.
> > On the UIO side, since U740 does not have an IOMMU, I've used igb_uio,
> > uio_pci_generic and vfio-pci noiommu drivers.
> >
> > Commits 1-2 fix small issues which are encountered if a given platform
> >     does not support any vector operations (which is the case with U740).
> > Commit 3 introduces EAL and build system support for RISC-V architecture
> >     as well as documentation updates.
> > Commits 4-7 add missing defines and stubs to enable RISC-V operation in
> >     non-EAL parts.
> > Commit 8 adds RISC-V specific cpuflags test.
> > Commit 9 works around a bug in the current GCC in test_ring compiled
> >     with -O0 or -Og.
> > Commit 10 adds RISC-V testing to test-meson-builds.sh automatically
> >     iterating over cross-compile config files (currently present for
> >     generic rv64gc and SiFive U740).
> > Commit 11 extends hash r/w perf test by displaying both HTM and non-HTM
> >     measurements. This is an extraneous commit which is not directly
> >     needed for RISC-V support but was noticed when we have started
> >     gathering test results. If needed, I can submit it separately.
> >
> > I appreciate Your comments and feedback.
> >
> > Best Regards,
> > Stanislaw Kardach
>
> On an SiFive Unmatched board with Ubuntu Jammy I have been compiling
> DPDK origin/main (36db4a1ad464) with this series and the test patches
> that you split off.
Thank you for testing!
>
> The fast tests are either skipped or succeed. But I have seen errors for
> the performance tests:
>
> 4 1GiB hugepages defined
> no network devices bound
> vfio_pci loaded (no IOMMU)
>
> sudo meson -t 30
>
> 129/173 DPDK:perf-tests / pmd_perf_autotest FAIL 7.85s (exit status 255
> or signal 127 SIGinvalid)
>  >>> DPDK_TEST=pmd_perf_autotest MALLOC_PERTURB_=135
> build/app/test/dpdk-test
This test I believe requires at least a single NIC port. Conversely
fast-tests seem to fail if a device is bound. DPDK CI doesn't bind any
on fast-tests, I'm not sure if perf-tests suite is run there.
On my local x86 machine perf-tests suite fails when no device is bound too.

> 136/173 DPDK:perf-tests / ipsec_perf_autotest FAIL 4.47s (exit status
> 255 or signal 127 SIGinvalid)
>  >>> MALLOC_PERTURB_=181 DPDK_TEST=ipsec_perf_autotest
> build/app/test/dpdk-test
On my unmatched I don't have openssl compiled so most crypto tests are
skipped (since no openssl is installed), aside of this one and it
indeed fails. I'm not sure whether it's a matter of a lack of a guard
to skip this test if there's no crypto backend built or if it's a real
issue.
I admit I haven't tried crypto libraries with RISC-V openssl as
there's no real HW offloading on Unmatched.

> 160/173 DPDK:driver-tests / link_bonding_mode4_autotest FAIL 31.80s
> killed by signal 11 SIGSEGV
>  >>> MALLOC_PERTURB_=62 DPDK_TEST=link_bonding_mode4_autotest
> build/app/test/dpdk-test
I use -t40 when testing on Unmatched. Unfortunately lots of the tests
hit timeouts.

>
> These are the patches used:
>
> # [PATCH 1/1] lpm: add a scalar version of lookupx4 function
>    https://inbox.dpdk.org/dev/20220510115824.457885-1-kda@semihalf.com/
> # [PATCH 1/1] examples/l3fwd: fix scalar LPM compilation
>    https://inbox.dpdk.org/dev/20220510115844.458009-1-kda@semihalf.com/
> # [PATCH 1/1] test/hash: report non HTM numbers for single r/w
>    https://inbox.dpdk.org/dev/20220510115734.457718-1-kda@semihalf.com/
> # [PATCH 1/1] test/ring: remove excessive inlining
>    https://inbox.dpdk.org/dev/20220510115758.457794-1-kda@semihalf.com/
> # [PATCH v3 0/8] Introduce support for RISC-V architecture
>    https://inbox.dpdk.org/dev/20220510154849.530872-1-kda@semihalf.com/
> # [PATCH 1/1] drivers: define OPENSSL_API_COMPAT
>
> https://inbox.dpdk.org/dev/20220510150635.61975-1-heinrich.schuchardt@canonical.com/
>
> Running sudo app/test/dpdk-test does not show the errors:
>
> RTE>>pmd_perf_autotest
> Start PMD RXTX cycles cost test.
> At least 1 port(s) used for perf. test
> Test Failed
> RTE>>ipsec_perf_autotest
> USER1: rte_ipsec_pkt_crypto_prepare fail
> Test Failed
> RTE>>link_bonding_mode4_autotest
> ...
> Test OK
> RTE>
>
> Best regards
>
> Heinrich
>
> >
> > NOTE: This work was sponsored by StarFive and SiFive which is signified by
> >     "Sponsored-by:" sign-offs in each commit message. After discussing it
> >     with Thomas Monjalon it seemed a better choice than "Suggested-by" which
> >     does not fully convey the nature of involvement. However it makes
> >     Linux checkpatch unhappy so I'm not sure if I shouldn't change the
> >     sign-offs.
> >
> > NOTE2: I have added maintainers for each commit based on MAINTAINERS file.
> >     However some modules (l3fwd, net/tap and cpuflags unit tests) do not have
> >     any maintainers assigned, hence I've targeted dev@dpdk.org mailing list as
> >     if it was a commit adding new files.
> >
> > Michal Mazurek (3):
> >    lpm: add a scalar version of lookupx4 function
> >    eal: add initial support for RISC-V architecture
> >    test/cpuflags: add test for RISC-V cpu flag
> >
> > Stanislaw Kardach (8):
> >    examples/l3fwd: fix scalar LPM compilation
> >    net/ixgbe: enable vector stubs for RISC-V
> >    net/memif: set memfd syscall ID on RISC-V
> >    net/tap: set BPF syscall ID for RISC-V
> >    examples/l3fwd: enable RISC-V operation
> >    test/ring: disable problematic tests for RISC-V
> >    devtools: add RISC-V to test-meson-builds.sh
> >    test/hash: report non HTM numbers for single r/w
> >
> >   MAINTAINERS                                   |   6 +
> >   app/test/test_cpuflags.c                      |  81 ++++++++++
> >   app/test/test_hash_readwrite.c                |   8 +-
> >   app/test/test_ring.c                          |   8 +
> >   app/test/test_xmmt_ops.h                      |  16 ++
> >   config/meson.build                            |   2 +
> >   config/riscv/meson.build                      | 148 ++++++++++++++++++
> >   config/riscv/riscv64_linux_gcc                |  17 ++
> >   config/riscv/riscv64_sifive_u740_linux_gcc    |  19 +++
> >   devtools/test-meson-builds.sh                 |   6 +
> >   doc/guides/contributing/design.rst            |   2 +-
> >   .../linux_gsg/cross_build_dpdk_for_riscv.rst  | 125 +++++++++++++++
> >   doc/guides/linux_gsg/index.rst                |   1 +
> >   doc/guides/nics/features.rst                  |   5 +
> >   doc/guides/nics/features/default.ini          |   1 +
> >   doc/guides/nics/features/ixgbe.ini            |   1 +
> >   doc/guides/rel_notes/release_22_07.rst        |  29 ++++
> >   drivers/net/i40e/meson.build                  |   6 +
> >   drivers/net/ixgbe/ixgbe_rxtx.c                |   4 +-
> >   drivers/net/memif/rte_eth_memif.h             |   2 +
> >   drivers/net/tap/tap_bpf.h                     |   2 +
> >   examples/l3fwd/l3fwd_em.c                     |   8 +
> >   examples/l3fwd/l3fwd_fib.c                    |   2 +
> >   examples/l3fwd/l3fwd_lpm.c                    |   2 +-
> >   lib/eal/riscv/include/meson.build             |  23 +++
> >   lib/eal/riscv/include/rte_atomic.h            |  52 ++++++
> >   lib/eal/riscv/include/rte_byteorder.h         |  44 ++++++
> >   lib/eal/riscv/include/rte_cpuflags.h          |  55 +++++++
> >   lib/eal/riscv/include/rte_cycles.h            | 103 ++++++++++++
> >   lib/eal/riscv/include/rte_io.h                |  21 +++
> >   lib/eal/riscv/include/rte_mcslock.h           |  18 +++
> >   lib/eal/riscv/include/rte_memcpy.h            |  63 ++++++++
> >   lib/eal/riscv/include/rte_pause.h             |  31 ++++
> >   lib/eal/riscv/include/rte_pflock.h            |  17 ++
> >   lib/eal/riscv/include/rte_power_intrinsics.h  |  22 +++
> >   lib/eal/riscv/include/rte_prefetch.h          |  50 ++++++
> >   lib/eal/riscv/include/rte_rwlock.h            |  44 ++++++
> >   lib/eal/riscv/include/rte_spinlock.h          |  67 ++++++++
> >   lib/eal/riscv/include/rte_ticketlock.h        |  21 +++
> >   lib/eal/riscv/include/rte_vect.h              |  55 +++++++
> >   lib/eal/riscv/meson.build                     |  11 ++
> >   lib/eal/riscv/rte_cpuflags.c                  | 122 +++++++++++++++
> >   lib/eal/riscv/rte_cycles.c                    |  77 +++++++++
> >   lib/eal/riscv/rte_hypervisor.c                |  13 ++
> >   lib/eal/riscv/rte_power_intrinsics.c          |  56 +++++++
> >   lib/lpm/meson.build                           |   1 +
> >   lib/lpm/rte_lpm.h                             |   4 +-
> >   lib/lpm/rte_lpm_scalar.h                      | 122 +++++++++++++++
> >   meson.build                                   |   2 +
> >   49 files changed, 1588 insertions(+), 7 deletions(-)
> >   create mode 100644 config/riscv/meson.build
> >   create mode 100644 config/riscv/riscv64_linux_gcc
> >   create mode 100644 config/riscv/riscv64_sifive_u740_linux_gcc
> >   create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
> >   create mode 100644 lib/eal/riscv/include/meson.build
> >   create mode 100644 lib/eal/riscv/include/rte_atomic.h
> >   create mode 100644 lib/eal/riscv/include/rte_byteorder.h
> >   create mode 100644 lib/eal/riscv/include/rte_cpuflags.h
> >   create mode 100644 lib/eal/riscv/include/rte_cycles.h
> >   create mode 100644 lib/eal/riscv/include/rte_io.h
> >   create mode 100644 lib/eal/riscv/include/rte_mcslock.h
> >   create mode 100644 lib/eal/riscv/include/rte_memcpy.h
> >   create mode 100644 lib/eal/riscv/include/rte_pause.h
> >   create mode 100644 lib/eal/riscv/include/rte_pflock.h
> >   create mode 100644 lib/eal/riscv/include/rte_power_intrinsics.h
> >   create mode 100644 lib/eal/riscv/include/rte_prefetch.h
> >   create mode 100644 lib/eal/riscv/include/rte_rwlock.h
> >   create mode 100644 lib/eal/riscv/include/rte_spinlock.h
> >   create mode 100644 lib/eal/riscv/include/rte_ticketlock.h
> >   create mode 100644 lib/eal/riscv/include/rte_vect.h
> >   create mode 100644 lib/eal/riscv/meson.build
> >   create mode 100644 lib/eal/riscv/rte_cpuflags.c
> >   create mode 100644 lib/eal/riscv/rte_cycles.c
> >   create mode 100644 lib/eal/riscv/rte_hypervisor.c
> >   create mode 100644 lib/eal/riscv/rte_power_intrinsics.c
> >   create mode 100644 lib/lpm/rte_lpm_scalar.h
> >
>

Re: [PATCH 00/11] Introduce support for RISC-V architecture

[Heinrich Schuchardt]

On 5/12/22 10:35, Stanisław Kardach wrote:
> On Thu, May 12, 2022 at 10:04 AM Heinrich Schuchardt
> <heinrich.schuchardt@canonical.com> wrote:
>>
>> On 5/5/22 19:29, Stanislaw Kardach wrote:
>>> This patchset adds support for building and running DPDK on 64bit RISC-V
>>> architecture. The initial support targets rv64gc (rv64imafdc) ISA and
>>> was tested on SiFive Unmatched development board with the Freedom U740
>>> SoC running Linux (freedom-u-sdk based kernel).
>>> I have tested this codebase using DPDK unit and perf tests as well as
>>> test-pmd, l2fwd and l3fwd examples.
>>> The NIC attached to the DUT was Intel X520-DA2 which uses ixgbe PMD.
>>> On the UIO side, since U740 does not have an IOMMU, I've used igb_uio,
>>> uio_pci_generic and vfio-pci noiommu drivers.
>>>
>>> Commits 1-2 fix small issues which are encountered if a given platform
>>>      does not support any vector operations (which is the case with U740).
>>> Commit 3 introduces EAL and build system support for RISC-V architecture
>>>      as well as documentation updates.
>>> Commits 4-7 add missing defines and stubs to enable RISC-V operation in
>>>      non-EAL parts.
>>> Commit 8 adds RISC-V specific cpuflags test.
>>> Commit 9 works around a bug in the current GCC in test_ring compiled
>>>      with -O0 or -Og.
>>> Commit 10 adds RISC-V testing to test-meson-builds.sh automatically
>>>      iterating over cross-compile config files (currently present for
>>>      generic rv64gc and SiFive U740).
>>> Commit 11 extends hash r/w perf test by displaying both HTM and non-HTM
>>>      measurements. This is an extraneous commit which is not directly
>>>      needed for RISC-V support but was noticed when we have started
>>>      gathering test results. If needed, I can submit it separately.
>>>
>>> I appreciate Your comments and feedback.
>>>
>>> Best Regards,
>>> Stanislaw Kardach
>>
>> On an SiFive Unmatched board with Ubuntu Jammy I have been compiling
>> DPDK origin/main (36db4a1ad464) with this series and the test patches
>> that you split off.
> Thank you for testing!
>>
>> The fast tests are either skipped or succeed. But I have seen errors for
>> the performance tests:
>>
>> 4 1GiB hugepages defined
>> no network devices bound
>> vfio_pci loaded (no IOMMU)
>>
>> sudo meson -t 30
>>
>> 129/173 DPDK:perf-tests / pmd_perf_autotest FAIL 7.85s (exit status 255
>> or signal 127 SIGinvalid)
>>   >>> DPDK_TEST=pmd_perf_autotest MALLOC_PERTURB_=135
>> build/app/test/dpdk-test
> This test I believe requires at least a single NIC port. Conversely
> fast-tests seem to fail if a device is bound. DPDK CI doesn't bind any
> on fast-tests, I'm not sure if perf-tests suite is run there.
> On my local x86 machine perf-tests suite fails when no device is bound too.
> 
>> 136/173 DPDK:perf-tests / ipsec_perf_autotest FAIL 4.47s (exit status
>> 255 or signal 127 SIGinvalid)
>>   >>> MALLOC_PERTURB_=181 DPDK_TEST=ipsec_perf_autotest
>> build/app/test/dpdk-test
> On my unmatched I don't have openssl compiled so most crypto tests are
> skipped (since no openssl is installed), aside of this one and it
> indeed fails. I'm not sure whether it's a matter of a lack of a guard
> to skip this test if there's no crypto backend built or if it's a real
> issue.
> I admit I haven't tried crypto libraries with RISC-V openssl as
> there's no real HW offloading on Unmatched.
> 
>> 160/173 DPDK:driver-tests / link_bonding_mode4_autotest FAIL 31.80s
>> killed by signal 11 SIGSEGV
>>   >>> MALLOC_PERTURB_=62 DPDK_TEST=link_bonding_mode4_autotest
>> build/app/test/dpdk-test
> I use -t40 when testing on Unmatched. Unfortunately lots of the tests
> hit timeouts.
> 
>>
>> These are the patches used:
>>
>> # [PATCH 1/1] lpm: add a scalar version of lookupx4 function
>>     https://inbox.dpdk.org/dev/20220510115824.457885-1-kda@semihalf.com/
>> # [PATCH 1/1] examples/l3fwd: fix scalar LPM compilation
>>     https://inbox.dpdk.org/dev/20220510115844.458009-1-kda@semihalf.com/
>> # [PATCH 1/1] test/hash: report non HTM numbers for single r/w
>>     https://inbox.dpdk.org/dev/20220510115734.457718-1-kda@semihalf.com/
>> # [PATCH 1/1] test/ring: remove excessive inlining
>>     https://inbox.dpdk.org/dev/20220510115758.457794-1-kda@semihalf.com/
>> # [PATCH v3 0/8] Introduce support for RISC-V architecture
>>     https://inbox.dpdk.org/dev/20220510154849.530872-1-kda@semihalf.com/
>> # [PATCH 1/1] drivers: define OPENSSL_API_COMPAT
>>
>> https://inbox.dpdk.org/dev/20220510150635.61975-1-heinrich.schuchardt@canonical.com/
>>
>> Running sudo app/test/dpdk-test does not show the errors:
>>
>> RTE>>pmd_perf_autotest
>> Start PMD RXTX cycles cost test.
>> At least 1 port(s) used for perf. test
>> Test Failed
>> RTE>>ipsec_perf_autotest
>> USER1: rte_ipsec_pkt_crypto_prepare fail
>> Test Failed
>> RTE>>link_bonding_mode4_autotest
>> ...
>> Test OK
>> RTE>
>>
>> Best regards
>>
>> Heinrich+

The above failures for performance tests without a bound NIC can be 
reproduced on x86_64. So this is not RISC-V specific.

With both ports of an Intel Corporation Ethernet Controller 10-Gigabit 
X540-AT2 bound to the sfio-pci driver some fast tests fail on the 
Unmatched board:

  16/173 DPDK:fast-tests / eal_flags_n_opt_autotest FAIL 5.54s (exit 
status 255 or signal 127 SIGinvalid)
 >>> DPDK_TEST=eal_flags_n_opt_autotest MALLOC_PERTURB_=31 
build/app/test/dpdk-test --file-prefix=eal_flags_n_opt_autotest
  18/173 DPDK:fast-tests / eal_flags_no_huge_autotest FAIL 5.31s (exit 
status 255 or signal 127 SIGinvalid)
 >>> DPDK_TEST=eal_flags_no_huge_autotest MALLOC_PERTURB_=150 
build/app/test/dpdk-test --file-prefix=eal_flags_no_huge_autotest
  21/173 DPDK:fast-tests / eal_flags_vdev_opt_autotest FAIL 5.38s (exit 
status 255 or signal 127 SIGinvalid)
 >>> MALLOC_PERTURB_=71 DPDK_TEST=eal_flags_vdev_opt_autotest 
build/app/test/dpdk-test --file-prefix=eal_flags_vdev_opt_autotest
  25/173 DPDK:fast-tests / eal_flags_misc_autotest FAIL 5.58s (exit 
status 255 or signal 127 SIGinvalid)
 >>> DPDK_TEST=eal_flags_misc_autotest MALLOC_PERTURB_=130 
build/app/test/dpdk-test --file-prefix=eal_flags_misc_autotest

The eal* tests succeed on x86_64 with a bound Intel I211 NIC.

If the eal* tests are run depends on the installed Linux packages. I 
have used 'apt build-dep dpdk' on Ubuntu Jammy to install prerequisite 
packages before building DPDK.

Best regards

Heinrich

>>
>>>
>>> NOTE: This work was sponsored by StarFive and SiFive which is signified by
>>>      "Sponsored-by:" sign-offs in each commit message. After discussing it
>>>      with Thomas Monjalon it seemed a better choice than "Suggested-by" which
>>>      does not fully convey the nature of involvement. However it makes
>>>      Linux checkpatch unhappy so I'm not sure if I shouldn't change the
>>>      sign-offs.
>>>
>>> NOTE2: I have added maintainers for each commit based on MAINTAINERS file.
>>>      However some modules (l3fwd, net/tap and cpuflags unit tests) do not have
>>>      any maintainers assigned, hence I've targeted dev@dpdk.org mailing list as
>>>      if it was a commit adding new files.
>>>
>>> Michal Mazurek (3):
>>>     lpm: add a scalar version of lookupx4 function
>>>     eal: add initial support for RISC-V architecture
>>>     test/cpuflags: add test for RISC-V cpu flag
>>>
>>> Stanislaw Kardach (8):
>>>     examples/l3fwd: fix scalar LPM compilation
>>>     net/ixgbe: enable vector stubs for RISC-V
>>>     net/memif: set memfd syscall ID on RISC-V
>>>     net/tap: set BPF syscall ID for RISC-V
>>>     examples/l3fwd: enable RISC-V operation
>>>     test/ring: disable problematic tests for RISC-V
>>>     devtools: add RISC-V to test-meson-builds.sh
>>>     test/hash: report non HTM numbers for single r/w
>>>
>>>    MAINTAINERS                                   |   6 +
>>>    app/test/test_cpuflags.c                      |  81 ++++++++++
>>>    app/test/test_hash_readwrite.c                |   8 +-
>>>    app/test/test_ring.c                          |   8 +
>>>    app/test/test_xmmt_ops.h                      |  16 ++
>>>    config/meson.build                            |   2 +
>>>    config/riscv/meson.build                      | 148 ++++++++++++++++++
>>>    config/riscv/riscv64_linux_gcc                |  17 ++
>>>    config/riscv/riscv64_sifive_u740_linux_gcc    |  19 +++
>>>    devtools/test-meson-builds.sh                 |   6 +
>>>    doc/guides/contributing/design.rst            |   2 +-
>>>    .../linux_gsg/cross_build_dpdk_for_riscv.rst  | 125 +++++++++++++++
>>>    doc/guides/linux_gsg/index.rst                |   1 +
>>>    doc/guides/nics/features.rst                  |   5 +
>>>    doc/guides/nics/features/default.ini          |   1 +
>>>    doc/guides/nics/features/ixgbe.ini            |   1 +
>>>    doc/guides/rel_notes/release_22_07.rst        |  29 ++++
>>>    drivers/net/i40e/meson.build                  |   6 +
>>>    drivers/net/ixgbe/ixgbe_rxtx.c                |   4 +-
>>>    drivers/net/memif/rte_eth_memif.h             |   2 +
>>>    drivers/net/tap/tap_bpf.h                     |   2 +
>>>    examples/l3fwd/l3fwd_em.c                     |   8 +
>>>    examples/l3fwd/l3fwd_fib.c                    |   2 +
>>>    examples/l3fwd/l3fwd_lpm.c                    |   2 +-
>>>    lib/eal/riscv/include/meson.build             |  23 +++
>>>    lib/eal/riscv/include/rte_atomic.h            |  52 ++++++
>>>    lib/eal/riscv/include/rte_byteorder.h         |  44 ++++++
>>>    lib/eal/riscv/include/rte_cpuflags.h          |  55 +++++++
>>>    lib/eal/riscv/include/rte_cycles.h            | 103 ++++++++++++
>>>    lib/eal/riscv/include/rte_io.h                |  21 +++
>>>    lib/eal/riscv/include/rte_mcslock.h           |  18 +++
>>>    lib/eal/riscv/include/rte_memcpy.h            |  63 ++++++++
>>>    lib/eal/riscv/include/rte_pause.h             |  31 ++++
>>>    lib/eal/riscv/include/rte_pflock.h            |  17 ++
>>>    lib/eal/riscv/include/rte_power_intrinsics.h  |  22 +++
>>>    lib/eal/riscv/include/rte_prefetch.h          |  50 ++++++
>>>    lib/eal/riscv/include/rte_rwlock.h            |  44 ++++++
>>>    lib/eal/riscv/include/rte_spinlock.h          |  67 ++++++++
>>>    lib/eal/riscv/include/rte_ticketlock.h        |  21 +++
>>>    lib/eal/riscv/include/rte_vect.h              |  55 +++++++
>>>    lib/eal/riscv/meson.build                     |  11 ++
>>>    lib/eal/riscv/rte_cpuflags.c                  | 122 +++++++++++++++
>>>    lib/eal/riscv/rte_cycles.c                    |  77 +++++++++
>>>    lib/eal/riscv/rte_hypervisor.c                |  13 ++
>>>    lib/eal/riscv/rte_power_intrinsics.c          |  56 +++++++
>>>    lib/lpm/meson.build                           |   1 +
>>>    lib/lpm/rte_lpm.h                             |   4 +-
>>>    lib/lpm/rte_lpm_scalar.h                      | 122 +++++++++++++++
>>>    meson.build                                   |   2 +
>>>    49 files changed, 1588 insertions(+), 7 deletions(-)
>>>    create mode 100644 config/riscv/meson.build
>>>    create mode 100644 config/riscv/riscv64_linux_gcc
>>>    create mode 100644 config/riscv/riscv64_sifive_u740_linux_gcc
>>>    create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst
>>>    create mode 100644 lib/eal/riscv/include/meson.build
>>>    create mode 100644 lib/eal/riscv/include/rte_atomic.h
>>>    create mode 100644 lib/eal/riscv/include/rte_byteorder.h
>>>    create mode 100644 lib/eal/riscv/include/rte_cpuflags.h
>>>    create mode 100644 lib/eal/riscv/include/rte_cycles.h
>>>    create mode 100644 lib/eal/riscv/include/rte_io.h
>>>    create mode 100644 lib/eal/riscv/include/rte_mcslock.h
>>>    create mode 100644 lib/eal/riscv/include/rte_memcpy.h
>>>    create mode 100644 lib/eal/riscv/include/rte_pause.h
>>>    create mode 100644 lib/eal/riscv/include/rte_pflock.h
>>>    create mode 100644 lib/eal/riscv/include/rte_power_intrinsics.h
>>>    create mode 100644 lib/eal/riscv/include/rte_prefetch.h
>>>    create mode 100644 lib/eal/riscv/include/rte_rwlock.h
>>>    create mode 100644 lib/eal/riscv/include/rte_spinlock.h
>>>    create mode 100644 lib/eal/riscv/include/rte_ticketlock.h
>>>    create mode 100644 lib/eal/riscv/include/rte_vect.h
>>>    create mode 100644 lib/eal/riscv/meson.build
>>>    create mode 100644 lib/eal/riscv/rte_cpuflags.c
>>>    create mode 100644 lib/eal/riscv/rte_cycles.c
>>>    create mode 100644 lib/eal/riscv/rte_hypervisor.c
>>>    create mode 100644 lib/eal/riscv/rte_power_intrinsics.c
>>>    create mode 100644 lib/lpm/rte_lpm_scalar.h
>>>
>>

Re: [PATCH 00/11] Introduce support for RISC-V architecture

[Stanisław Kardach]

On Thu, May 12, 2022 at 11:46 AM Heinrich Schuchardt
<heinrich.schuchardt@canonical.com> wrote:
<snip>
> The above failures for performance tests without a bound NIC can be
> reproduced on x86_64. So this is not RISC-V specific.
>
> With both ports of an Intel Corporation Ethernet Controller 10-Gigabit
> X540-AT2 bound to the sfio-pci driver some fast tests fail on the
> Unmatched board:
>
>   16/173 DPDK:fast-tests / eal_flags_n_opt_autotest FAIL 5.54s (exit
> status 255 or signal 127 SIGinvalid)
>  >>> DPDK_TEST=eal_flags_n_opt_autotest MALLOC_PERTURB_=31
> build/app/test/dpdk-test --file-prefix=eal_flags_n_opt_autotest
>   18/173 DPDK:fast-tests / eal_flags_no_huge_autotest FAIL 5.31s (exit
> status 255 or signal 127 SIGinvalid)
>  >>> DPDK_TEST=eal_flags_no_huge_autotest MALLOC_PERTURB_=150
> build/app/test/dpdk-test --file-prefix=eal_flags_no_huge_autotest
>   21/173 DPDK:fast-tests / eal_flags_vdev_opt_autotest FAIL 5.38s (exit
> status 255 or signal 127 SIGinvalid)
>  >>> MALLOC_PERTURB_=71 DPDK_TEST=eal_flags_vdev_opt_autotest
> build/app/test/dpdk-test --file-prefix=eal_flags_vdev_opt_autotest
>   25/173 DPDK:fast-tests / eal_flags_misc_autotest FAIL 5.58s (exit
> status 255 or signal 127 SIGinvalid)
>  >>> DPDK_TEST=eal_flags_misc_autotest MALLOC_PERTURB_=130
> build/app/test/dpdk-test --file-prefix=eal_flags_misc_autotest
>
> The eal* tests succeed on x86_64 with a bound Intel I211 NIC.
The common element of those tests is --no-huge flag. The reason why
they are failing is a combination of --no-huge and a lack of IOMMU
(VT-d on Intel). Lack of IOMMU means that DMA will be done using
physical addresses (RTE_IOVA_PA), however that implicitly requires
hugepages to function. More details are in [1]. That mail also shows
how to replicate the same issue on x86 even without a device bound to
UIO.
The following fails:
  $ ./app/test/dpdk-test --iova-mode=pa --no-huge
But this works:
  sudo ./app/test/dpdk-test --iova-mode=pa
However fixing it is not as straightforward as I thought (some tests
are not run where they should - [3]). As I explain in [2], the PCI bus
probing may force RTE_IOVA_PA on no-IOMMU platforms. That gives the
same effect as passing `--iova-mode=pa`. If no PCI device is bound,
then DPDK will be in RTE_IOVA_DC mode and that works just fine with
--no-huge.

As DPDK CI does not bind any device for fast-tests I've concluded that
it is the way those tests should be run. If not then I'm not sure how
should I handle --iova-mode=pa + --no-huge in general. Any
suggestions?

[1] http://mails.dpdk.org/archives/dev/2021-June/210773.html
[2] http://mails.dpdk.org/archives/dev/2021-June/211146.html
[3] https://patches.dpdk.org/project/dpdk/patch/20210604141601.275430-4-kda@semihalf.com/

>
> If the eal* tests are run depends on the installed Linux packages. I
> have used 'apt build-dep dpdk' on Ubuntu Jammy to install prerequisite
> packages before building DPDK.
>
> Best regards
>
> Heinrich
>

Re: [PATCH 00/11] Introduce support for RISC-V architecture

[Heinrich Schuchardt]

On 5/12/22 15:56, Stanisław Kardach wrote:
> On Thu, May 12, 2022 at 11:46 AM Heinrich Schuchardt
> <heinrich.schuchardt@canonical.com> wrote:
> <snip>
>> The above failures for performance tests without a bound NIC can be
>> reproduced on x86_64. So this is not RISC-V specific.
>>
>> With both ports of an Intel Corporation Ethernet Controller 10-Gigabit
>> X540-AT2 bound to the sfio-pci driver some fast tests fail on the
>> Unmatched board:
>>
>>    16/173 DPDK:fast-tests / eal_flags_n_opt_autotest FAIL 5.54s (exit
>> status 255 or signal 127 SIGinvalid)
>>   >>> DPDK_TEST=eal_flags_n_opt_autotest MALLOC_PERTURB_=31
>> build/app/test/dpdk-test --file-prefix=eal_flags_n_opt_autotest
>>    18/173 DPDK:fast-tests / eal_flags_no_huge_autotest FAIL 5.31s (exit
>> status 255 or signal 127 SIGinvalid)
>>   >>> DPDK_TEST=eal_flags_no_huge_autotest MALLOC_PERTURB_=150
>> build/app/test/dpdk-test --file-prefix=eal_flags_no_huge_autotest
>>    21/173 DPDK:fast-tests / eal_flags_vdev_opt_autotest FAIL 5.38s (exit
>> status 255 or signal 127 SIGinvalid)
>>   >>> MALLOC_PERTURB_=71 DPDK_TEST=eal_flags_vdev_opt_autotest
>> build/app/test/dpdk-test --file-prefix=eal_flags_vdev_opt_autotest
>>    25/173 DPDK:fast-tests / eal_flags_misc_autotest FAIL 5.58s (exit
>> status 255 or signal 127 SIGinvalid)
>>   >>> DPDK_TEST=eal_flags_misc_autotest MALLOC_PERTURB_=130
>> build/app/test/dpdk-test --file-prefix=eal_flags_misc_autotest
>>
>> The eal* tests succeed on x86_64 with a bound Intel I211 NIC.
> The common element of those tests is --no-huge flag. The reason why
> they are failing is a combination of --no-huge and a lack of IOMMU
> (VT-d on Intel). Lack of IOMMU means that DMA will be done using
> physical addresses (RTE_IOVA_PA), however that implicitly requires
> hugepages to function. More details are in [1]. That mail also shows
> how to replicate the same issue on x86 even without a device bound to
> UIO.
> The following fails:
>    $ ./app/test/dpdk-test --iova-mode=pa --no-huge
> But this works:
>    sudo ./app/test/dpdk-test --iova-mode=pa
> However fixing it is not as straightforward as I thought (some tests
> are not run where they should - [3]). As I explain in [2], the PCI bus
> probing may force RTE_IOVA_PA on no-IOMMU platforms. That gives the
> same effect as passing `--iova-mode=pa`. If no PCI device is bound,
> then DPDK will be in RTE_IOVA_DC mode and that works just fine with
> --no-huge.
> 
> As DPDK CI does not bind any device for fast-tests I've concluded that
> it is the way those tests should be run. If not then I'm not sure how
> should I handle --iova-mode=pa + --no-huge in general. Any
> suggestions?

Thanks for your analysis and explanation. The respective tests should 
return TEST_SKIPPED if called with an unsupported parameter combination.

According to your analysis this is not a problem specific to the RISC-V 
series but can be resolved separately.

Maybe you could add a note in doc/guides/rel_notes/known_issues.rst.

Best regards

Heinrich

> 
> [1] http://mails.dpdk.org/archives/dev/2021-June/210773.html
> [2] http://mails.dpdk.org/archives/dev/2021-June/211146.html
> [3] https://patches.dpdk.org/project/dpdk/patch/20210604141601.275430-4-kda@semihalf.com/
> 
>>
>> If the eal* tests are run depends on the installed Linux packages. I
>> have used 'apt build-dep dpdk' on Ubuntu Jammy to install prerequisite
>> packages before building DPDK.
>>
>> Best regards
>>
>> Heinrich
>>