From: Stanislaw Kardach <kda@semihalf.com>
To: dev@dpdk.org
Cc: Michal Mazurek <maz@semihalf.com>,
Frank Zhao <Frank.Zhao@starfivetech.com>,
Sam Grove <sam.grove@sifive.com>,
mw@semihalf.com, upstream@semihalf.com,
Stanislaw Kardach <kda@semihalf.com>
Subject: [PATCH 08/11] test/cpuflags: add test for RISC-V cpu flag
Date: Thu, 5 May 2022 19:30:00 +0200 [thread overview]
Message-ID: <20220505173003.3242618-9-kda@semihalf.com> (raw)
In-Reply-To: <20220505173003.3242618-1-kda@semihalf.com>
From: Michal Mazurek <maz@semihalf.com>
Add checks for all flag values defined in the RISC-V misa CSR register.
Signed-off-by: Michal Mazurek <maz@semihalf.com>
Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
---
app/test/test_cpuflags.c | 81 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 81 insertions(+)
diff --git a/app/test/test_cpuflags.c b/app/test/test_cpuflags.c
index 40f6ac7fca..98a99c2c7d 100644
--- a/app/test/test_cpuflags.c
+++ b/app/test/test_cpuflags.c
@@ -200,6 +200,87 @@ test_cpuflags(void)
CHECK_FOR_FLAG(RTE_CPUFLAG_INVTSC);
#endif
+#if defined(RTE_ARCH_RISCV)
+
+ printf("Check for RISCV_ISA_A:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_A);
+
+ printf("Check for RISCV_ISA_B:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_B);
+
+ printf("Check for RISCV_ISA_C:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_C);
+
+ printf("Check for RISCV_ISA_D:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_D);
+
+ printf("Check for RISCV_ISA_E:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_E);
+
+ printf("Check for RISCV_ISA_F:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_F);
+
+ printf("Check for RISCV_ISA_G:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_G);
+
+ printf("Check for RISCV_ISA_H:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_H);
+
+ printf("Check for RISCV_ISA_I:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_I);
+
+ printf("Check for RISCV_ISA_J:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_J);
+
+ printf("Check for RISCV_ISA_K:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_K);
+
+ printf("Check for RISCV_ISA_L:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_L);
+
+ printf("Check for RISCV_ISA_M:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_M);
+
+ printf("Check for RISCV_ISA_N:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_N);
+
+ printf("Check for RISCV_ISA_O:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_O);
+
+ printf("Check for RISCV_ISA_P:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_P);
+
+ printf("Check for RISCV_ISA_Q:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Q);
+
+ printf("Check for RISCV_ISA_R:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_R);
+
+ printf("Check for RISCV_ISA_S:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_S);
+
+ printf("Check for RISCV_ISA_T:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_T);
+
+ printf("Check for RISCV_ISA_U:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_U);
+
+ printf("Check for RISCV_ISA_V:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_V);
+
+ printf("Check for RISCV_ISA_W:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_W);
+
+ printf("Check for RISCV_ISA_X:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_X);
+
+ printf("Check for RISCV_ISA_Y:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Y);
+
+ printf("Check for RISCV_ISA_Z:\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Z);
+#endif
+
/*
* Check if invalid data is handled properly
*/
--
2.30.2
next prev parent reply other threads:[~2022-05-05 17:31 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-05 17:29 [PATCH 00/11] Introduce support for RISC-V architecture Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 01/11] lpm: add a scalar version of lookupx4 function Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 02/11] examples/l3fwd: fix scalar LPM compilation Stanislaw Kardach
2022-05-05 17:39 ` Stephen Hemminger
2022-05-05 17:49 ` Stanisław Kardach
2022-05-05 18:09 ` Stephen Hemminger
2022-05-05 17:29 ` [PATCH 03/11] eal: add initial support for RISC-V architecture Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 04/11] net/ixgbe: enable vector stubs for RISC-V Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 05/11] net/memif: set memfd syscall ID on RISC-V Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 06/11] net/tap: set BPF syscall ID for RISC-V Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 07/11] examples/l3fwd: enable RISC-V operation Stanislaw Kardach
2022-05-05 17:30 ` Stanislaw Kardach [this message]
2022-05-05 17:30 ` [PATCH 09/11] test/ring: disable problematic tests for RISC-V Stanislaw Kardach
2022-05-05 17:35 ` Stephen Hemminger
2022-05-05 17:43 ` Stanisław Kardach
2022-05-05 18:06 ` Stephen Hemminger
2022-05-10 23:28 ` Honnappa Nagarahalli
2022-05-11 10:07 ` Stanisław Kardach
2022-05-05 17:30 ` [PATCH 10/11] devtools: add RISC-V to test-meson-builds.sh Stanislaw Kardach
2022-05-05 17:30 ` [PATCH 11/11] test/hash: report non HTM numbers for single r/w Stanislaw Kardach
2022-05-06 9:13 ` [PATCH 00/11] Introduce support for RISC-V architecture David Marchand
2022-05-09 12:24 ` Stanisław Kardach
2022-05-09 12:30 ` Thomas Monjalon
2022-05-11 8:09 ` Morten Brørup
2022-05-11 10:28 ` Stanisław Kardach
2022-05-11 11:06 ` Thomas Monjalon
2022-05-09 14:30 ` David Marchand
2022-05-10 11:21 ` Stanisław Kardach
2022-05-10 12:31 ` Thomas Monjalon
2022-05-10 14:00 ` Stanisław Kardach
2022-05-10 14:23 ` Thomas Monjalon
2022-05-10 15:07 ` [PATCH v2 0/8] " Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 1/8] eal: add initial " Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 2/8] net/ixgbe: enable vector stubs for RISC-V Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 3/8] net/memif: set memfd syscall ID on RISC-V Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 4/8] net/tap: set BPF syscall ID for RISC-V Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 5/8] examples/l3fwd: enable RISC-V operation Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 6/8] test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 7/8] devtools: add RISC-V to test-meson-builds.sh Stanislaw Kardach
2022-05-10 15:35 ` Stanisław Kardach
2022-05-10 15:07 ` [PATCH v2 8/8] ci: add RISCV64 cross compilation job Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 0/8] Introduce support for RISC-V architecture Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 1/8] eal: add initial " Stanislaw Kardach
2022-05-13 6:50 ` Heinrich Schuchardt
2022-05-13 8:42 ` Stanisław Kardach
2022-05-13 10:51 ` Heinrich Schuchardt
2022-05-13 11:47 ` Stanisław Kardach
2022-05-13 15:37 ` Stephen Hemminger
2022-05-16 8:00 ` Stanisław Kardach
2022-05-10 15:48 ` [PATCH v3 2/8] net/ixgbe: enable vector stubs for RISC-V Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 3/8] net/memif: set memfd syscall ID on RISC-V Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 4/8] net/tap: set BPF syscall ID for RISC-V Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 5/8] examples/l3fwd: enable RISC-V operation Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 6/8] test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 7/8] devtools: add RISC-V to test-meson-builds.sh Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 8/8] ci: add RISCV64 cross compilation job Stanislaw Kardach
2022-05-12 15:47 ` Aaron Conole
2022-05-12 16:07 ` Stanisław Kardach
2022-05-13 14:33 ` Aaron Conole
2022-05-12 8:04 ` [PATCH 00/11] Introduce support for RISC-V architecture Heinrich Schuchardt
2022-05-12 8:35 ` Stanisław Kardach
2022-05-12 9:46 ` Heinrich Schuchardt
2022-05-12 13:56 ` Stanisław Kardach
2022-05-12 21:06 ` Heinrich Schuchardt
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220505173003.3242618-9-kda@semihalf.com \
--to=kda@semihalf.com \
--cc=Frank.Zhao@starfivetech.com \
--cc=dev@dpdk.org \
--cc=maz@semihalf.com \
--cc=mw@semihalf.com \
--cc=sam.grove@sifive.com \
--cc=upstream@semihalf.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).