From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7C255A050A; Sat, 7 May 2022 11:40:16 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 201CF4068A; Sat, 7 May 2022 11:40:16 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id DB7BE40395 for ; Sat, 7 May 2022 11:40:14 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2479Q3Tr006411; Sat, 7 May 2022 02:40:08 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=vnLadWbBEShr5iX6ZVTGN/hiUVSnpcJ7oPM/x+pUyHk=; b=hNaWzSJs6aiPoVqvvz+a8BgeQZ2Pbd/r2eh2fl2hVGLTzGX4EYxeet12OQfKl3GpedRN Fv1ShVipvh9WJdFdyfgokjAU21zxe/cjJJxQJvXTkpawts93Bmg7HPzmobTW6aZxQ8Hn tS+ayiD+9hFG+QYV6POM8Kf6pNp+5iqCJmvVhacPDP0x21E7UE1Al0J3dGSzhFOmt7M4 +npD1uuklvzEEU6UQ6XXAKEDu85NwcNsqUgbb1okOLg1EyJxwv+7TEIU/T0dUtXXo2QN t6y4C/ogOtSehHzipAY2xCjrqZbAXH+GwEB4im2BrueNjUbYOphN2LQvt6URrnBt/z5m 6A== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3fwp4pr0n1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sat, 07 May 2022 02:40:08 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sat, 7 May 2022 02:40:07 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Sat, 7 May 2022 02:40:07 -0700 Received: from localhost.localdomain (unknown [10.28.48.107]) by maili.marvell.com (Postfix) with ESMTP id 4FE103F7079; Sat, 7 May 2022 02:40:05 -0700 (PDT) From: Rahul Bhansali To: , Jan Viktorin , Ruifeng Wang , Bruce Richardson CC: , Rahul Bhansali Subject: [PATCH v2 1/2] config/arm: add SVE ACLE control flag Date: Sat, 7 May 2022 15:09:42 +0530 Message-ID: <20220507093943.2065586-1-rbhansali@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505142744.1423344-1-rbhansali@marvell.com> References: <20220505142744.1423344-1-rbhansali@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: VbKjk3wCKLWt4DI1K7l6GjaHKJ6A1vtf X-Proofpoint-GUID: VbKjk3wCKLWt4DI1K7l6GjaHKJ6A1vtf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-07_02,2022-05-06_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This add the control flag for SVE ACLE to enable or disable RTE_HAS_SVE_ACLE macro in the build. Signed-off-by: Rahul Bhansali --- Changes in v2: - Renamed the flag to sve_acle from sve - Added double-indent. config/arm/meson.build | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 8aead74086..2e12b541ef 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -603,7 +603,8 @@ if (cc.get_define('__ARM_NEON', args: machine_args) != '' or compile_time_cpuflags += ['RTE_CPUFLAG_NEON'] endif -if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' +if (cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' and + soc_config.get('sve_acle', true)) compile_time_cpuflags += ['RTE_CPUFLAG_SVE'] if (cc.check_header('arm_sve.h')) dpdk_conf.set('RTE_HAS_SVE_ACLE', 1) -- 2.25.1