From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 53909A00C2; Mon, 9 May 2022 11:46:31 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EF549407FF; Mon, 9 May 2022 11:46:30 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 5535F4068F for ; Mon, 9 May 2022 11:46:29 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 248MKQiM022413; Mon, 9 May 2022 02:46:24 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=dszsHRBKp5p7guTHIQ8nwPmJOseFcncrwC1FhT0vE/c=; b=izVRhmPa1kNujKFHg54U+DoO1AfEXYMowYd17S+hqjrQ7qQEE83rQMNprp6Ki7vQEDuL u7cV4MOaU8tPQiNlvENpYq8mZSUo+Dtv2Iwz5TJfq65CbI4tE6m0B+dMjg6zOG4LxXfa N1Xq4wzlHi+O12/McEOkbEgoko1pTWD9WooC7jnlUDMff3UXjQLiGkL/xTaL6FrFjQEv I7uX98JCaIOhqpwMDWpKi0yz1itLchEGdyETd7J7Ys+7w/7POTWOvLj6es9V/tnClw8z H/RH3i/BlZCr0/s6YcmHVhy0HvGUTjEI6q0UIjRFGRV7m25smknwsW8/yiMqDQJ+qyn/ gg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3fwp4pwt65-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 09 May 2022 02:46:24 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 9 May 2022 02:46:22 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 9 May 2022 02:46:22 -0700 Received: from localhost.localdomain (unknown [10.28.48.107]) by maili.marvell.com (Postfix) with ESMTP id B8A4B5B692F; Mon, 9 May 2022 02:46:20 -0700 (PDT) From: Rahul Bhansali To: , Ruifeng Wang , Jan Viktorin , Bruce Richardson CC: , Rahul Bhansali Subject: [PATCH v3 1/2] config/arm: add SVE ACLE control flag Date: Mon, 9 May 2022 15:16:15 +0530 Message-ID: <20220509094615.2397452-1-rbhansali@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220507093943.2065586-1-rbhansali@marvell.com> References: <20220507093943.2065586-1-rbhansali@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: IVi_nvmrtJ1kS8yLtfdwC2yIRJ9ZxyWM X-Proofpoint-GUID: IVi_nvmrtJ1kS8yLtfdwC2yIRJ9ZxyWM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-09_03,2022-05-09_01,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This add the control flag for SVE ACLE to enable or disable RTE_HAS_SVE_ACLE macro in the build. Signed-off-by: Rahul Bhansali --- Changes in v3: - Moved sve_acle condition to be consider for RTE_HAS_SVE_ACLE flag only. Changes in v2: - Renamed the flag to sve_acle from sve - Added double-indent. config/arm/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 8aead74086..6f8961eac8 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -605,7 +605,7 @@ endif if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' compile_time_cpuflags += ['RTE_CPUFLAG_SVE'] - if (cc.check_header('arm_sve.h')) + if (cc.check_header('arm_sve.h') and soc_config.get('sve_acle', true)) dpdk_conf.set('RTE_HAS_SVE_ACLE', 1) endif endif -- 2.25.1