From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D3A9DA0093; Tue, 10 May 2022 17:08:16 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C353A4283E; Tue, 10 May 2022 17:08:16 +0200 (CEST) Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) by mails.dpdk.org (Postfix) with ESMTP id 30456410EE for ; Tue, 10 May 2022 17:08:15 +0200 (CEST) Received: by mail-lf1-f44.google.com with SMTP id j4so29864658lfh.8 for ; Tue, 10 May 2022 08:08:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nwLeAkiBtwlPltHgeHbDFtas1bIep5PQ/BzZhSMkNXA=; b=8PwfIoICruEhp0hR/x2wGHzZKQislvCyD+SiX5elz0Mf9CbL3+iOEH0URRoGvgS/Si FVv33EOsZpEO6UQnI67ocok1f84R+3WjdzapBLR/b2gSPucK55r2hC7cExcjm6VSXw5E bJi9XrZpB6QZjeLxpt3DfO9lYvVLqy3NWHLYu9FQCL3FNGyIDp27TdaTX7E3LteK8v74 bm1Y7SPgH31s24Yd9AR142LNIOSHWfPbOSpwbTeXl3RK6xi+IBzmgWevfa5eKNYhjHdg jIsXLPXtGFOnnE1xcKTxbwR1k4ceVgTW5FITlocMGJFVRq8wKAQXLiWc+PBqNm5Becyv C6BQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nwLeAkiBtwlPltHgeHbDFtas1bIep5PQ/BzZhSMkNXA=; b=iSajv/CwKeXQjbrTQFhr/eM4yAFkYfavc7QxOJTbLpNJ52zgzJUTnNRIx8vYfQb1IC d7zwi2Njt2sTefxyjqGHM7oms09yBf59/wzSPsqjU5nGeRldIa/+7h2jt6YFOaYzFx9i GwYJGWSNhpapYlvY1/elLDR0jym0ci5CqNdaGXHhRWmP7foE1YfvNtvg2OUSd398CQS6 aAmH7tDDvx30WG1b/VWlpWtNI2gjhDxoTMK23CkHzxk9PM2BvcYZ2Ky6UosWzt1hLnIz eMANs/tyAqsz+yteHQ18Z8pa2yDt9I1o49gG5pQPtwOrOlkRLSZm6IGsvJKqUTX67imC ls1g== X-Gm-Message-State: AOAM532HHDNeYd3O490ATnUNqzLBvrFRTsgA8r6//svvTq9b6tVgu7LB b+/11FYIFsS2NeBXVWX9EhBin0AbDGvL4Q== X-Google-Smtp-Source: ABdhPJyS3UfNPB040Iq0GGz/9xn+lk49pl8bsWSk9AST3bctKpFu7pegk0CSl3Puorn5/aCe5+CxBQ== X-Received: by 2002:a05:6512:3b0f:b0:473:9dbb:a72c with SMTP id f15-20020a0565123b0f00b004739dbba72cmr16761042lfv.399.1652195294643; Tue, 10 May 2022 08:08:14 -0700 (PDT) Received: from toster.office.semihalf.net ([83.142.187.84]) by smtp.gmail.com with ESMTPSA id z4-20020a19e204000000b0047255d2117esm2311895lfg.173.2022.05.10.08.08.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 May 2022 08:08:14 -0700 (PDT) From: Stanislaw Kardach To: dev@dpdk.org Cc: Stanislaw Kardach , Frank Zhao , Sam Grove , mw@semihalf.com, upstream@semihalf.com Subject: [PATCH v2 0/8] Introduce support for RISC-V architecture Date: Tue, 10 May 2022 17:07:51 +0200 Message-Id: <20220510150759.525434-1-kda@semihalf.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220505173003.3242618-1-kda@semihalf.com> References: <20220505173003.3242618-1-kda@semihalf.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patchset adds support for building and running DPDK on 64bit RISC-V architecture. The initial support targets rv64gc (rv64imafdc) ISA and was tested on SiFive Unmatched development board with the Freedom U740 SoC running Linux (freedom-u-sdk based kernel). I have tested this codebase using DPDK unit and perf tests as well as test-pmd, l2fwd and l3fwd examples. The NIC attached to the DUT was Intel X520-DA2 which uses ixgbe PMD. On the UIO side, since U740 does not have an IOMMU, I've used igb_uio, uio_pci_generic and vfio-pci noiommu drivers. Functional verification done using meson tests. fast-tests suite passing with the default config. PMD verification done using a Intel x520-DA2 NIC (ixgbe) and the test-pmd application. Packet transfer checked using all UIO drivers available for non-IOMMU platforms: uio_pci_generic, vfio-pci noiommu and igb_uio. The i40e PMD driver is disabled on RISC-V as the rv64gc ISA has no vector operations. RISCV support is currently limited to Linux as the time measurement frequency discovery is tied to reading a device-tree node via procfs. Clang compilation currently not supported due to issues with missing relocation relaxation. Commit 1 introduces EAL and build system support for RISC-V architecture as well as documentation updates. Commits 2-5 add missing defines and stubs to enable RISC-V operation in non-EAL parts. Commit 6 adds RISC-V specific cpuflags test. Commits 7-8 add RISC-V build testing to test-meson-builds.sh and github CI. I appreciate Your comments and feedback. Best Regards, Stanislaw Kardach v2: - Separate bug-fixes into separate series. - Prevent RV64_CSRR leak to API users. - Limit test-meson-builds.sh testing to a generic rv64gc configuration. - Clean-up release notes and fix style issues. Michal Mazurek (2): eal: add initial support for RISC-V architecture test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach (6): net/ixgbe: enable vector stubs for RISC-V net/memif: set memfd syscall ID on RISC-V net/tap: set BPF syscall ID for RISC-V examples/l3fwd: enable RISC-V operation devtools: add RISC-V to test-meson-builds.sh ci: add RISCV64 cross compilation job --- NOTE: I have added maintainers for each commit based on MAINTAINERS file. However some modules (l3fwd, net/tap and cpuflags unit tests) do not have any maintainers assigned, hence I've targeted dev@dpdk.org mailing list as if it was a commit adding new files. .ci/linux-build.sh | 4 + .github/workflows/build.yml | 11 +- MAINTAINERS | 6 + app/test/test_cpuflags.c | 81 ++++++++++ app/test/test_xmmt_ops.h | 16 ++ config/meson.build | 2 + config/riscv/meson.build | 143 ++++++++++++++++++ config/riscv/riscv64_linux_gcc | 17 +++ config/riscv/riscv64_sifive_u740_linux_gcc | 19 +++ devtools/test-meson-builds.sh | 6 + doc/guides/contributing/design.rst | 2 +- .../linux_gsg/cross_build_dpdk_for_riscv.rst | 125 +++++++++++++++ doc/guides/linux_gsg/index.rst | 1 + doc/guides/nics/features.rst | 5 + doc/guides/nics/features/default.ini | 1 + doc/guides/nics/features/ixgbe.ini | 1 + doc/guides/rel_notes/release_22_07.rst | 8 + drivers/net/i40e/meson.build | 6 + drivers/net/ixgbe/ixgbe_rxtx.c | 4 +- drivers/net/memif/rte_eth_memif.h | 2 + drivers/net/tap/tap_bpf.h | 2 + examples/l3fwd/l3fwd_em.c | 8 + examples/l3fwd/l3fwd_fib.c | 2 + lib/eal/riscv/include/meson.build | 23 +++ lib/eal/riscv/include/rte_atomic.h | 52 +++++++ lib/eal/riscv/include/rte_byteorder.h | 44 ++++++ lib/eal/riscv/include/rte_cpuflags.h | 55 +++++++ lib/eal/riscv/include/rte_cycles.h | 105 +++++++++++++ lib/eal/riscv/include/rte_io.h | 21 +++ lib/eal/riscv/include/rte_mcslock.h | 18 +++ lib/eal/riscv/include/rte_memcpy.h | 63 ++++++++ lib/eal/riscv/include/rte_pause.h | 31 ++++ lib/eal/riscv/include/rte_pflock.h | 17 +++ lib/eal/riscv/include/rte_power_intrinsics.h | 22 +++ lib/eal/riscv/include/rte_prefetch.h | 50 ++++++ lib/eal/riscv/include/rte_rwlock.h | 44 ++++++ lib/eal/riscv/include/rte_spinlock.h | 67 ++++++++ lib/eal/riscv/include/rte_ticketlock.h | 21 +++ lib/eal/riscv/include/rte_vect.h | 55 +++++++ lib/eal/riscv/meson.build | 11 ++ lib/eal/riscv/rte_cpuflags.c | 122 +++++++++++++++ lib/eal/riscv/rte_cycles.c | 77 ++++++++++ lib/eal/riscv/rte_hypervisor.c | 13 ++ lib/eal/riscv/rte_power_intrinsics.c | 56 +++++++ meson.build | 2 + 45 files changed, 1437 insertions(+), 4 deletions(-) create mode 100644 config/riscv/meson.build create mode 100644 config/riscv/riscv64_linux_gcc create mode 100644 config/riscv/riscv64_sifive_u740_linux_gcc create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst create mode 100644 lib/eal/riscv/include/meson.build create mode 100644 lib/eal/riscv/include/rte_atomic.h create mode 100644 lib/eal/riscv/include/rte_byteorder.h create mode 100644 lib/eal/riscv/include/rte_cpuflags.h create mode 100644 lib/eal/riscv/include/rte_cycles.h create mode 100644 lib/eal/riscv/include/rte_io.h create mode 100644 lib/eal/riscv/include/rte_mcslock.h create mode 100644 lib/eal/riscv/include/rte_memcpy.h create mode 100644 lib/eal/riscv/include/rte_pause.h create mode 100644 lib/eal/riscv/include/rte_pflock.h create mode 100644 lib/eal/riscv/include/rte_power_intrinsics.h create mode 100644 lib/eal/riscv/include/rte_prefetch.h create mode 100644 lib/eal/riscv/include/rte_rwlock.h create mode 100644 lib/eal/riscv/include/rte_spinlock.h create mode 100644 lib/eal/riscv/include/rte_ticketlock.h create mode 100644 lib/eal/riscv/include/rte_vect.h create mode 100644 lib/eal/riscv/meson.build create mode 100644 lib/eal/riscv/rte_cpuflags.c create mode 100644 lib/eal/riscv/rte_cycles.c create mode 100644 lib/eal/riscv/rte_hypervisor.c create mode 100644 lib/eal/riscv/rte_power_intrinsics.c -- 2.30.2