From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 54DD3A0093; Tue, 10 May 2022 17:49:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 01607410EE; Tue, 10 May 2022 17:49:01 +0200 (CEST) Received: from mail-lj1-f170.google.com (mail-lj1-f170.google.com [209.85.208.170]) by mails.dpdk.org (Postfix) with ESMTP id F1CD0406B4 for ; Tue, 10 May 2022 17:48:59 +0200 (CEST) Received: by mail-lj1-f170.google.com with SMTP id 4so21347038ljw.11 for ; Tue, 10 May 2022 08:48:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vSe9kAZZqpoYgkdtTA1T50x6X6oX8bWwjqOKnE79jdE=; b=RXF2ZtLmDwtDKgd6Y4OkzE1wUUhq7qHMhTCR2MSsWLlZP+Xf4f0cts29ECN7/u2PXG 4BsJXnUswYbNuXN4RnpHWlu4E0D9gGKphD4sXrh5cw20Ym2q40qoaJev/fLfNvCJvJws rBCptjxTR3g2i1wDDUG8rq1eVo1yg0gTD1rDW1Gl0vbJVjkvk/mZ2MFFHXg5mduJwqfg zHeZaP8EZQ79ytAKKoZ3LSokEU1p8DcNiH19ovaUAF7v4ngvqLe/NzigwXov41S5DR37 yxbDvqOVRI6GXRS4gU8sHemhtN30BhtmfTY9VDgULXX8WzRUjLfjSvjVqT95LFdsjcYg Zy1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vSe9kAZZqpoYgkdtTA1T50x6X6oX8bWwjqOKnE79jdE=; b=hWorLQwP01omsMD9QUyNGt9kgHPk+w4ixsarXeb/iCyGlVhKLBszt9hozJpmsfzvXO r+AwsP8Jy9D0w7rLERG6AYuL/jyAu6J+Sa987jT7C2PM1fJvdwxowMwhA7WcDw/37/1g XTx3hTPad/mrRlSgLMJqe2meMaxz6LZBUy7fhxtokhJfpc/3ak1uRwGnQcVU6dJZcUC9 DQ57Rxe77D2a7uCXIcIxjLKN2BrzhfvgeiZHuh39R9raFW+Z55HAxIrmRBmL9itwzA8J YzeWhy8GI9a44kyNkXXXf1BItVGRlltm3ex3ELa3TpfyOuj/y4EPoYxeOOUXjXTRkRKV EJqA== X-Gm-Message-State: AOAM530bK1NshS4rh8icYcIVfHyD3PFwvR//6vnD0TCgzozQfcDz4INY k/VWkDBLpg1Li62abNyy5UFjCevXzc30dg== X-Google-Smtp-Source: ABdhPJzTFkU8On4jSGzKVRx6e5ryhB/QSgkmyzk7Rr9dlCnm0uxoX1CS9LB3Fe4dpWC/acGN8DNSDg== X-Received: by 2002:a2e:8902:0:b0:24f:1446:3101 with SMTP id d2-20020a2e8902000000b0024f14463101mr13988801lji.266.1652197739392; Tue, 10 May 2022 08:48:59 -0700 (PDT) Received: from toster.office.semihalf.net ([83.142.187.84]) by smtp.gmail.com with ESMTPSA id i13-20020a2e540d000000b0024f3d1daeedsm2175051ljb.117.2022.05.10.08.48.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 May 2022 08:48:58 -0700 (PDT) From: Stanislaw Kardach To: dev@dpdk.org Cc: Stanislaw Kardach , Frank Zhao , Sam Grove , mw@semihalf.com, upstream@semihalf.com Subject: [PATCH v3 0/8] Introduce support for RISC-V architecture Date: Tue, 10 May 2022 17:48:41 +0200 Message-Id: <20220510154849.530872-1-kda@semihalf.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220510150759.525434-1-kda@semihalf.com> References: <20220510150759.525434-1-kda@semihalf.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patchset adds support for building and running DPDK on 64bit RISC-V architecture. The initial support targets rv64gc (rv64imafdc) ISA and was tested on SiFive Unmatched development board with the Freedom U740 SoC running Linux (freedom-u-sdk based kernel). I have tested this codebase using DPDK unit and perf tests as well as test-pmd, l2fwd and l3fwd examples. The NIC attached to the DUT was Intel X520-DA2 which uses ixgbe PMD. On the UIO side, since U740 does not have an IOMMU, I've used igb_uio, uio_pci_generic and vfio-pci noiommu drivers. Functional verification done using meson tests. fast-tests suite passing with the default config. PMD verification done using a Intel x520-DA2 NIC (ixgbe) and the test-pmd application. Packet transfer checked using all UIO drivers available for non-IOMMU platforms: uio_pci_generic, vfio-pci noiommu and igb_uio. The i40e PMD driver is disabled on RISC-V as the rv64gc ISA has no vector operations. RISCV support is currently limited to Linux as the time measurement frequency discovery is tied to reading a device-tree node via procfs. Clang compilation currently not supported due to issues with missing relocation relaxation. Commit 1 introduces EAL and build system support for RISC-V architecture as well as documentation updates. Commits 2-5 add missing defines and stubs to enable RISC-V operation in non-EAL parts. Commit 6 adds RISC-V specific cpuflags test. Commits 7-8 add RISC-V build testing to test-meson-builds.sh and github CI. I appreciate Your comments and feedback. Best Regards, Stanislaw Kardach v3: - Limit test-meson-builds.sh testing to a generic rv64gc configuration. Previous version was missing this change by mistake. v2: - Separate bug-fixes into separate series. - Prevent RV64_CSRR leak to API users. - Limit test-meson-builds.sh testing to a generic rv64gc configuration. - Clean-up release notes and fix style issues. Michal Mazurek (2): eal: add initial support for RISC-V architecture test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach (6): net/ixgbe: enable vector stubs for RISC-V net/memif: set memfd syscall ID on RISC-V net/tap: set BPF syscall ID for RISC-V examples/l3fwd: enable RISC-V operation devtools: add RISC-V to test-meson-builds.sh ci: add RISCV64 cross compilation job --- NOTE: I have added maintainers for each commit based on MAINTAINERS file. However some modules (l3fwd, net/tap and cpuflags unit tests) do not have any maintainers assigned, hence I've targeted dev@dpdk.org mailing list as if it was a commit adding new files. .ci/linux-build.sh | 4 + .github/workflows/build.yml | 11 +- MAINTAINERS | 6 + app/test/test_cpuflags.c | 81 ++++++++++ app/test/test_xmmt_ops.h | 16 ++ config/meson.build | 2 + config/riscv/meson.build | 143 ++++++++++++++++++ config/riscv/riscv64_linux_gcc | 17 +++ config/riscv/riscv64_sifive_u740_linux_gcc | 19 +++ devtools/test-meson-builds.sh | 4 + doc/guides/contributing/design.rst | 2 +- .../linux_gsg/cross_build_dpdk_for_riscv.rst | 125 +++++++++++++++ doc/guides/linux_gsg/index.rst | 1 + doc/guides/nics/features.rst | 5 + doc/guides/nics/features/default.ini | 1 + doc/guides/nics/features/ixgbe.ini | 1 + doc/guides/rel_notes/release_22_07.rst | 8 + drivers/net/i40e/meson.build | 6 + drivers/net/ixgbe/ixgbe_rxtx.c | 4 +- drivers/net/memif/rte_eth_memif.h | 2 + drivers/net/tap/tap_bpf.h | 2 + examples/l3fwd/l3fwd_em.c | 8 + examples/l3fwd/l3fwd_fib.c | 2 + lib/eal/riscv/include/meson.build | 23 +++ lib/eal/riscv/include/rte_atomic.h | 52 +++++++ lib/eal/riscv/include/rte_byteorder.h | 44 ++++++ lib/eal/riscv/include/rte_cpuflags.h | 55 +++++++ lib/eal/riscv/include/rte_cycles.h | 105 +++++++++++++ lib/eal/riscv/include/rte_io.h | 21 +++ lib/eal/riscv/include/rte_mcslock.h | 18 +++ lib/eal/riscv/include/rte_memcpy.h | 63 ++++++++ lib/eal/riscv/include/rte_pause.h | 31 ++++ lib/eal/riscv/include/rte_pflock.h | 17 +++ lib/eal/riscv/include/rte_power_intrinsics.h | 22 +++ lib/eal/riscv/include/rte_prefetch.h | 50 ++++++ lib/eal/riscv/include/rte_rwlock.h | 44 ++++++ lib/eal/riscv/include/rte_spinlock.h | 67 ++++++++ lib/eal/riscv/include/rte_ticketlock.h | 21 +++ lib/eal/riscv/include/rte_vect.h | 55 +++++++ lib/eal/riscv/meson.build | 11 ++ lib/eal/riscv/rte_cpuflags.c | 122 +++++++++++++++ lib/eal/riscv/rte_cycles.c | 77 ++++++++++ lib/eal/riscv/rte_hypervisor.c | 13 ++ lib/eal/riscv/rte_power_intrinsics.c | 56 +++++++ meson.build | 2 + 45 files changed, 1435 insertions(+), 4 deletions(-) create mode 100644 config/riscv/meson.build create mode 100644 config/riscv/riscv64_linux_gcc create mode 100644 config/riscv/riscv64_sifive_u740_linux_gcc create mode 100644 doc/guides/linux_gsg/cross_build_dpdk_for_riscv.rst create mode 100644 lib/eal/riscv/include/meson.build create mode 100644 lib/eal/riscv/include/rte_atomic.h create mode 100644 lib/eal/riscv/include/rte_byteorder.h create mode 100644 lib/eal/riscv/include/rte_cpuflags.h create mode 100644 lib/eal/riscv/include/rte_cycles.h create mode 100644 lib/eal/riscv/include/rte_io.h create mode 100644 lib/eal/riscv/include/rte_mcslock.h create mode 100644 lib/eal/riscv/include/rte_memcpy.h create mode 100644 lib/eal/riscv/include/rte_pause.h create mode 100644 lib/eal/riscv/include/rte_pflock.h create mode 100644 lib/eal/riscv/include/rte_power_intrinsics.h create mode 100644 lib/eal/riscv/include/rte_prefetch.h create mode 100644 lib/eal/riscv/include/rte_rwlock.h create mode 100644 lib/eal/riscv/include/rte_spinlock.h create mode 100644 lib/eal/riscv/include/rte_ticketlock.h create mode 100644 lib/eal/riscv/include/rte_vect.h create mode 100644 lib/eal/riscv/meson.build create mode 100644 lib/eal/riscv/rte_cpuflags.c create mode 100644 lib/eal/riscv/rte_cycles.c create mode 100644 lib/eal/riscv/rte_hypervisor.c create mode 100644 lib/eal/riscv/rte_power_intrinsics.c -- 2.30.2