From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AF5A9A0093; Tue, 10 May 2022 17:49:15 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 354A14113D; Tue, 10 May 2022 17:49:04 +0200 (CEST) Received: from mail-lf1-f51.google.com (mail-lf1-f51.google.com [209.85.167.51]) by mails.dpdk.org (Postfix) with ESMTP id A4A174282B for ; Tue, 10 May 2022 17:49:02 +0200 (CEST) Received: by mail-lf1-f51.google.com with SMTP id b18so30057203lfv.9 for ; Tue, 10 May 2022 08:49:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SiJJicmSCFrFlrS6bKskGVGKimGsuO7DGMjRiELgor4=; b=NLnAV02e1bfYWfP/TsrsUqydHeOKks2iVd/o7Tvtwbn8LoV1nrOLKqIWA+t3VHtVNw igWQoI07+wobSr/RahVbiUUHY/mcBDnEIOwh+NvzSy2TsPqfTdkhKsvgFoBg2LWuksnA Ejg63La9c0Mi5JVcDulxmo/xOzppFiG/kZmLgUUcDPjrdsqXfnlMzXWq3QyVW+Hyll8Y Kj4yzZCMirf4+f8P+STwUH4XCFySv9CmkKCZqDsm0aN5IgZFnRDHmwMVJxVr3jlejb/Y jqVWm8OO7XVO+fCLsJh5SW136LQvkgVuLLJCMWQxR/TUMV/C3sah/zxMQSEMk/O8oKiL Dc5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SiJJicmSCFrFlrS6bKskGVGKimGsuO7DGMjRiELgor4=; b=s+Hodcao+heAe3x8NDAh6fYuOn96WQmO23/X5NqZF7t8hLAA94FfomDV1aLLHQ/xfA RTuTPL25CJMcZfP7xZgoznv4EVC1UyBUUipqA4cAwK1XHp4a4VqPxeqscQeKPBWNN4mK ERntBs02f5IgZyAGUJumEZLMN6Md4je3wRcMRtFUQDfO57a1kj37Tu/H/DrLZ98buV/Y 4TO6STDJLK+J0msnQP/46/y8eaMi/b1NmnQlAEay86L5YMooT8oCvQ3Yhv7s87OPGPUN KrCnXMW/+S74u+oOSUhdvOlrUggZVcTllKhz/WWvGyK1FaDKbv9QYBvZ1IWBm6t8fnU7 4lqw== X-Gm-Message-State: AOAM530j5zpTp0nSodscveVr9jq5F70GesfNgcbNcpkpkzom8dN5VnGL f5Sm29N7XpR4UHxdLxURHG1iLw== X-Google-Smtp-Source: ABdhPJwRr7wcQCJZGiZ7zd3czDvA8P8ZF2BOtyTcI6Ui1yUvYmy7/WEJ12WWmL6UfsxSXwA6o9kpkA== X-Received: by 2002:a05:6512:e84:b0:474:12f3:cb53 with SMTP id bi4-20020a0565120e8400b0047412f3cb53mr12300814lfb.254.1652197742294; Tue, 10 May 2022 08:49:02 -0700 (PDT) Received: from toster.office.semihalf.net ([83.142.187.84]) by smtp.gmail.com with ESMTPSA id i13-20020a2e540d000000b0024f3d1daeedsm2175051ljb.117.2022.05.10.08.49.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 May 2022 08:49:01 -0700 (PDT) From: Stanislaw Kardach To: Haiyue Wang Cc: Stanislaw Kardach , dev@dpdk.org, Frank Zhao , Sam Grove , mw@semihalf.com, upstream@semihalf.com Subject: [PATCH v3 2/8] net/ixgbe: enable vector stubs for RISC-V Date: Tue, 10 May 2022 17:48:43 +0200 Message-Id: <20220510154849.530872-3-kda@semihalf.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220510154849.530872-1-kda@semihalf.com> References: <20220510150759.525434-1-kda@semihalf.com> <20220510154849.530872-1-kda@semihalf.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Re-use vector processing stubs in ixgbe PMD defined for PPC for RISC-V. This enables ixgbe PMD usage in scalar mode on this architecture. The ixgbe PMD driver was validated with Intel X520-DA2 NIC and the test-pmd application. Packet transfer checked using all UIO drivers available for non-IOMMU platforms: uio_pci_generic, vfio-pci noiommu and igb_uio. Sponsored-by: Frank Zhao Sponsored-by: Sam Grove Signed-off-by: Stanislaw Kardach --- doc/guides/nics/features/ixgbe.ini | 1 + drivers/net/ixgbe/ixgbe_rxtx.c | 4 ++-- drivers/net/ixgbe/meson.build | 6 ------ 3 files changed, 3 insertions(+), 8 deletions(-) diff --git a/doc/guides/nics/features/ixgbe.ini b/doc/guides/nics/features/ixgbe.ini index c5333d1142..b776ca1cf1 100644 --- a/doc/guides/nics/features/ixgbe.ini +++ b/doc/guides/nics/features/ixgbe.ini @@ -54,6 +54,7 @@ Windows = Y ARMv8 = Y x86-32 = Y x86-64 = Y +rv64 = Y [rte_flow items] eth = Y diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c index 9e8ea366a5..009d9b624a 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx.c +++ b/drivers/net/ixgbe/ixgbe_rxtx.c @@ -5957,8 +5957,8 @@ ixgbe_config_rss_filter(struct rte_eth_dev *dev, return 0; } -/* Stubs needed for linkage when RTE_ARCH_PPC_64 is set */ -#if defined(RTE_ARCH_PPC_64) +/* Stubs needed for linkage when RTE_ARCH_PPC_64 or RTE_ARCH_RISCV is set */ +#if defined(RTE_ARCH_PPC_64) || defined(RTE_ARCH_RISCV) int ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev) { diff --git a/drivers/net/ixgbe/meson.build b/drivers/net/ixgbe/meson.build index 88539e97d5..162f8d5f46 100644 --- a/drivers/net/ixgbe/meson.build +++ b/drivers/net/ixgbe/meson.build @@ -1,12 +1,6 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2017 Intel Corporation -if arch_subdir == 'riscv' - build = false - reason = 'riscv arch not supported' - subdir_done() -endif - cflags += ['-DRTE_LIBRTE_IXGBE_BYPASS'] subdir('base') -- 2.30.2