From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 77709A0093; Tue, 10 May 2022 17:49:37 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E01E34284A; Tue, 10 May 2022 17:49:09 +0200 (CEST) Received: from mail-lj1-f182.google.com (mail-lj1-f182.google.com [209.85.208.182]) by mails.dpdk.org (Postfix) with ESMTP id 64AAD42845 for ; Tue, 10 May 2022 17:49:07 +0200 (CEST) Received: by mail-lj1-f182.google.com with SMTP id bx33so10486888ljb.12 for ; Tue, 10 May 2022 08:49:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=il/Ojg6nMnnxJ4v/UzuQOsltnvdlSZEce3Ircx4SClE=; b=UfSyMXba2o57rZm94PsN4f3kzD0iUFcdEj6sw1BWGLRhh1BgMSpD6TPO1J/lD7R2X6 Sm9h4kcVUaoTkVOlWRIWu5hKsha9d6/IlNVIGNUxmQGi23VWVLJvIN1n4FZB9h9w3b6i MLF1eYGMOA575v4yJ7F14ylJXHIfpQAvSmyMoFi+9sqk6ysqCysOMZboJxKinbsED4b2 SB5f0xtNz13l2LtPJorTewiri7B6Qkq07GVb720mXgHH4X/8s3Qntf03zSLAqpMMXqK0 2SMUSuuLThtQbEd53aBeqpVtxURw/rw1CdS+MXj3vZlQlWs6jodFQqMbcXhmZ3Ev1ZHZ rQgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=il/Ojg6nMnnxJ4v/UzuQOsltnvdlSZEce3Ircx4SClE=; b=ZTQL7xojCDUynj6q6RgPXbnA5pZGTLIzWUQQdzOfLb3vZ45CqDVHfDoOA6AYASE/Nj h9rBWk4RRg9QdO1tfN4k0CD+6ExEx58HkkyZ01pm+Vk+TYV9BNEmsJZE2MGCOOTdXJUc 0umVLXh+J0uVZgBL//HR4phRi5+ucCYGwqlNjg3Fil37Nx62iyiICb1ar0FolJQgyq4f buAFX4jR/B6S/BFj0qVFP0nYsiIYWhJPPEOewVl0nlwOU5dJPixnRqaUzp2NRAcZs+hv 4A+BgQz8JDC48iIcMtfUDSHLi1S7UAts4HyGjttmKOhK8jOjtv1gcAIJFRMlUZS8Gkxj VvOg== X-Gm-Message-State: AOAM530sHaHM97Gel46jKX/pnegPkYKWU2sSYm3DBw9bEcB2r25NagRw UwlYxn/pjTrCFqnPcmkQOmTZlr0wKNiRcQ== X-Google-Smtp-Source: ABdhPJw5sgb7sSYvRPdbkARj8En/nPLUKmo5MGLLi/0SgEjsWac1VAYmFPItGuLjinkgnk9XAbKplg== X-Received: by 2002:a05:651c:1a0b:b0:250:5c9e:d7e8 with SMTP id by11-20020a05651c1a0b00b002505c9ed7e8mr14128310ljb.84.1652197746953; Tue, 10 May 2022 08:49:06 -0700 (PDT) Received: from toster.office.semihalf.net ([83.142.187.84]) by smtp.gmail.com with ESMTPSA id i13-20020a2e540d000000b0024f3d1daeedsm2175051ljb.117.2022.05.10.08.49.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 May 2022 08:49:06 -0700 (PDT) From: Stanislaw Kardach To: dev@dpdk.org Cc: Michal Mazurek , Frank Zhao , Sam Grove , mw@semihalf.com, upstream@semihalf.com, Stanislaw Kardach Subject: [PATCH v3 6/8] test/cpuflags: add test for RISC-V cpu flag Date: Tue, 10 May 2022 17:48:47 +0200 Message-Id: <20220510154849.530872-7-kda@semihalf.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220510154849.530872-1-kda@semihalf.com> References: <20220510150759.525434-1-kda@semihalf.com> <20220510154849.530872-1-kda@semihalf.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Michal Mazurek Add checks for all flag values defined in the RISC-V misa CSR register. Sponsored-by: Frank Zhao Sponsored-by: Sam Grove Signed-off-by: Michal Mazurek Signed-off-by: Stanislaw Kardach --- app/test/test_cpuflags.c | 81 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/app/test/test_cpuflags.c b/app/test/test_cpuflags.c index 40f6ac7fca..98a99c2c7d 100644 --- a/app/test/test_cpuflags.c +++ b/app/test/test_cpuflags.c @@ -200,6 +200,87 @@ test_cpuflags(void) CHECK_FOR_FLAG(RTE_CPUFLAG_INVTSC); #endif +#if defined(RTE_ARCH_RISCV) + + printf("Check for RISCV_ISA_A:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_A); + + printf("Check for RISCV_ISA_B:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_B); + + printf("Check for RISCV_ISA_C:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_C); + + printf("Check for RISCV_ISA_D:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_D); + + printf("Check for RISCV_ISA_E:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_E); + + printf("Check for RISCV_ISA_F:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_F); + + printf("Check for RISCV_ISA_G:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_G); + + printf("Check for RISCV_ISA_H:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_H); + + printf("Check for RISCV_ISA_I:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_I); + + printf("Check for RISCV_ISA_J:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_J); + + printf("Check for RISCV_ISA_K:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_K); + + printf("Check for RISCV_ISA_L:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_L); + + printf("Check for RISCV_ISA_M:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_M); + + printf("Check for RISCV_ISA_N:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_N); + + printf("Check for RISCV_ISA_O:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_O); + + printf("Check for RISCV_ISA_P:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_P); + + printf("Check for RISCV_ISA_Q:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Q); + + printf("Check for RISCV_ISA_R:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_R); + + printf("Check for RISCV_ISA_S:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_S); + + printf("Check for RISCV_ISA_T:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_T); + + printf("Check for RISCV_ISA_U:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_U); + + printf("Check for RISCV_ISA_V:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_V); + + printf("Check for RISCV_ISA_W:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_W); + + printf("Check for RISCV_ISA_X:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_X); + + printf("Check for RISCV_ISA_Y:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Y); + + printf("Check for RISCV_ISA_Z:\t"); + CHECK_FOR_FLAG(RTE_CPUFLAG_RISCV_ISA_Z); +#endif + /* * Check if invalid data is handled properly */ -- 2.30.2