From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 73499A00BE; Mon, 16 May 2022 19:27:34 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1FC3D40A7A; Mon, 16 May 2022 19:27:34 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id A28464068B for ; Mon, 16 May 2022 19:27:32 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 24GBCUne024067 for ; Mon, 16 May 2022 10:27:31 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=xsRobAbooIcvghiNMM9RFyYDteblbhMdq22DmmBxY8I=; b=HQ5/qwrikl8i9BVcZslARn5vmQKOdEj9oBBszy0UuCLAuQjdsrOcLGBEA0KMOPfYdCSf xu8yckA9OEwu/dA9xRoplWxJHmB+EntfdE1E1AUf8iwGsFwbRKesozSAaEKV6q2SDn1D TQzorPbN7Cj0D6dPEsArXPiSbUACS7T2Pc3tkLC1E7MqPRZm/q1Ddad4YfkmRjntlSSa fj4mYDQjoMFX4n5FSueIt0NzdFcWK3nQw+PNE4LNcgFtPxXGZSXoijplgn7yTY/PKDoy NkX1VU1aplfPFfYf+sawSHPnww0wwFtjW7RAvliQs0LRtDHBz6VAF1Pnnrpid2glyUFr fg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3g2bxsqxgb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 16 May 2022 10:27:30 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 16 May 2022 10:27:27 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 16 May 2022 10:27:27 -0700 Received: from ml-host-33.caveonetworks.com (unknown [10.110.143.233]) by maili.marvell.com (Postfix) with ESMTP id 452E83F70CB; Mon, 16 May 2022 10:27:27 -0700 (PDT) From: Srikanth Yalavarthi To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , , "Srikanth Yalavarthi" Subject: [PATCH v2 1/1] common/cnxk: added new macros to platform layer Date: Mon, 16 May 2022 10:26:56 -0700 Message-ID: <20220516172656.22333-1-syalavarthi@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220412174224.13143-1-syalavarthi@marvell.com> References: <20220412174224.13143-1-syalavarthi@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-ORIG-GUID: 5arYK7om2WygSwWwUBWtxhLk1a7rORe2 X-Proofpoint-GUID: 5arYK7om2WygSwWwUBWtxhLk1a7rORe2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-16_15,2022-05-16_02,2022-02-23_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added new platform layer macros for pointer operations, bitwise operations, spinlocks and 32 bit read and write. Signed-off-by: Srikanth Yalavarthi --- drivers/common/cnxk/roc_platform.h | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h index 86987aea3b..1ad3c16705 100644 --- a/drivers/common/cnxk/roc_platform.h +++ b/drivers/common/cnxk/roc_platform.h @@ -41,6 +41,7 @@ #define PLT_MEMZONE_NAMESIZE RTE_MEMZONE_NAMESIZE #define PLT_STD_C11 RTE_STD_C11 #define PLT_PTR_ADD RTE_PTR_ADD +#define PLT_PTR_SUB RTE_PTR_SUB #define PLT_PTR_DIFF RTE_PTR_DIFF #define PLT_MAX_RXTX_INTR_VEC_ID RTE_MAX_RXTX_INTR_VEC_ID #define PLT_INTR_VEC_RXTX_OFFSET RTE_INTR_VEC_RXTX_OFFSET @@ -70,6 +71,10 @@ #define PLT_U32_CAST(val) ((uint32_t)(val)) #define PLT_U16_CAST(val) ((uint16_t)(val)) +/* Add / Sub pointer with scalar and cast to uint64_t */ +#define PLT_PTR_ADD_U64_CAST(__ptr, __x) PLT_U64_CAST(PLT_PTR_ADD(__ptr, __x)) +#define PLT_PTR_SUB_U64_CAST(__ptr, __x) PLT_U64_CAST(PLT_PTR_SUB(__ptr, __x)) + /** Divide ceil */ #define PLT_DIV_CEIL(x, y) \ ({ \ @@ -113,10 +118,11 @@ #define plt_bitmap_scan rte_bitmap_scan #define plt_bitmap_get_memory_footprint rte_bitmap_get_memory_footprint -#define plt_spinlock_t rte_spinlock_t -#define plt_spinlock_init rte_spinlock_init -#define plt_spinlock_lock rte_spinlock_lock -#define plt_spinlock_unlock rte_spinlock_unlock +#define plt_spinlock_t rte_spinlock_t +#define plt_spinlock_init rte_spinlock_init +#define plt_spinlock_lock rte_spinlock_lock +#define plt_spinlock_unlock rte_spinlock_unlock +#define plt_spinlock_trylock rte_spinlock_trylock #define plt_intr_callback_register rte_intr_callback_register #define plt_intr_callback_unregister rte_intr_callback_unregister @@ -165,12 +171,24 @@ #define plt_write64(val, addr) \ rte_write64_relaxed((val), (volatile void *)(addr)) +#define plt_read32(addr) rte_read32_relaxed((volatile void *)(addr)) +#define plt_write32(val, addr) \ + rte_write32_relaxed((val), (volatile void *)(addr)) + #define plt_wmb() rte_wmb() #define plt_rmb() rte_rmb() #define plt_io_wmb() rte_io_wmb() #define plt_io_rmb() rte_io_rmb() #define plt_atomic_thread_fence rte_atomic_thread_fence +#define plt_bit_relaxed_get32 rte_bit_relaxed_get32 +#define plt_bit_relaxed_set32 rte_bit_relaxed_set32 +#define plt_bit_relaxed_clear32 rte_bit_relaxed_clear32 + +#define plt_bit_relaxed_get64 rte_bit_relaxed_get64 +#define plt_bit_relaxed_set64 rte_bit_relaxed_set64 +#define plt_bit_relaxed_clear64 rte_bit_relaxed_clear64 + #define plt_mmap mmap #define PLT_PROT_READ PROT_READ #define PLT_PROT_WRITE PROT_WRITE -- 2.17.1