From: Rahul Bhansali <rbhansali@marvell.com>
To: <dev@dpdk.org>, Nithin Dabilpuram <ndabilpuram@marvell.com>,
Kiran Kumar K <kirankumark@marvell.com>,
Sunil Kumar Kori <skori@marvell.com>,
Satha Rao <skoteshwar@marvell.com>
Cc: <jerinj@marvell.com>, Rahul Bhansali <rbhansali@marvell.com>
Subject: [PATCH 1/2] common/cnxk: decrypt packet count register update
Date: Fri, 20 May 2022 10:52:29 +0530 [thread overview]
Message-ID: <20220520052230.3680344-1-rbhansali@marvell.com> (raw)
Corrects the CPT decrypt packet counter register.
Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
drivers/common/cnxk/roc_cpt_debug.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/common/cnxk/roc_cpt_debug.c b/drivers/common/cnxk/roc_cpt_debug.c
index 847d969268..be6ddb56aa 100644
--- a/drivers/common/cnxk/roc_cpt_debug.c
+++ b/drivers/common/cnxk/roc_cpt_debug.c
@@ -200,7 +200,7 @@ cpt_lf_print(struct roc_cpt_lf *lf)
reg_val = plt_read64(lf->rbase + CPT_LF_CTX_DEC_BYTE_CNT);
plt_print(" Decrypted byte count:\t%" PRIu64, reg_val);
- reg_val = plt_read64(lf->rbase + CPT_LF_CTX_ENC_PKT_CNT);
+ reg_val = plt_read64(lf->rbase + CPT_LF_CTX_DEC_PKT_CNT);
plt_print(" Decrypted packet count:\t%" PRIu64, reg_val);
}
--
2.25.1
next reply other threads:[~2022-05-20 5:22 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-20 5:22 Rahul Bhansali [this message]
2022-05-20 5:22 ` [PATCH 2/2] common/cnxk: print NIX inline outbound CPT LF registers Rahul Bhansali
2022-05-24 15:13 ` Ray Kinsella
2022-06-15 12:28 ` Jerin Jacob
2022-06-15 12:28 ` [PATCH 1/2] common/cnxk: decrypt packet count register update Jerin Jacob
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