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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.235 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.235; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.235) by CO1NAM11FT043.mail.protection.outlook.com (10.13.174.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5273.14 via Frontend Transport; Tue, 24 May 2022 15:20:59 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Tue, 24 May 2022 15:20:58 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 24 May 2022 08:20:56 -0700 From: Spike Du To: , , , CC: , Subject: [PATCH v3 0/7] introduce per-queue limit watermark and host shaper Date: Tue, 24 May 2022 18:20:34 +0300 Message-ID: <20220524152041.737154-1-spiked@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220522055900.417282-1-spiked@nvidia.com> References: <20220522055900.417282-1-spiked@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a7f8a260-0f9e-4de0-e0bb-08da3d9901b4 X-MS-TrafficTypeDiagnostic: MN2PR12MB3214:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 May 2022 15:20:59.3174 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a7f8a260-0f9e-4de0-e0bb-08da3d9901b4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT043.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3214 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org LWM(limit watermark) is per RX queue attribute, when RX queue fullness reach the LWM limit, HW sends an event to dpdk application. Host shaper can configure shaper rate and lwm-triggered for a host port. The shaper limits the rate of traffic from host port to wire port. If lwm-triggered is enabled, a 100Mbps shaper is enabled automatically when one of the host port's Rx queues receives LWM event. These two features can combine to control traffic from host port to wire port. The work flow is configure LWM to RX queue and enable lwm-triggered flag in host shaper, after receiving LWM event, delay a while until RX queue is empty , then disable the shaper. We recycle this work flow to reduce RX queue drops. Add new libethdev API to set LWM, add rte event RTE_ETH_EVENT_RXQ_LIMIT_REACHED to handle LWM event. For host shaper, because it doesn't align to existing DPDK framework and is specific to Nvidia NIC, use PMD private API. For integration with testpmd, put the private cmdline function and LWM event handler in mlx5 PMD directory by adding a new file mlx5_test.c. Only add minimal code in testpmd to invoke interfaces from mlx5_test.c. Spike Du (7): net/mlx5: add LWM support for Rxq common/mlx5: share interrupt management ethdev: introduce Rx queue based limit watermark net/mlx5: add LWM event handling support net/mlx5: support Rx queue based limit watermark net/mlx5: add private API to config host port shaper app/testpmd: add LWM and Host Shaper command app/test-pmd/cmdline.c | 74 +++++ app/test-pmd/config.c | 21 ++ app/test-pmd/meson.build | 4 + app/test-pmd/testpmd.c | 24 ++ app/test-pmd/testpmd.h | 1 + doc/guides/nics/mlx5.rst | 84 ++++++ doc/guides/rel_notes/release_22_07.rst | 2 + drivers/common/mlx5/linux/meson.build | 13 + drivers/common/mlx5/linux/mlx5_common_os.c | 131 +++++++++ drivers/common/mlx5/linux/mlx5_common_os.h | 11 + drivers/common/mlx5/mlx5_prm.h | 26 ++ drivers/common/mlx5/version.map | 2 + drivers/common/mlx5/windows/mlx5_common_os.h | 24 ++ drivers/net/mlx5/linux/mlx5_ethdev_os.c | 71 ----- drivers/net/mlx5/linux/mlx5_os.c | 132 ++------- drivers/net/mlx5/linux/mlx5_socket.c | 53 +--- drivers/net/mlx5/mlx5.c | 68 +++++ drivers/net/mlx5/mlx5.h | 12 +- drivers/net/mlx5/mlx5_devx.c | 60 +++- drivers/net/mlx5/mlx5_devx.h | 1 + drivers/net/mlx5/mlx5_rx.c | 292 +++++++++++++++++++ drivers/net/mlx5/mlx5_rx.h | 13 + drivers/net/mlx5/mlx5_testpmd.c | 184 ++++++++++++ drivers/net/mlx5/mlx5_testpmd.h | 27 ++ drivers/net/mlx5/mlx5_txpp.c | 28 +- drivers/net/mlx5/rte_pmd_mlx5.h | 30 ++ drivers/net/mlx5/version.map | 2 + drivers/net/mlx5/windows/mlx5_ethdev_os.c | 22 -- drivers/vdpa/mlx5/mlx5_vdpa_virtq.c | 48 +-- lib/ethdev/ethdev_driver.h | 22 ++ lib/ethdev/rte_ethdev.c | 52 ++++ lib/ethdev/rte_ethdev.h | 71 +++++ lib/ethdev/version.map | 2 + 33 files changed, 1299 insertions(+), 308 deletions(-) create mode 100644 drivers/net/mlx5/mlx5_testpmd.c create mode 100644 drivers/net/mlx5/mlx5_testpmd.h -- 2.27.0